I've got a 16F18326 running at 32MHz. I want the SPI to run as quickly as possible as it sucks power during the data transfer and I am running on batteries. Would this be the way to go?
is both the #define and the spimode line needed? Would spimode masterfast work just as well?
(I am finding the ASM difficult to interpret due to all the "select case" statements)
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MASTERSLOW, or, MASTER or MASTERFAST or MASTERULTRAFAST for specific AVRs only or MasterSSPADDMode for specific PICs SSPADD support
This constant sets the library to the desire SPI fequency, therefore enable adaption of the SPI frequency without have to change the library. "
It would nice to know what the "desire SPI frequency" the library decides you want.
Basically what would be nice to know is if you are working at 32 MHz clock frequency and you set MasterSSADDMode what is the baud rate.
Indeed what would be the baud rate at a given clock frequency in each of the modes.
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Are you asking so you can improve the Help ? So, others learn from the insights?
Or, is this specific to some chip / solution?
I would have to look and document what has been written - the SPI code supports PIC (legacy mode and K mode), AVR and LGT. I remember that each has a specific approach to calculating and setting the hardware SPI.
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I'm asking because I want to know. Remember I was the one who pointed out that the I2C baud rate calculation was wrong (and for some clock rates set ridiculously slow) .
Hope you don't mind me being blunt I know from experience you also can be very blunt.
I would try to work it out for myself (and it looks like I might have to), but the problem is obfuscated as at the assembly stage as there are IFs and CASEs. Surely the parameters selected for SPI should have been firmly set in the basic compiler and not left to the ASM stage - does this not add code bloat.
It would be nice if the baud rate could be set (as it can be for I2C) rather than these somewhat vague terms slow, fast, sspadd, ultrafast.
From the ASM it looks like SSP1ADD is set =1. This would make the transfer rate 4 Mbaud (at Fosc=32MHz)- is this realistic? I don't think it is going that fast.
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the following is the intended frequencies for a clock frequency of 32
MasterSSPADDMode 31250Hz ( SSP1ADD=0xFF) to 400000Hz ( SSP1ADD=0x01) .
Where SSP1CON.SSPM = 0b1010 equates to SPI Host mode, clock = FOSC/(4 * (SPPxADD+1)) Where Great Cow BASIC sets SSP1ADD = 0x01 to give 400000Hz
MasterFast 8000000Hz
I am ignoring the other frequencies for now.
Hope this helps.
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Some testing. The results look correct based upon my previous post. I have used a sister chip but the code will be the same. I have measure the clock frequency.
I think it is worth pointing out.. there is no SPI frequency calculator for these chips. There is a SPI frequency calculator for the K mode chips. Maybe someone should add.
Last edit: Anobium 2022-05-18
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Thanks for taking the time to look into this. So 4 Mb/s with ssp1add=1.
I am going to dust off my oscilloscope and check this, but if true it is something else is slowing down my data transfer - I will have to check other stuff.
Can SSP1ADD=0x00 be used (should give 8 Mbaud).
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I don't know. The calc would make 8Mbaud but how would the chip know the process of roll-over? I looked at the MPLAB IDE. Permitted values 1=>..<=255. So, this would tell me 1 is the minimum. But, try it.. nothing to lose.
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I've started looking at my code as it seems SPI is running really fast so that is not the problem.
I'm communicating with a Waveshare 2.9" e-paper display.
I've come to the realization that I should be scanning in the y-direction as this will probably speed up the transfer about 3-fold (with auto y increment) - I'm currently scanning with auto x-increment (x is the shorter axis).
Thanks for the help it has got me thinking through the problem more carefully.
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I've got a 16F18326 running at 32MHz. I want the SPI to run as quickly as possible as it sucks power during the data transfer and I am running on batteries. Would this be the way to go?
is both the #define and the spimode line needed? Would spimode masterfast work just as well?
(I am finding the ASM difficult to interpret due to all the "select case" statements)
Just call SPIMODE there is no need for the constant or to change the registers.
The Help is the best resource for this.
So this is what the help says...
"The options for HWSPIMode are:
MASTERSLOW, or, MASTER or MASTERFAST or MASTERULTRAFAST for specific AVRs only or MasterSSPADDMode for specific PICs SSPADD support
This constant sets the library to the desire SPI fequency, therefore enable adaption of the SPI frequency without have to change the library. "
It would nice to know what the "desire SPI frequency" the library decides you want.
Basically what would be nice to know is if you are working at 32 MHz clock frequency and you set MasterSSADDMode what is the baud rate.
Indeed what would be the baud rate at a given clock frequency in each of the modes.
So, I get the answer right.
Are you asking so you can improve the Help ? So, others learn from the insights?
Or, is this specific to some chip / solution?
I would have to look and document what has been written - the SPI code supports PIC (legacy mode and K mode), AVR and LGT. I remember that each has a specific approach to calculating and setting the hardware SPI.
I'm asking because I want to know. Remember I was the one who pointed out that the I2C baud rate calculation was wrong (and for some clock rates set ridiculously slow) .
Hope you don't mind me being blunt I know from experience you also can be very blunt.
I would try to work it out for myself (and it looks like I might have to), but the problem is obfuscated as at the assembly stage as there are IFs and CASEs. Surely the parameters selected for SPI should have been firmly set in the basic compiler and not left to the ASM stage - does this not add code bloat.
It would be nice if the baud rate could be set (as it can be for I2C) rather than these somewhat vague terms slow, fast, sspadd, ultrafast.
From the ASM it looks like SSP1ADD is set =1. This would make the transfer rate 4 Mbaud (at Fosc=32MHz)- is this realistic? I don't think it is going that fast.
As you say the #IFs do support many chips and it all processed by the compiler during processing not using the ASM stage.
Willing to help. What chip are you using? The discussion is very specific to the chip.
I have just spotted the 16F18326 in the first post.
For the program
the following is the intended frequencies for a clock frequency of 32
MasterSSPADDMode 31250Hz ( SSP1ADD=0xFF) to 400000Hz ( SSP1ADD=0x01) .
Where SSP1CON.SSPM = 0b1010 equates to SPI Host mode, clock = FOSC/(4 * (SPPxADD+1)) Where Great Cow BASIC sets SSP1ADD = 0x01 to give 400000Hz
MasterFast 8000000Hz
I am ignoring the other frequencies for now.
Hope this helps.
Some testing. The results look correct based upon my previous post. I have used a sister chip but the code will be the same. I have measure the clock frequency.
I think it is worth pointing out.. there is no SPI frequency calculator for these chips. There is a SPI frequency calculator for the K mode chips. Maybe someone should add.
Last edit: Anobium 2022-05-18
Thanks for taking the time to look into this. So 4 Mb/s with ssp1add=1.
I am going to dust off my oscilloscope and check this, but if true it is something else is slowing down my data transfer - I will have to check other stuff.
Can SSP1ADD=0x00 be used (should give 8 Mbaud).
I don't know. The calc would make 8Mbaud but how would the chip know the process of roll-over? I looked at the MPLAB IDE. Permitted values 1=>..<=255. So, this would tell me 1 is the minimum. But, try it.. nothing to lose.
I've started looking at my code as it seems SPI is running really fast so that is not the problem.
I'm communicating with a Waveshare 2.9" e-paper display.
I've come to the realization that I should be scanning in the y-direction as this will probably speed up the transfer about 3-fold (with auto y increment) - I'm currently scanning with auto x-increment (x is the shorter axis).
Thanks for the help it has got me thinking through the problem more carefully.