The 18fxxk20 and 18fxxk22 .dat generation files look good with IntOsc = 64, 32, ... now added.
Simple HSerSend test for 18f46k22 is all good. Perusal of .asm files and OSCCON and PLLEN (when needed) bits are being set properly.
Simple HSerSend test for 18f46k20 is NOTGOOD. I am going to chalk this up to a typo? in the logic. Why? because the OSSCON value in INITSYS is off by dec 32 across the whole range of chipmhz values PLLEN bit seems OK.
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So, the 18fxxk20 and 18fxxk22 .dat files are good. We have a robust method to create the .dat files - so, I am pleased about this.
18f46k22 looks good and therefore we may have resolved the setup of this class of chips.
18f46k20 is not correct. We reword the initialisation routines using the new commands in the distribution emails - therefore not a typo - the setup for this chip class is therefore incorrect at the moment. Clarify please: OSSCON is off by 32.... left or right? and, which frequencies are correct? I think you are saying 32 and 64 are good and other below 32 are incorrect. What is the OSCCON set to now using RC6 and what should it be? This info really helps us.
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Please test the following for the 18f46k20. Within RC6, only RC6 add the following to your user program please, add the same to k22 to be sure it does not break that chip.
OK then, after dropping Evan's new system.h in the RC6 bucket, all is well with the 18f46k20. Actual compiled INITSYS, IRCF and PLLEN bits are as expected across the above table range. Made sure by testing HSerPrint at 9600 baud at 1-64 MHZ and that checks out too. Well done, thank you.
Back tested 18f46k22 and everything is still good.
Decided to throw in a 18f4620 for the heck of it. Whoops, will start a new thread.
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The 18fxxk20 and 18fxxk22 .dat generation files look good with IntOsc = 64, 32, ... now added.
Simple HSerSend test for 18f46k22 is all good. Perusal of .asm files and OSCCON and PLLEN (when needed) bits are being set properly.
Simple HSerSend test for 18f46k20 is NOTGOOD. I am going to chalk this up to a typo? in the logic. Why? because the OSSCON value in INITSYS is off by dec 32 across the whole range of chipmhz values PLLEN bit seems OK.
OK.
So, the 18fxxk20 and 18fxxk22 .dat files are good. We have a robust method to create the .dat files - so, I am pleased about this.
18f46k22 looks good and therefore we may have resolved the setup of this class of chips.
18f46k20 is not correct. We reword the initialisation routines using the new commands in the distribution emails - therefore not a typo - the setup for this chip class is therefore incorrect at the moment. Clarify please: OSSCON is off by 32.... left or right? and, which frequencies are correct? I think you are saying 32 and 64 are good and other below 32 are incorrect. What is the OSCCON set to now using RC6 and what should it be? This info really helps us.
@Kent.
Please test the following for the 18f46k20. Within RC6, only RC6 add the following to your user program please, add the same to k22 to be sure it does not break that chip.
https://sourceforge.net/p/gcbasic/code/HEAD/tree/GCBASIC/trunk/include/lowlevel/system.h?format=raw
Test and report back.
I have changed the initsys - not a typo but the order of setting bits.
Ta
Last edit: Anobium 2017-09-24
Playing catch up here.
v98 RC06 - 18F46k20 OSCCON ICRF bit settings
I'll have a look at the system.h file here in a bit, and get back.
OK then, after dropping Evan's new system.h in the RC6 bucket, all is well with the 18f46k20. Actual compiled INITSYS, IRCF and PLLEN bits are as expected across the above table range. Made sure by testing HSerPrint at 9600 baud at 1-64 MHZ and that checks out too. Well done, thank you.
Back tested 18f46k22 and everything is still good.
Decided to throw in a 18f4620 for the heck of it. Whoops, will start a new thread.