Re: [Fx2lib-devel] FX2 Slave FIFO being difficult

[Ben G. <bga...@gm...>]

To start, thanks a ton for your message. I really appreciate it. As it
generally turns out with these things, the problem was simple and completely
unexpected.

While initially reworking the code, I felt that the pin assignments
could be renamed. Unfortunately, instead of changing the assignments
themselves, I decided that it would be less error-prone if I just setup
"alias" assignments from the new pin names to the old.

Naturally, I quickly forgot that I did this and went on my way reworking
the code. When I finally arrived at the point of testing and found that
things weren't working, this assignment decision was far out of my mind.
In fact, it wasn't until several days of searching that I finally came
across this and on a whim set the assignments correctly. It was at this
point that I learned that "alias" assignments don't seem to be aliases
at all. Argh! But regardless, now things seem to be working (insofar as
I can expect them to).

Now it's time for the real debugging.


Excerpts from Dennis Muhlestein's message of Wed Oct 21 17:32:40 -0400 2009:
> We have a working slave fifo controller.  The issues I had when getting 
> it up and running were with the timing of the data, the read/write 
> signals and the pktend signal.  If I recall, we had issues needing to 
> wait one cycle between asserting the FD and the fx2_slwr and/or 
> fx2_pktend.  I don't see how this would be an issue for you since you 
> aren't asserting different bytes between data though.
> 
> You might try registering your inputs/outputs and asserting the signals 
> on posedge FX2_CLK.  I'm not positive that will help but I do think the 
> FX2 may want at least a clock cycle at least before WR is asserted after 
> it deasserted the EP6_full signal.
> 
> reg [2:0] fx2_flags_reg;
> reg FIFO_WR;
> wire FIFO6_full = fx2_flags_reg[1];
> assign FX2_SLWR = ~FIFO_WR;
> always @(posedge FX2_CLK) begin
>  // resets, latches etc
>  ... else begin
>   if (!FIFO6_full) begin
>    FIFO_WR <= 1;
>   end else begin
>    FIFO_WR <= 0;
>   end
>  end
> end
> 
> Have you tried monitoring the fx2_flags on your LASER outputs?  When I 
> was debugging our system, I created a counter that counted the number of 
> times the signals went low (for a lot of inputs/outputs besides the 
> flags too) and tied that to the lights.  Eventually, I found some signal 
> that wasn't tied the way I thought it was supposed to be.
> 
> I hope to release a Verilog behavioral model of the fx2 that implements 
> slave fifo along with our slave fifo interface.  This helped me a lot 
> during debugging. As I was able to visualize what was supposed to be 
> going on instead of only having my "4 bit" LED display.
> 
> A few firmware issues:
> 
> You can't use ep6 quad and ep8 double at the same time.  They use the 
> same memory space in the FX2.  The best you can do is ep6 double/ep8 
> double.  See the TRM 1.18.

This is a good catch. Guess I forgot to check whether my desired
configuration was actually supported.

> 
> An additional note, my handle_set_interface function has this:
> 
> BOOL handle_set_interface(...) {
>  RESETTOGGLE(0x02);
>  RESETTOGGLE(0x86);
>  //.. other code
> }
> 
> Without the resets, my driver would get a timeout after a read that read 
> an odd number of packets.  In addition, I had to put my endpoints in 
> interface 1 instead of 0 because on Windows, the driver never called the 
> set_interface USB command on interface 0 and the fx2 never reset the 
> TOGGLES.  This just might be your whole issue but you'll have to test 
> and see.
This is another very good point. Excellent advice.

> 
> I'll let everyone know when I get the slave fifo interface and models 
> released.

This would be fantastic. I've just started working on my own test
harnesses. I'm omitting the FX2 for now, but it might be nice to include
if a model were readily available.

Thanks,

- Ben