#43 HCS12 CCR initialization (Port.c)


In the Freescale HCS12, all compiler variants should have the Condition Code Register initialized to something other than zero.
Setting it to zero enables some features which may not be desired by an application and should therefore be enabled specifically by the application.

There are 2 features of main concern, enabling of the XIRQ and enabling of the STOP instruction. The later is not of global consequence and needs to be handled differently.

(1) Enabling the XIRQ, by setting the control bit to zero, is a "once only" control, and is therefore "global" in its effect until the CPU is reset again. This control should only be enabled if the application specifically requires it. The control bit is bit 6 of the CCR.

(2) Enabling the STOP instruction, allows the CPU to enter the lowest power state where all osc etc are turned off and can only return from that state via an external IRQ. However this control bit is not a "one time" action and the control can be turned of again. The cpu comes out of the reset state with this control turned off, so it should follow that the CCR initialization does the same thing and leaves the programmer to turn on the feature if required. However the programmer should note that the enabling of the feature will have to be performed in every task specifically since its activation is dependant on each tasks CCR value. This control bit is bit 7 of the CCR.

Therefore I suggest the Port.c file where the 'pxPortInitialiseStack' function is defined, the value for the CCR, (line 152), should be changed to 0xC0 from 0.
This will leave these features disabled and will allow the programmer to enable them if and when they are required.



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