The vPortInstallInterruptHandler() function in the ARM_Cortex-A9 port.c file has the following:
unsigned long ulBank16 = 4 * ( ulVector / 16 );
/* Is it Edge Triggered?. */
if ( 0 != ucEdgeTriggered )
portGIC_SET( (portGIC_ICDICR_BASE(puxGICDistributorAddress + ulBank16) ),
( portGIC_READ(puxGICDistributorAddress + ulBank16) | ( 0x02 << ( ulOffset16 * 2 ) ) ) );
I think it wants to set the edge-triggered bit in the appropriate Interrupt Interrupt Configuration Register, but it looks like it is OR'ing the edge-triggered bit with the contents of the Interrupt Controller Type Register at GCDistributorAddress+4 (e.g. for "vector" 29).
This makes no sense to me. Am I missing something? Why does it read (puxGICDistributorAddress + ulBank16) and OR the edge-triggered bit into that value?
Seems like it should be something like this:
portGIC_SET( (portGIC_ICDICR_BASE(puxGICDistributorAddress + ulBank16) ), ( ( 0x02 << ( ulOffset16 * 2 ) ) ) );
There is not (yet) an official Real Time Engineers ltd maintained Cortex-A9 port. Did you get your code from the FreeRTOS Interactive site? If so, please let me know which post the code came from and I may be able to ping the authour for a reply.
I found the Cortex-A9 posting and download on the FreeRTOS Interactive site:
Did you check it against this version?
I hadn't seen that version, but it has the same edge-triggered code in vPortInstallInterruptHandler().
I have convinced myself that this is a bug in the code, but I don't think it matters for the Cortex-A9 MPCore, as ICDICR0 and ICDICR1 are read-only registers. Different implementations, e.g. single Cortex-A9 with a GIC, might have a problem.
Thanks for taking the time to mention this. I will let the authors know.
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