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#190 Demo RISCV/QEMU : Can't build for embedded profile rv32ec

v1.0 (example)
closed-invalid
nobody
None
5
2019-03-13
2019-03-13
No

Hello,

When building FreeRTOSv10.2.0, demo RISCV/QEMU, toolchain riscv64-unknown-elf-gcc, for the embedded profile rv32ec, the compilation

make CROSS_COMPILE_PREFIX=riscv64-unknown-elf ARCH_FLAGS="-march=rv32ec -mabi=ilp32e -mcmodel=medany"

fails with

./fulldemo/RegTest.S: Assembler message:
./fulldemo/RegTest.S: 55: Error: illegal operands 'li x16,0x10'
...

Indeed, in the e profile, registers x16 to x31 do not exist, and are therefore prohibited by the assembler.

For what I've seen, this is also likely to affect FreeRTOS/Source/portable/GCC/RISC-V/portASM.S

All the best

Jean-Francois

Discussion

  • Richard Barry

    Richard Barry - 2019-03-13
    • status: open --> closed-invalid
     
  • Richard Barry

    Richard Barry - 2019-03-13

    Great you are using our new RISC-V port :o) I'm going to take this as feedback rather than a bug though, as currently only the 'i' profile has been implemented. We are keen to receive this kind of feedback so we know what will be the most useful thing to implement next. Currently we are adding 64-bit support, then we can look at the 'e' profile too. Any other feedback greatly appreciated - it can be discussed in the support forum on this site.

     
  • Jean-Francois MONESTIER

    Did some test

    When building for the e profile, the preprocessor sets __riscv_32e to 1

    riscv64-unknown-elf-gcc -dM -E -march=rv32imc -mabi=ilp32 - < /dev/null | grep riscv
    #define __riscv 1
    #define __riscv_cmodel_medlow 1
    #define __riscv_float_abi_soft 1
    #define __riscv_compressed 1
    #define __riscv_mul 1
    #define __riscv_muldiv 1
    #define __riscv_xlen 32
    #define __riscv_div 1

    riscv64-unknown-elf-gcc -dM -E -march=rv32ic -mabi=ilp32 - < /dev/null | grep riscv
    #define __riscv 1
    #define __riscv_cmodel_medlow 1
    #define __riscv_float_abi_soft 1
    #define __riscv_compressed 1
    #define __riscv_xlen 32

    riscv64-unknown-elf-gcc -dM -E -march=rv32ec -mabi=ilp32e - < /dev/null | grep riscv
    #define __riscv 1
    #define __riscv_cmodel_medlow 1
    #define __riscv_float_abi_soft 1
    #define __riscv_32e 1
    #define __riscv_compressed 1
    #define __riscv_xlen 32
    #define __riscv_abi_rve 1

     

    Last edit: Jean-Francois MONESTIER 2019-03-13
  • Jean-Francois MONESTIER

    Ok Richard, thank you for the quick update !

    Best regards,

    Jean-Francois

     

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