<?xml version="1.0" encoding="utf-8"?>
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Recent changes to Home</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>Recent changes to Home</description><atom:link href="https://sourceforge.net/p/fpgasm/wiki/Home/feed" rel="self"/><language>en</language><lastBuildDate>Mon, 01 Oct 2012 21:35:32 -0000</lastBuildDate><atom:link href="https://sourceforge.net/p/fpgasm/wiki/Home/feed" rel="self" type="application/rss+xml"/><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v32
+++ v33
@@ -1,113 +1,2 @@
 You can't wait to build bare-metal FPGA circuits, so
-* Read **fpgasm in a nutshell** below
-* See [What is this](http://github.com/stacksmith/fpgasm/wiki/What-is-this) and [Getting Started](http://github.com/stacksmith/fpgasm/wiki/Getting-Started); also, [Legal Notes](http://github.com/stacksmith/fpgasm/wiki/Legal-Notes).  Also see the Documentation [Table Of Contents](http://github.com/stacksmith/fpgasm/wiki/Table-ogf-Contents).
-* Read [my blog at fpgarelated.com](http://www.fpgarelated.com/showarticle/39.php) to see why I wrote **fpgasm**.  
-
-**fpgasm** in a nutshell
-------------------------
-This is a basic tool thats allows you to define and instantiate circuits called modules.  Each [module](http://github.com/stacksmith/fpgasm/wiki/Module) contains [instances](http://github.com/stacksmith/fpgasm/wiki/Module) of other modules, along with [location](http://github.com/stacksmith/fpgasm/wiki/Location) and [Wiring](http://github.com/stacksmith/fpgasm/wiki/Wiring) information.  Eventually, your 'top' module solves your problem.  That's pretty much it - no expressions, no logical operators, no loops.
-
-Like chess, the moves are few and simple.  The game has infinite possibilities.
-
-Each module exposes "input" and "output" pins (that later will be wired up).  And there is a way to parametrize modules so that different instances of, say, a LUT, can initialize it with different values to create your logic.
-
-Here is a simple example of a module.  This module defines 4 pushbuttons on my Digilent Spartan S3 board:
-
-	//================================    
-	// Digilent Spartan S3 Demo board
-	// 4 pushbuttons
-	//================================
-	Buttons() output( OUT[4] /*Bus of 4 wires*/) {
-	  button0 InSimple loc:M13; //M13 is the FPGA pin - no ucf files needed.
-	  wire button0's OUT to my OUT[0] ; //We know that InSimple declares an OUT pin
-	  button1 InSimple loc:M14;
-	  wire button1 OUT to my OUT[1] ;
-	  button2 InSimple loc:L13;
-	  wire his OUT to my OUT[2] ; //his refers to button2
-	  button3 InSimple loc:L14;
-	  wire his OUT to my OUT[3] ; //now his refers to button3
-	}
-
-Note the wiring syntax.  Module **InSimple**, a simple input port, declares a pin **OUT**.  So we literally wire the instance's **OUT** pin to our own output pin.  You can optionally use the posessive **'s** to make your code more readable.  The module's own pins are called **my** or **our**.  **His** (or **her**) refers to the last instance declared, for convenience.
-
-
-**loc:M13** is a simple **name:value** asignment for the instance.  In this case, we are setting the instance's location.  Now, we can use the module **Buttons** as an instance inside another module:
-
-	//
-	Top() {
-	  buttons Buttons;
-	}
-
-Imagine module similar to Buttons called **Leds**, with 8 LEDs, exposing a bus of four **input** pins.  We can wire the two together up like this:
-
-	//
-	Top() {
-	  button Buttons;
-	  led Leds;
-	  wire button OUT[0:3] to led IN[0:3];   //'s are optional
-	  wire my gnd to led[4:7]; //inputs need to be connected, my gnd is GROUND
-	}
-
-This is an actual circuit that lights leds when buttons are pressed.
-
-Now let me show you how to use parameters.  Let's revisit the Buttons module definition, and set it up to allow different IO standards, such as **LVTTL** or **LVCMOS33**.
-
-	//================================    
-	// Digilent Spartan S3 Demo board
-	// 4 pushbuttons
-	//================================
-	Buttons() output(OUT[4] ) {
-	  button0 InSimple loc:M13 std:LVTTL; //InSimple exposes parameter 'std'
-	  wire his OUT to my OUT[0] ;
-	  button1 InSimple loc:M14 std:LVTTL;
-	  wire his OUT to my OUT[1] ;
-	  button2 InSimple loc:L13 std:LVTTL;
-	  wire his OUT to my OUT[2] ;
-	  button3 InSimple loc:L14 std:LVTTL;
-	  wire his OUT to my OUT[3] ; 
-	}
-
-Now the buttons will be instantiated to support **LVTTL** io standard.  To make it more generic, we can parametrize the values of **std** like this:
-
-	//================================    
-	// Digilent Spartan S3 Demo board
-	// 4 pushbuttons
-	//================================
-	Buttons(level) output(OUT[4] ) {
-	  button0 InSimple loc:M13 std:!level!; //pass on our level to InSimple's std
-	  wire his OUT to my OUT[0] ;
-	  button1 InSimple loc:M14 std:!level!;
-	  wire his OUT to my OUT[1] ;
-	  button2 InSimple loc:L13 std:!level!;
-	  wire his OUT to my OUT[2] ;
-	  button3 InSimple loc:L14 std:!level!;
-	  wire his OUT to my OUT[3] ; 
-	}
-
-Now we will need to set **level** parameter when instantiating **Buttons** like this:
-
-	//
-	Top() {
-	  button Buttons level:LVTTL; //pass on LVTTL to Buttons' level
-	  led Leds;
-	  wire button's OUT[0:3] to led's IN[0:3];
-	}
-
-Not setting level is considered an error.  To make it optional, we can introduce a default value in the **Buttons** definition like this:
-
-	//
-	Buttons(level:LVTTL) output:(OUT[4] ) {
-	  button0 InSimple loc:M13 std:!level!;
-	  ...
-
-Now we can explicitly set the **level** or default to **LVTTL** without setting it.  (InSimple does this with **std** which is why we didn't have to set it in the first example).
-
-
-	//
-	  button Buttons level:LVCMOS33;
-	    or
-	  button Buttons;  //defaults to LVTTL
-
-Now you know pretty much all the "chess moves".  To learn to play, follow some examples in **fpgasm-test** repo.
-
-
+[up-to-date info is here at github](https://github.com/stacksmith/fpgasm/wiki/aaa.-Welcome-to-fpgasm!)
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Mon, 01 Oct 2012 21:35:32 -0000</pubDate><guid>https://sourceforge.net8b27bc036ba06277b4708a935027153f047cbb63</guid></item><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v31
+++ v32
@@ -12,7 +12,7 @@
 Each module exposes "input" and "output" pins (that later will be wired up).  And there is a way to parametrize modules so that different instances of, say, a LUT, can initialize it with different values to create your logic.
 
 Here is a simple example of a module.  This module defines 4 pushbuttons on my Digilent Spartan S3 board:
-```c++
+
 	//================================    
 	// Digilent Spartan S3 Demo board
 	// 4 pushbuttons
@@ -27,7 +27,7 @@
 	  button3 InSimple loc:L14;
 	  wire his OUT to my OUT[3] ; //now his refers to button3
 	}
-```
+
 Note the wiring syntax.  Module **InSimple**, a simple input port, declares a pin **OUT**.  So we literally wire the instance's **OUT** pin to our own output pin.  You can optionally use the posessive **'s** to make your code more readable.  The module's own pins are called **my** or **our**.  **His** (or **her**) refers to the last instance declared, for convenience.
 
 
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Fri, 14 Sep 2012 00:40:56 -0000</pubDate><guid>https://sourceforge.netb687458efa571e3f75d58164ee54f8dbe4c43ed1</guid></item><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v30
+++ v31
@@ -1,82 +1,54 @@
-Welcome to FPGAsm!
+You can't wait to build bare-metal FPGA circuits, so
+* Read **fpgasm in a nutshell** below
+* See [What is this](http://github.com/stacksmith/fpgasm/wiki/What-is-this) and [Getting Started](http://github.com/stacksmith/fpgasm/wiki/Getting-Started); also, [Legal Notes](http://github.com/stacksmith/fpgasm/wiki/Legal-Notes).  Also see the Documentation [Table Of Contents](http://github.com/stacksmith/fpgasm/wiki/Table-ogf-Contents).
+* Read [my blog at fpgarelated.com](http://www.fpgarelated.com/showarticle/39.php) to see why I wrote **fpgasm**.  
 
-Also welcome to the bleeding edge. The syntax is stable, so your code should require no changes as the compiler is updated. The code and some test projects are in the download are.  See [What is this] and [Getting Started]; also, [Legal Notes].  Also see the Documentation [Table Of Contents].
+**fpgasm** in a nutshell
+------------------------
+This is a basic tool thats allows you to define and instantiate circuits called modules.  Each [module](http://github.com/stacksmith/fpgasm/wiki/Module) contains [instances](http://github.com/stacksmith/fpgasm/wiki/Module) of other modules, along with [location](http://github.com/stacksmith/fpgasm/wiki/Location) and [Wiring](http://github.com/stacksmith/fpgasm/wiki/Wiring) information.  Eventually, your 'top' module solves your problem.  That's pretty much it - no expressions, no logical operators, no loops.
 
-In the meantime, see [my blog at fpgarelated.com](http://www.fpgarelated.com/showarticle/39.php) to see why I wrote FPGAsm.  And look below for a glimpse of FPGAsm.
+Like chess, the moves are few and simple.  The game has infinite possibilities.
 
-FPGAsm in a nutshell
---------------------
-This is a basic tool thats allows you to define and instantiate modules.  Each [Module] contains [Instance]s of other modules, along with [Location] and [Wiring] information.  That's pretty much it.  Eventually, your 'top' module solves your problem.
-
-There is a little more to it.  Each module exposes "input" and "output" pins (that later will be wired up).  And there is a way to parametrize modules so that different instances of, say, a LUT, can initialize it with different values to create your logic.
+Each module exposes "input" and "output" pins (that later will be wired up).  And there is a way to parametrize modules so that different instances of, say, a LUT, can initialize it with different values to create your logic.
 
 Here is a simple example of a module.  This module defines 4 pushbuttons on my Digilent Spartan S3 board:
-
+```c++
 	//================================    
 	// Digilent Spartan S3 Demo board
 	// 4 pushbuttons
 	//================================
-	Buttons() output:(OUT0,OUT1, OUT2, OUT3 ) {
+	Buttons() output( OUT[4] /*Bus of 4 wires*/) {
 	  button0 InSimple loc:M13; //M13 is the FPGA pin - no ucf files needed.
-	  wire button0's OUT to my OUT0 ; //We know that InSimple declares an OUT pin
+	  wire button0's OUT to my OUT[0] ; //We know that InSimple declares an OUT pin
 	  button1 InSimple loc:M14;
-	  wire button1 OUT to my OUT1 ;
+	  wire button1 OUT to my OUT[1] ;
 	  button2 InSimple loc:L13;
-	  wire his OUT to my OUT2 ; //his refers to button2
+	  wire his OUT to my OUT[2] ; //his refers to button2
 	  button3 InSimple loc:L14;
-	  wire his OUT to my OUT3 ; //now his refers to button3
+	  wire his OUT to my OUT[3] ; //now his refers to button3
 	}
+```
 Note the wiring syntax.  Module **InSimple**, a simple input port, declares a pin **OUT**.  So we literally wire the instance's **OUT** pin to our own output pin.  You can optionally use the posessive **'s** to make your code more readable.  The module's own pins are called **my** or **our**.  **His** (or **her**) refers to the last instance declared, for convenience.
 
 
-**loc:M13** is a simple **name:value** asignment for the instance.  It implies an absolute location.  Because of that, only one instance of Buttons is possible.  We can invoke it so:
+**loc:M13** is a simple **name:value** asignment for the instance.  In this case, we are setting the instance's location.  Now, we can use the module **Buttons** as an instance inside another module:
 
 	//
 	Top() {
 	  buttons Buttons;
 	}
 
-Imagine a similar module called **Leds**, with four LEDs, exposing four input pins.  We can wire it up like this:
+Imagine module similar to Buttons called **Leds**, with 8 LEDs, exposing a bus of four **input** pins.  We can wire the two together up like this:
 
 	//
 	Top() {
 	  button Buttons;
 	  led Leds;
-	  wire button OUT0 to his IN0;   //his refers to led
-	  wire button OUT1 to led's IN1; //same here
-	  wire button OUT2 to led IN2;   //'s is optional
-	  wire button OUT3 to his IN3;
+	  wire button OUT[0:3] to led IN[0:3];   //'s are optional
+	  wire my gnd to led[4:7]; //inputs need to be connected, my gnd is GROUND
 	}
 
 This is an actual circuit that lights leds when buttons are pressed.
-
-It's a bit repetitive, so let me show you a shortcut:
-
-	//================================    
-	// Digilent Spartan S3 Demo board
-	// 4 pushbuttons
-	//================================
-	Buttons() output:(OUT[4] ) {
-	  button0 InSimple loc:M13;
-	  wire his OUT to my OUT[0] ;
-	  button1 InSimple loc:M14;
-	  wire his OUT to my OUT[1] ;
-	  button2 InSimple loc:L13;
-	  wire his OUT to my OUT[2] ;
-	  button3 InSimple loc:L14;
-	  wire his OUT to my OUT[3] ; 
-	}
-
-**OUT** is now a bus, with 4 wires.  In the spirit of verilog, we can refer to it with a subscript-like notation.  Assuming we fix Leds the same way, we can say:
-
-	//
-	Top() {
-	  button Buttons;
-	  led Leds;
-	  wire button's OUT[0:3] to led's IN[0:3];
-	}
-
-Buses can be wired to each other on a single line!
 
 Now let me show you how to use parameters.  Let's revisit the Buttons module definition, and set it up to allow different IO standards, such as **LVTTL** or **LVCMOS33**.
 
@@ -84,8 +56,8 @@
 	// Digilent Spartan S3 Demo board
 	// 4 pushbuttons
 	//================================
-	Buttons() output:(OUT[4] ) {
-	  button0 InSimple loc:M13 std:LVTTL;
+	Buttons() output(OUT[4] ) {
+	  button0 InSimple loc:M13 std:LVTTL; //InSimple exposes parameter 'std'
 	  wire his OUT to my OUT[0] ;
 	  button1 InSimple loc:M14 std:LVTTL;
 	  wire his OUT to my OUT[1] ;
@@ -101,8 +73,8 @@
 	// Digilent Spartan S3 Demo board
 	// 4 pushbuttons
 	//================================
-	Buttons(level) output:(OUT[4] ) {
-	  button0 InSimple loc:M13 std:!level!;
+	Buttons(level) output(OUT[4] ) {
+	  button0 InSimple loc:M13 std:!level!; //pass on our level to InSimple's std
 	  wire his OUT to my OUT[0] ;
 	  button1 InSimple loc:M14 std:!level!;
 	  wire his OUT to my OUT[1] ;
@@ -116,7 +88,7 @@
 
 	//
 	Top() {
-	  button Buttons level:LVTTL;
+	  button Buttons level:LVTTL; //pass on LVTTL to Buttons' level
 	  led Leds;
 	  wire button's OUT[0:3] to led's IN[0:3];
 	}
@@ -128,7 +100,7 @@
 	  button0 InSimple loc:M13 std:!level!;
 	  ...
 
-Now we can explicitly set the **level** or default to **LVTTL** without setting it.
+Now we can explicitly set the **level** or default to **LVTTL** without setting it.  (InSimple does this with **std** which is why we didn't have to set it in the first example).
 
 
 	//
@@ -136,8 +108,6 @@
 	    or
 	  button Buttons;  //defaults to LVTTL
 
+Now you know pretty much all the "chess moves".  To learn to play, follow some examples in **fpgasm-test** repo.
 
 
-
-[[project_admins]]
-[[download_button]]
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Thu, 13 Sep 2012 03:18:56 -0000</pubDate><guid>https://sourceforge.net614773c298884eda51e74c79c6dc1a43587ee757</guid></item><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v29
+++ v30
@@ -22,11 +22,12 @@
 	  button1 InSimple loc:M14;
 	  wire button1 OUT to my OUT1 ;
 	  button2 InSimple loc:L13;
-	  wire his OUT to my OUT2 ;
+	  wire his OUT to my OUT2 ; //his refers to button2
 	  button3 InSimple loc:L14;
-	  wire his OUT to my OUT3 ; 
+	  wire his OUT to my OUT3 ; //now his refers to button3
 	}
-Note the wiring syntax.  Module **InSimple**, a simple input port, declares a pin **OUT**.  So we literally wire the instance's **OUT** pin to our own output pin.
+Note the wiring syntax.  Module **InSimple**, a simple input port, declares a pin **OUT**.  So we literally wire the instance's **OUT** pin to our own output pin.  You can optionally use the posessive **'s** to make your code more readable.  The module's own pins are called **my** or **our**.  **His** (or **her**) refers to the last instance declared, for convenience.
+
 
 **loc:M13** is a simple **name:value** asignment for the instance.  It implies an absolute location.  Because of that, only one instance of Buttons is possible.  We can invoke it so:
 
@@ -34,8 +35,6 @@
 	Top() {
 	  buttons Buttons;
 	}
-
-You can optionally use the posessive **'s** to make your code more readable.  The module's own pins are called **my** or **our**.  **His** (or **her**) refers to the last instance invoked, for convenience.
 
 Imagine a similar module called **Leds**, with four LEDs, exposing four input pins.  We can wire it up like this:
 
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Thu, 06 Sep 2012 03:54:24 -0000</pubDate><guid>https://sourceforge.netfcd15da846be28496fb0eea3c9b5977eebe89524</guid></item><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v28
+++ v29
@@ -17,8 +17,8 @@
 	// 4 pushbuttons
 	//================================
 	Buttons() output:(OUT0,OUT1, OUT2, OUT3 ) {
-	  button0 InSimple loc:M13;
-	  wire button0's OUT to my OUT0 ;
+	  button0 InSimple loc:M13; //M13 is the FPGA pin - no ucf files needed.
+	  wire button0's OUT to my OUT0 ; //We know that InSimple declares an OUT pin
 	  button1 InSimple loc:M14;
 	  wire button1 OUT to my OUT1 ;
 	  button2 InSimple loc:L13;
@@ -26,13 +26,14 @@
 	  button3 InSimple loc:L14;
 	  wire his OUT to my OUT3 ; 
 	}
+Note the wiring syntax.  Module **InSimple**, a simple input port, declares a pin **OUT**.  So we literally wire the instance's **OUT** pin to our own output pin.
+
 **loc:M13** is a simple **name:value** asignment for the instance.  It implies an absolute location.  Because of that, only one instance of Buttons is possible.  We can invoke it so:
 
 	//
 	Top() {
 	  buttons Buttons;
 	}
-Note the wiring syntax.  Module **InSimple**, a simple input port, declares a pin **OUT**.  So we literally wire the instance's **OUT** pin to our own output pin.
 
 You can optionally use the posessive **'s** to make your code more readable.  The module's own pins are called **my** or **our**.  **His** (or **her**) refers to the last instance invoked, for convenience.
 
@@ -42,10 +43,10 @@
 	Top() {
 	  button Buttons;
 	  led Leds;
-	  wire button OUT0 to led IN0;
-	  wire button OUT1 to led IN1;
-	  wire button OUT2 to led IN2;
-	  wire button OUT3 to led IN3;
+	  wire button OUT0 to his IN0;   //his refers to led
+	  wire button OUT1 to led's IN1; //same here
+	  wire button OUT2 to led IN2;   //'s is optional
+	  wire button OUT3 to his IN3;
 	}
 
 This is an actual circuit that lights leds when buttons are pressed.
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Thu, 06 Sep 2012 03:46:59 -0000</pubDate><guid>https://sourceforge.neted01bb57a764bdd5571d188a131a56db6eb9b0f9</guid></item><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v27
+++ v28
@@ -26,17 +26,17 @@
 	  button3 InSimple loc:L14;
 	  wire his OUT to my OUT3 ; 
 	}
-*loc:M13* is a simple *name:value* asignment for the instance.  It implies an absolute location.  Because of that, only one instance of Buttons is possible.  We can invoke it so:
+**loc:M13** is a simple **name:value** asignment for the instance.  It implies an absolute location.  Because of that, only one instance of Buttons is possible.  We can invoke it so:
 
 	//
 	Top() {
 	  buttons Buttons;
 	}
-Note the wiring syntax.  Module *InSimple*, a simple input port, declares a pin *OUT*.  So we literally wire the instance's *OUT* pin to our own output pin.
+Note the wiring syntax.  Module **InSimple**, a simple input port, declares a pin **OUT**.  So we literally wire the instance's **OUT** pin to our own output pin.
 
-You can optionally use the posessive **'s** to make your code more readable.  The module's own pins are called *my* or *our*.  *His* (or *her*) refers to the last instance invoked, for convenience.
+You can optionally use the posessive **'s** to make your code more readable.  The module's own pins are called **my** or **our**.  **His** (or **her**) refers to the last instance invoked, for convenience.
 
-Imagine a similar module called 'Leds', with four LEDs, exposing four input pins.  We can wire it up like this:
+Imagine a similar module called **Leds**, with four LEDs, exposing four input pins.  We can wire it up like this:
 
 	//
 	Top() {
@@ -67,7 +67,7 @@
 	  wire his OUT to my OUT[3] ; 
 	}
 
-*OUT* is now a bus, with 4 wires.  In the spirit of verilog, we can refer to it with a subscript-like notation.  Assuming we fix Leds the same way, we can say:
+**OUT** is now a bus, with 4 wires.  In the spirit of verilog, we can refer to it with a subscript-like notation.  Assuming we fix Leds the same way, we can say:
 
 	//
 	Top() {
@@ -78,7 +78,7 @@
 
 Buses can be wired to each other on a single line!
 
-Now let me show you how to use parameters.  Let's revisit the Buttons module definition, and set it up to allow different IO standards, such as *LVTTL* or *LVCMOS33*.
+Now let me show you how to use parameters.  Let's revisit the Buttons module definition, and set it up to allow different IO standards, such as **LVTTL** or **LVCMOS33**.
 
 	//================================    
 	// Digilent Spartan S3 Demo board
@@ -95,7 +95,7 @@
 	  wire his OUT to my OUT[3] ; 
 	}
 
-Now the buttons will be instantiated to support *LVTTL* io standard.  To make it more generic, we can parametrize the values of *std* like this:
+Now the buttons will be instantiated to support **LVTTL** io standard.  To make it more generic, we can parametrize the values of **std** like this:
 
 	//================================    
 	// Digilent Spartan S3 Demo board
@@ -112,7 +112,7 @@
 	  wire his OUT to my OUT[3] ; 
 	}
 
-Now we will need to set *level* parameter when instantiating *Buttons* like this:
+Now we will need to set **level** parameter when instantiating **Buttons** like this:
 
 	//
 	Top() {
@@ -121,14 +121,14 @@
 	  wire button's OUT[0:3] to led's IN[0:3];
 	}
 
-Not setting level is considered an error.  To make it optional, we can introduce a default value in the *Buttons* definition like this:
+Not setting level is considered an error.  To make it optional, we can introduce a default value in the **Buttons** definition like this:
 
 	//
 	Buttons(level:LVTTL) output:(OUT[4] ) {
 	  button0 InSimple loc:M13 std:!level!;
 	  ...
 
-Now we can explicitly set the *level* or default to *LVTTL* without setting it.
+Now we can explicitly set the **level** or default to **LVTTL** without setting it.
 
 
 	//
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Thu, 06 Sep 2012 02:08:52 -0000</pubDate><guid>https://sourceforge.netcac903c8329df2034ee7a50e26f201287a621fdd</guid></item><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v26
+++ v27
@@ -6,7 +6,7 @@
 
 FPGAsm in a nutshell
 --------------------
-This is a basic tool thats allows you to define and instantiate modules.  Each [Module] contains[Instance]s of other modules, along with placement and [Wiring] information.  That's pretty much it.  Eventually, your 'top' module solves your problem.
+This is a basic tool thats allows you to define and instantiate modules.  Each [Module] contains [Instance]s of other modules, along with [Location] and [Wiring] information.  That's pretty much it.  Eventually, your 'top' module solves your problem.
 
 There is a little more to it.  Each module exposes "input" and "output" pins (that later will be wired up).  And there is a way to parametrize modules so that different instances of, say, a LUT, can initialize it with different values to create your logic.
 
@@ -26,16 +26,15 @@
 	  button3 InSimple loc:L14;
 	  wire his OUT to my OUT3 ; 
 	}
-loc:M13 is a simple name:value asignment for the instance.  It implies an absolute location.  Because of that, only one instance of Buttons is possible.  We can invoke it so:
+*loc:M13* is a simple *name:value* asignment for the instance.  It implies an absolute location.  Because of that, only one instance of Buttons is possible.  We can invoke it so:
 
 	//
 	Top() {
 	  buttons Buttons;
 	}
+Note the wiring syntax.  Module *InSimple*, a simple input port, declares a pin *OUT*.  So we literally wire the instance's *OUT* pin to our own output pin.
 
-Note the wiring syntax.  Module InSimple, a simple input port, declares a pin 'OUT'.  So we literally wire the instance's 'OUT' pin to our own output pin.
-
-You can optionally use the posessive 's to make your code more readable.  The module's own pins are called 'my' or 'our'.  'His' (or 'her') refers to the last instance invoked, for convenience.
+You can optionally use the posessive **'s** to make your code more readable.  The module's own pins are called *my* or *our*.  *His* (or *her*) refers to the last instance invoked, for convenience.
 
 Imagine a similar module called 'Leds', with four LEDs, exposing four input pins.  We can wire it up like this:
 
@@ -68,7 +67,7 @@
 	  wire his OUT to my OUT[3] ; 
 	}
 
-OUT is now a bus, with 4 wires.  In the spirit of verilog, we can refer to it with a subscript-like notation.  Assuming we fix Leds the same way, we can say:
+*OUT* is now a bus, with 4 wires.  In the spirit of verilog, we can refer to it with a subscript-like notation.  Assuming we fix Leds the same way, we can say:
 
 	//
 	Top() {
@@ -79,7 +78,7 @@
 
 Buses can be wired to each other on a single line!
 
-Now let me show you how to use parameters.  Let's revisit the Buttons module definition, and set it up to allow different IO standards, such as LVTTL or LVCMOS33.
+Now let me show you how to use parameters.  Let's revisit the Buttons module definition, and set it up to allow different IO standards, such as *LVTTL* or *LVCMOS33*.
 
 	//================================    
 	// Digilent Spartan S3 Demo board
@@ -96,7 +95,7 @@
 	  wire his OUT to my OUT[3] ; 
 	}
 
-Now the buttons will be instantiated to support LVTTL io standard.  To make it more generic, we can parametrize the values of std like this:
+Now the buttons will be instantiated to support *LVTTL* io standard.  To make it more generic, we can parametrize the values of *std* like this:
 
 	//================================    
 	// Digilent Spartan S3 Demo board
@@ -113,7 +112,7 @@
 	  wire his OUT to my OUT[3] ; 
 	}
 
-Now we will need to set level parameter when instantiating Buttons like this:
+Now we will need to set *level* parameter when instantiating *Buttons* like this:
 
 	//
 	Top() {
@@ -122,14 +121,14 @@
 	  wire button's OUT[0:3] to led's IN[0:3];
 	}
 
-Not setting level is considered an error.  To make it optional, we can introduce a default value in the Buttons definition like this:
+Not setting level is considered an error.  To make it optional, we can introduce a default value in the *Buttons* definition like this:
 
 	//
 	Buttons(level:LVTTL) output:(OUT[4] ) {
 	  button0 InSimple loc:M13 std:!level!;
 	  ...
 
-Now we can explicitly set the level or default to LVTTL without setting it.
+Now we can explicitly set the *level* or default to *LVTTL* without setting it.
 
 
 	//
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Thu, 06 Sep 2012 02:05:19 -0000</pubDate><guid>https://sourceforge.net2f0424f0f6b3b4da5229d2af8241a4c193ab87fb</guid></item><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v25
+++ v26
@@ -1,6 +1,6 @@
 Welcome to FPGAsm!
 
-Also welcome to the bleeding edge. The syntax is stable, so your code should require no changes as the compiler is updated. The code and some test projects are in the download are.  See [What is this] and [Getting Started]; also, [Legal Notes].  
+Also welcome to the bleeding edge. The syntax is stable, so your code should require no changes as the compiler is updated. The code and some test projects are in the download are.  See [What is this] and [Getting Started]; also, [Legal Notes].  Also see the Documentation [Table Of Contents].
 
 In the meantime, see [my blog at fpgarelated.com](http://www.fpgarelated.com/showarticle/39.php) to see why I wrote FPGAsm.  And look below for a glimpse of FPGAsm.
 
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Thu, 06 Sep 2012 02:00:28 -0000</pubDate><guid>https://sourceforge.net139a04bb08f1161cf004e97324effd264c5270fc</guid></item><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v24
+++ v25
@@ -6,7 +6,7 @@
 
 FPGAsm in a nutshell
 --------------------
-This is a basic tool thats allows you to define and instantiate modules.  Each module contains instances of other modules, along with placement and wiring information.  That's pretty much it.  Eventually, your 'top' module solves your problem.
+This is a basic tool thats allows you to define and instantiate modules.  Each [Module] contains[Instance]s of other modules, along with placement and [Wiring] information.  That's pretty much it.  Eventually, your 'top' module solves your problem.
 
 There is a little more to it.  Each module exposes "input" and "output" pins (that later will be wired up).  And there is a way to parametrize modules so that different instances of, say, a LUT, can initialize it with different values to create your logic.
 
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Thu, 06 Sep 2012 01:22:28 -0000</pubDate><guid>https://sourceforge.neta2b6e8de90984d9f5e2fd0280c51cf7fd4f64542</guid></item><item><title>WikiPage Home modified by StackSmith</title><link>https://sourceforge.net/p/fpgasm/wiki/Home/</link><description>&lt;pre&gt;--- v23
+++ v24
@@ -1,6 +1,6 @@
 Welcome to FPGAsm!
 
-Also welcome to the bleeding edge. The syntax is stable, so your code should require no changes as the compiler is updated. The code and some test projects are in the download are.  See [What is this] and [Getting Started].  
+Also welcome to the bleeding edge. The syntax is stable, so your code should require no changes as the compiler is updated. The code and some test projects are in the download are.  See [What is this] and [Getting Started]; also, [Legal Notes].  
 
 In the meantime, see [my blog at fpgarelated.com](http://www.fpgarelated.com/showarticle/39.php) to see why I wrote FPGAsm.  And look below for a glimpse of FPGAsm.
 
&lt;/pre&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">StackSmith</dc:creator><pubDate>Wed, 05 Sep 2012 02:50:47 -0000</pubDate><guid>https://sourceforge.net3d81e96753b7009e3cb7a7ee3460f2fbc9ca7e5a</guid></item></channel></rss>