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SRAM on Altera's DE2

Developers
Mani Ma
2007-10-01
2013-04-19
  • Mani Ma

    Mani Ma - 2007-10-01

    seems having real trouble interfacing with the SRAM .. I have linked push buttons directly to control signals, data/addr from switches .. And still I can't write anything ?!?

    Can someone see my bugs ??

    pin assignment:

    attribute chip_pin of SRAM_addr : signal is "AC8, AB8, Y10, W10, W8, AC7, V9, V10, AD7, AD6, AF5, AE5, AD5, AD4, AC6, AC5, AF4, AE4";
    attribute chip_pin of SRAM_data : signal is "AC10, AC9, W12, W11, AF8, AE8, AF7, AE7, Y11, AA11, AB10, AA10, AA9, AF6, AE6, AD8";
    attribute chip_pin of SRAM_we_n  : signal is "AE10";
    attribute chip_pin of SRAM_oe_n  : signal is "AD10";
    attribute chip_pin of SRAM_ub_n  : signal is "AF9";
    attribute chip_pin of SRAM_lb_n  : signal is "AE9";
    attribute chip_pin of SRAM_ce_n  : signal is "AC11";

    --    DE2 general I/O ports   
    attribute chip_pin of user_sw : signal is "V2,V1,U4,U3,T7,P2,P1,N1,A13,B13,C13,AC13,AD13,AF14,AE14,P25,N26,N25"; -- slide switch 17-0
    attribute chip_pin of user_pb_n : signal is "W26,P23,N23,G26"; --key3-0
    attribute chip_pin of LEDR : signal is "AD12,AE12,AE13,AF13,AE15,AD15,AC14,AA13,Y13,AA14,AC21,AD21,AD23,AD22,AC22,AB21,AF23,AE23"; -- red LEDs 17-0
    attribute chip_pin of LEDG : signal is "Y12,Y18,AA20,U17,U18,V18,W19,AF22,AE22"; -- green LEDs 8-0

    code i used:

    SRAM_we_n <= user_pb_n(0);
    SRAM_oe_n <= user_pb_n(1);
    SRAM_ub_n <= user_pb_n(2);
    SRAM_lb_n <= user_pb_n(3);
    SRAM_ce_n <= user_pb_n(3);
    LEDR(17 downto 15) <= user_sw(17 downto 15);
    SRAM_addr(2 downto 0) <= user_sw(17 downto 15);
    LEDG(7 downto 0) <= user_sw(7 downto 0);
    SRAM_data(7 downto 0) <= user_sw(7 downto 0) when user_pb_n(0) = '0' else (others => 'Z');
    SRAM_data(15 downto 8) <= (others =>  'Z');
    SRAM_addr(15 downto 3) <= (others =>  '0');

     
    • Mani Ma

      Mani Ma - 2007-10-01

      Ar.. stupid me..

      see the problem now..
      I have not assign any LEDs to SRAM_data(7 downto 0), LEDG(7 downto 0) <= user_sw(7 downto 0) is not enough.

      see the current revision of test.vhdl for sample, they work now ! (rev 387/388)

      Thanks to Nathan for picking it up for me :)

       

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