[Firebug-cvs] mts400/sensors/i2c HPLI2CM.nc,NONE,1.1 HPLInterrupt.nc,NONE,1.1 I2CC.nc,NONE,1.1 I2CPa
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[Firebug-cvs] mts400/sensors/i2c HPLI2CM.nc,NONE,1.1 HPLInterrupt.nc,NONE,1.1 I2CC.nc,NONE,1.1 I2CPacketC.nc,NONE,1.1 I2CPacketM.nc,NONE,1.1 I2CSwitchCmds.nc,NONE,1.1 Interrupt.nc,NONE,1.1
Update of /cvsroot/firebug/mts400/sensors/i2c
In directory sc8-pr-cvs1:/tmp/cvs-serv8640
Added Files:
HPLI2CM.nc HPLInterrupt.nc I2CC.nc I2CPacketC.nc I2CPacketM.nc
I2CSwitchCmds.nc Interrupt.nc
Log Message:
Adding the i2c driver code in stages due
to sourceforge puking on 40k add limits.
--- NEW FILE: HPLI2CM.nc ---
/* -*- Mode: C; c-basic-indent: 3; indent-tabs-mode: nil -*- */
//Mohammad Rahimi,Phil Buonadonna
module HPLI2CM {
provides {
interface StdControl;
interface I2C;
}
uses interface Interrupt;
uses interface Leds;
}
implementation {
// global variables
char state; // maintain the state of the current processx
char global_data;
#define SET_START_TX() sbi(TWCR,TWSTA)
#define CLEAR_START_TX() cbi(TWCR,TWSTA)
#define SET_STOP_TX() sbi(TWCR,TWSTO)
#define CLEAR_STOP_TX() cbi(TWCR,TWSTO)
#define I2C_ENABLE() sbi(TWCR,TWEN)
#define I2C_DISABLE() cbi(TWCR,TWEN)
#define INT_ENABLE() sbi(TWCR,TWIE)
#define INT_DISABLE() cbi(TWCR,TWIE)
#define INT_FLAG_ENABLE() sbi(TWCR,TWINT)
#define INT_FLAG_DISABLE() cbi(TWCR,TWINT)
#define ACK_ENABLE() sbi(TWCR,TWEA)
#define NACK_ENABLE() cbi(TWCR,TWEA)
#define RESET() outp(0x0,TWCR);
#define MAKE_CLOCK_OUTPUT() sbi(DDRD, 0);
#define CLOCK_HIGH() sbi(PORTD,0);
#define CLCOK_LOW() sbi(PORTD,0);
#define MAKE_DATA_INPUT() cbi(DDRD, 1);
#define DATA_PULL_UP() sbi(PORTD, 1);
#define DATA_NO_PULL_UP() cbi(PORTD, 1);
// define constants for state
enum {
IDLE = 1, // idle
MA_START, // Initiation of the Master Bus
MA_ADDRESS, // Master Transmitter,writing address
MA_DATA, // Master Transmitter,writing data
MR_DATA, // Master Receiver
ST, // Slave Transmitter
SR // Slave Receiver
};
// define TWI device status codes.
enum {
TWS_BUSERROR = 0x00,
TWS_START = 0x08,
TWS_RSTART = 0x10,
TWS_MT_SLA_ACK = 0x18,
TWS_MT_SLA_NACK = 0x20,
TWS_MT_DATA_ACK = 0x28,
TWS_MT_DATA_NACK = 0x30,
TWS_M_ARB_LOST = 0x38,
TWS_MR_SLA_ACK = 0x40,
TWS_MR_SLA_NACK = 0x48,
TWS_MR_DATA_ACK = 0x50,
TWS_MR_DATA_NACK = 0x58
};
static inline void setBitRate() // See Note, Page 205 of ATmega128 docs
{
cbi(TWSR, TWPS0);
cbi(TWSR, TWPS1);
outp(100,TWBR);
}
static inline void init()
{
//sbi(PORTD, 0); // i2c SCL,this activate pullup resistor
//sbi(PORTD, 1); // i2c SDA,this activate pullup resistor
MAKE_CLOCK_OUTPUT();
MAKE_DATA_INPUT();
CLOCK_HIGH();
DATA_PULL_UP();
RESET();
I2C_ENABLE();
INT_ENABLE(); //*********************
ACK_ENABLE();
call Interrupt.enable(); //*********************
atomic {
state = IDLE;
}
}
static inline void reset()
{
RESET();
//INT_DISABLE();
//I2C_DISABLE();
setBitRate();
init();
}
// Silly task to signal when a stop condition is completed.
task void I2C_task() {
loop_until_bit_is_clear(TWCR,TWSTO);
INT_FLAG_ENABLE();
//INT_DISABLE(); //***************
signal I2C.sendEndDone();
}
command result_t StdControl.init() {
setBitRate();
init();
return SUCCESS;
}
command result_t StdControl.start() {
return SUCCESS;
}
command result_t StdControl.stop() {
return SUCCESS;
}
command result_t I2C.sendStart() {
atomic {
state=MA_START;
}
signal I2C.sendStartDone();
return SUCCESS;
}
void sendstart()
{
SET_START_TX();
INT_FLAG_ENABLE();
}
void sendAddress()
{
outb(TWDR,global_data);
//if(state==MA_ADDRESS) CLEAR_START_TX();
CLEAR_START_TX();
INT_FLAG_ENABLE();
}
command result_t I2C.sendEnd() {
SET_STOP_TX();
//INT_FLAG_ENABLE();
post I2C_task();
return SUCCESS;
}
// For reads and writes, if the TWINT bit is clear, the TWI is
// busy or the TWI improperly initialized
command result_t I2C.read(bool ack) {
//if (bit_is_clear(TWCR,TWINT)) return FAIL;
//if(state==MR_DATA){
//INT_ENABLE(); //******************
if (ack) ACK_ENABLE();
else NACK_ENABLE();
INT_FLAG_ENABLE();
//}
return SUCCESS;
}
command result_t I2C.write(char data) {
atomic {
global_data=data;
}
//INT_ENABLE(); //******************
atomic {
if(state==MA_START) {
state=MA_ADDRESS;
sendstart();
}
if(state==MA_DATA)
{
//if(bit_is_clear(TWCR,TWINT)) return FAIL;
//call Leds.redToggle();
outb(TWDR,data);
INT_FLAG_ENABLE();
}
}
return SUCCESS;
}
default event result_t I2C.sendStartDone() {
return SUCCESS;
}
default event result_t I2C.sendEndDone() {
return SUCCESS;
}
default event result_t I2C.readDone(char data) {
return SUCCESS;
}
default event result_t I2C.writeDone(bool success) {
return SUCCESS;
}
TOSH_SIGNAL(SIG_2WIRE_SERIAL) {
uint8_t i2cState;
i2cState=inp(TWSR) & 0xF8;
INT_FLAG_DISABLE();
switch (i2cState) {
case TWS_BUSERROR:
reset();
//outb(TWCR,((1 << TWSTO) | (1 << TWINT))); // Reset TWI
break;
case TWS_START: //08
case TWS_RSTART: //10
sendAddress();
//signal I2C.sendStartDone();
break;
case TWS_MT_SLA_ACK: //18
state=MA_DATA;
signal I2C.writeDone(TRUE);
break;
case TWS_MT_DATA_ACK: //28
state=MA_DATA;
signal I2C.writeDone(TRUE);
break;
case TWS_MT_SLA_NACK: //20
signal I2C.writeDone(FALSE);
break;
case TWS_MT_DATA_NACK: //30
signal I2C.writeDone(FALSE);
break;
case TWS_MR_SLA_ACK:
state=MA_DATA;
signal I2C.writeDone(TRUE);
break;
case TWS_MR_SLA_NACK:
signal I2C.writeDone(FALSE);
break;
case TWS_MR_DATA_ACK:
case TWS_MR_DATA_NACK:
state=MA_DATA;
signal I2C.readDone(inb(TWDR));
break;
default:
//something wrong
reset();
break;
}
}
}
--- NEW FILE: HPLInterrupt.nc ---
/* tab:4
*
*
* "Copyright (c) 2000-2002 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
*/
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2002 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
/*
*
* Authors: Jason Hill, David Gay, Philip Levis
* Date last modified: 6/25/02
*
*/
// The hardware presentation layer. See hpl.h for the C side.
// Note: there's a separate C side (hpl.h) to get access to the avr macros
// The model is that HPL is stateless. If the desired interface is as stateless
// it can be implemented here (Clock, FlashBitSPI). Otherwise you should
// create a separate component
module HPLInterrupt {
provides interface Interrupt;
}
implementation
{
async command result_t Interrupt.enable() {
sei();
return SUCCESS;
}
async command bool Interrupt.disable() {
bool result = (inp(SREG) & 0x80) != 0;
cli();
return result;
}
void TOSH_interrupt_enable() __attribute__((C)) {
call Interrupt.enable();
}
bool TOSH_interrupt_disable() __attribute__((C)) {
return call Interrupt.disable();
}
}
--- NEW FILE: I2CC.nc ---
/*
*
* Authors: Phil Buonadonna, Joe Polastre, Rob Szewczyk
* Date last modified: 12/19/02
*
* Note: Modify this configuration file to choose between software or hardware
* based I2C.
*/
/* Uncomment line below to enable Hardware based I2C on the mica128 */
#define HARDWARE_I2C
configuration I2CC
{
provides {
interface StdControl;
interface I2C;
}
}
implementation {
#ifdef HARDWARE_I2C
components HPLI2CM, HPLInterrupt;
StdControl = HPLI2CM;
I2C = HPLI2CM;
HPLI2CM.Interrupt->HPLInterrupt;
#else
components I2CM;
StdControl = I2CM;
I2C = I2CM;
#endif
}
--- NEW FILE: I2CPacketC.nc ---
/* tab:4
*
*
* "Copyright (c) 2000-2002 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
*/
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2002 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
/*
*
* Authors: Joe Polastre
* Date last modified: 7/18/02
*
*/
/**
* Provides the ability to write or read a series of bytes to/from the
* I2C bus. For more information, look at the I2CPacket.ti interface
**/
configuration I2CPacketC
{
provides {
interface StdControl;
interface I2CPacket[uint8_t id];
}
}
implementation {
components I2CC,I2CPacketM,LedsC;
StdControl = I2CPacketM;
I2CPacket = I2CPacketM;
I2CPacketM.I2C -> I2CC;
I2CPacketM.I2CStdControl -> I2CC.StdControl;
I2CPacketM.Leds -> LedsC;
}
--- NEW FILE: I2CPacketM.nc ---
/* tab:4
*
*
* "Copyright (c) 2000-2002 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
*/
/*
*
* Authors: Joe Polastre, Rob Szewczyk
* Date last modified: 7/18/02
*
*/
/**
* Provides functionality for writing and reading packets on the I2C bus
*/
module I2CPacketM
{
provides {
interface StdControl;
interface I2CPacket[uint8_t id];
}
uses {
interface I2C;
interface StdControl as I2CStdControl;
interface Leds;
}
}
implementation
{
/* state of the i2c request */
enum {IDLE=99,
I2C_START_COMMAND=1,
I2C_STOP_COMMAND=2,
I2C_STOP_COMMAND_SENT=3,
I2C_WRITE_ADDRESS=10,
I2C_WRITE_DATA=11,
I2C_READ_ADDRESS=20,
I2C_READ_DATA=21,
I2C_READ_DONE=22};
enum {STOP_FLAG=0x01, /* send stop command at the end of packet? */
ACK_FLAG =0x02, /* send ack after recv a byte (except for last byte) */
ACK_END_FLAG=0x04, /* send ack after last byte recv'd */
ADDR_8BITS_FLAG=0x80, // the address is a full 8-bits with no terminating readflag
};
/**
* bytes to write to the i2c bus
*/
char* data;
/**
* length in bytes of the request
*/
char length;
/**
* current index of read/write byte
*/
char index;
/**
* current state of the i2c request
*/
char state;
/**
* destination address
*/
char addr;
/**
* store flags
*/
char flags;
/**
* cache incoming bytes : 10 is a random number
*/
char temp[10];
/**
* initialize the I2C bus and set initial state
*/
command result_t StdControl.init() {
call I2CStdControl.init();
state = IDLE;
index = 0;
return SUCCESS;
}
/**
* start the component
**/
command result_t StdControl.start() {
return SUCCESS;
}
/**
* stop the component
**/
command result_t StdControl.stop() {
return SUCCESS;
}
/**
* writes a series of bytes out to the I2C bus
*
* @param in_length number of bytes to be written to the bus
* @param in_data pointer to the data
* @param in_flags bitmask of flags (see I2CPacket.ti interface)
*
* @return returns SUCCESS if the bus is free and the request is accepted.
*/
command result_t I2CPacket.writePacket[uint8_t id](char in_length,char* in_data, char in_flags) {
if (state == IDLE)
{
/* reset variables */
addr = id;
data = in_data;
index = 0;
length = in_length;
flags = in_flags;
}
else {
return FAIL;
}
state = I2C_WRITE_ADDRESS;
if (call I2C.sendStart())
{
return SUCCESS;
}
else
{
state = IDLE;
return FAIL;
}
}
/**
* reads a series of bytes out to the I2C bus
*
* @param in_length number of bytes to be read from the bus
* @param in_flags bitmask of flags (see I2CPacket.ti interface)
*
* @return returns SUCCESS if the bus is free and the request is accepted.
*/
command result_t I2CPacket.readPacket[uint8_t id](char in_length,
char in_flags) {
if (state == IDLE)
{
addr = id;
index = 0;
length = in_length;
flags = in_flags;
}
else {
return FAIL;
}
state = I2C_READ_ADDRESS;
if (call I2C.sendStart())
{
return SUCCESS;
}
else
{
state = IDLE;
return FAIL;
}
}
/**
* notification that the start symbol was sent
**/
event result_t I2C.sendStartDone() {
if(state == I2C_WRITE_ADDRESS){
state = I2C_WRITE_DATA;
call I2C.write( (flags & ADDR_8BITS_FLAG) ? addr : ((addr << 1) + 0) );
}
else if (state == I2C_READ_ADDRESS){
state = I2C_READ_DATA;
call I2C.write( (flags & ADDR_8BITS_FLAG) ? addr : ((addr << 1) + 1) );
index++;
}
return 1;
}
/**
* notification that the stop symbol was sent
**/
event result_t I2C.sendEndDone() {
if (state == I2C_STOP_COMMAND_SENT) {
/* success! */
state = IDLE;
signal I2CPacket.writePacketDone[addr](SUCCESS);
}
else if (state == I2C_READ_DONE) {
state = IDLE;
signal I2CPacket.readPacketDone[addr](length, data);
}
return SUCCESS;
}
/**
* notification of a byte sucessfully written to the bus
**/
event result_t I2C.writeDone(bool result) {
if(result == FAIL) {
state = IDLE;
signal I2CPacket.writePacketDone[addr](FAIL);
return FAIL;
}
if ((state == I2C_WRITE_DATA) && (index < length))
{
index++;
if (index == length) {
state = I2C_STOP_COMMAND;
}
return call I2C.write(data[index-1]);
}
else if (state == I2C_STOP_COMMAND)
{
state = I2C_STOP_COMMAND_SENT;
if (flags & STOP_FLAG)
{
return call I2C.sendEnd();
}
else {
state = IDLE;
return signal I2CPacket.writePacketDone[addr](SUCCESS);
}
}
else if (state == I2C_READ_DATA)
{
if (index == length)
{
return call I2C.read((flags & ACK_END_FLAG) == ACK_END_FLAG);
}
else if (index < length)
return call I2C.read((flags & ACK_FLAG) == ACK_FLAG);
}
return SUCCESS;
}
/**
* read a byte off the bus and add it to the packet
**/
event result_t I2C.readDone(char in_data) {
temp[index-1] = in_data;
index++;
if (index == length)
call I2C.read((flags & ACK_END_FLAG) == ACK_END_FLAG);
else if (index < length)
call I2C.read((flags & ACK_FLAG) == ACK_FLAG);
else if (index > length)
{
state = I2C_READ_DONE;
data = (char*)(&temp);
if (flags & STOP_FLAG)
call I2C.sendEnd();
else
{
state = IDLE;
signal I2CPacket.readPacketDone[addr](length, data);
}
}
return SUCCESS;
}
default event result_t I2CPacket.readPacketDone[uint8_t id](char in_length, char* in_data) {
return SUCCESS;
}
default event result_t I2CPacket.writePacketDone[uint8_t id](bool result) {
return SUCCESS;
}
}
--- NEW FILE: I2CSwitchCmds.nc ---
interface I2CSwitchCmds
{
command result_t PowerSwitch(uint8_t PowerState);
/* 0 => power off; 1 => power on */
//notify that I2C power switch has been set.
//PowerState = 0 => power is off; PowerState = 1 => power is on
event result_t SwitchesSet(uint8_t PowerState); //notify that I2C switches are set
}
--- NEW FILE: Interrupt.nc ---
/* tab:4
*
*
* "Copyright (c) 2000-2002 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
*/
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2002 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
/*
* Authors: Jason Hill, David Gay, Philip Levis
* Date last modified: 6/25/02
*
*
*/
/**
* Hardware interface to enable and disable interrupts.
*/
interface Interrupt
{
/** Disables interrupts.
* @return TRUE iff interrupts were previously enabled
*/
async command bool disable();
/**
* Enables interrupts.
*
* @return SUCCESS always.
*/
async command result_t enable();
}
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