[fbt-commit] SF.net SVN: fbt:[104] trunk/bin/blackboxify_vhdl.py
Status: Beta
Brought to you by:
dave_infj
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From: <dav...@us...> - 2012-03-19 16:09:19
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Revision: 104
http://fbt.svn.sourceforge.net/fbt/?rev=104&view=rev
Author: dave_infj
Date: 2012-03-19 16:09:09 +0000 (Mon, 19 Mar 2012)
Log Message:
-----------
initial commit; make simulatable, synthesizable blackbox vhdl
Added Paths:
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trunk/bin/blackboxify_vhdl.py
Added: trunk/bin/blackboxify_vhdl.py
===================================================================
--- trunk/bin/blackboxify_vhdl.py (rev 0)
+++ trunk/bin/blackboxify_vhdl.py 2012-03-19 16:09:09 UTC (rev 104)
@@ -0,0 +1,109 @@
+#!/usr/bin/env python
+
+################################################################################
+#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
+# blackboxify_vhdl.py
+#
+# PURPOSE:
+#
+# Turn simulation VHDL netlist into a synthesizable blackbox (ie, enclose
+# simulation-only objects in translate_{off,on} pragmas.)
+#
+# $Id$
+
+from __future__ import with_statement
+from util import *
+
+import os
+import re
+import sys
+import types
+
+translate = re.compile( '^\s*--.*translate_(on|off)', re.I )
+architecture = re.compile( '^\s*architecture.*is' , re.I )
+begin = re.compile( '^\s*begin.*' , re.I )
+end = re.compile( '^\s*end.*;' , re.I )
+
+SYNTH_OFF = '-- synthesis translate_off\n'
+SYNTH_ON = '-- synthesis translate_on\n'
+
+
+def blackboxify( file ):
+ """
+ Make a simulation netlist a synthesizable blackbox as well as simulatable.
+ """
+
+ print file
+
+ # Load file, stripping out any translate pragmas
+ with open(file) as f:
+ text = [line for line in f.readlines() if not translate.search(line)]
+
+ # enclose signal declarations in translate pragmas
+ for i in xrange( len(text) ):
+ if architecture.search( text[i] ):
+ text.insert( i+1, SYNTH_OFF )
+ break
+ else:
+ print '%s: failed to find ARCHITECTURE declaration' % file
+ exit(1)
+
+ for i in xrange( i+2, len(text) ):
+ if begin.search( text[i] ):
+ text.insert( i+1, SYNTH_OFF )
+ text.insert( i , SYNTH_ON )
+ break
+ else:
+ print '%s: failed to find BEGIN declaration' % file
+ exit(1)
+
+ # add translate_on before final END
+ for i in xrange( len(text)-1, i+3, -1 ):
+ if end.search( text[i] ):
+ text.insert( i, SYNTH_ON )
+ break
+ else:
+ print '%s: failed to find final END declaration' % file
+ exit(1)
+
+ with open( file+'x', 'w' ) as f:
+ f.writelines( text )
+
+
+def main( sources ):
+ if len( sources ) == 0:
+ print "usage: blackboxify.py <source> [...]"
+ exit(0)
+
+ for source in sources:
+ blackboxify( source )
+
+if __name__ == '__main__':
+ try:
+ main(sys.argv[1:])
+ except SystemExit, e:
+ if e.code:
+ if type(e.code) is types.IntType:
+ exit(e.code)
+ else:
+ sys.stderr.write( '%s: panic: %s\n' % (prog_name(), e.code) )
+ exit(1)
Property changes on: trunk/bin/blackboxify_vhdl.py
___________________________________________________________________
Added: svn:executable
+ *
Added: svn:keywords
+ Author Date Id Revision
Added: svn:eol-style
+ native
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