[fbt-commit] SF.net SVN: fbt:[100] trunk/bin/parse_verilog.py

[<dav...@us...>]

Revision: 100
          http://fbt.svn.sourceforge.net/fbt/?rev=100&view=rev
Author:   dave_infj
Date:     2010-05-28 15:03:58 +0000 (Fri, 28 May 2010)

Log Message:
-----------
first attempt at supporting `includes

Modified Paths:
--------------
    trunk/bin/parse_verilog.py

Modified: trunk/bin/parse_verilog.py
===================================================================
--- trunk/bin/parse_verilog.py	2010-05-26 15:09:21 UTC (rev 99)
+++ trunk/bin/parse_verilog.py	2010-05-28 15:03:58 UTC (rev 100)
@@ -33,10 +33,11 @@
 import pyparsing
 from pyparsing import Literal, CaselessKeyword, Word, ZeroOrMore, OneOrMore, Combine, \
     Group, Optional, Forward, ParseException, alphas, alphanums, printables, \
-    Regex, cppStyleComment, oneOf, nestedExpr, lineno, col, line
+    Regex, cppStyleComment, oneOf, nestedExpr, quotedString, lineno, col, line
 
 import DepList
 import comp_filter
+import os
 
 debug = False
 
@@ -45,22 +46,31 @@
     Determine dependencies for a given file (verilog mode)
     """
 
-    global _src
+    global main_src
+    global this_src
     global dep_list
+    global current_module
+    global includes
 
-    _src = hdl_src       # for handle_syntax_err
     dep_list = DepList.DepList()
+    current_module = None
+    main_src = hdl_src
+    includes = [hdl_src]
 
-    # Parse the file
-    try:
-        results = parser.parseFile( hdl_src, parseAll = True )
-    except pyparsing.ParseException, e:
-        exit("""\
+    # Parse source(s)
+    for this_src in includes:
+        if this_src != hdl_src:
+            print '\t`include %s' % this_src
+
+        try:
+            results = parser.parseFile( this_src, parseAll = True )
+        except pyparsing.ParseException, e:
+            exit("""\
 %%s:%d: error: Parse exception:
       %s
 
 %s
-%s^""" % (relpath(hdl_src),
+%s^""" % (relpath(this_src),
           e.lineno,
           e,
           e.line,
@@ -93,19 +103,30 @@
             print '\n%s,' % ('    '*indent ),
 
 
+def handle_include( s, loc, toks ):
+    """
+    Handle include directives
+    """
+
+    include = toks[-1].strip( '"'+"'" )
+    includes.append( os.path.join( os.path.dirname( this_src ), include ) )
+
+
 def handle_module( s, loc, toks ):
     """
     Handle module declarations
     """
 
     global current_module
+    if this_src != main_src:
+        exit('%s: module declarations in includes not supported' % this_src)
     current_module = toks[1]
     if current_module in dep_list:
         print "%s: warning: duplicate entity %s declaration found in %s: previous in:\n\t%s" % (
-            prog_name(), current_module, relpath(_src),
+            prog_name(), current_module, relpath(main_src),
             '\n\t'.join( relpath(dep[0]) for dep in dep_list[current_module] )
             )
-    dep_list.add_dep( current_module, _src, [] )
+    dep_list.add_dep( current_module, main_src, [] )
 
 
 def handle_inst( s, loc, toks ):
@@ -114,8 +135,8 @@
     """
 
     ent, inst = toks[0], toks[-3]
-    if comp_filter.accept(ent):
-        dep_list.add_dep( current_module, _src, [ent] )
+    if current_module is not None and comp_filter.accept(ent):
+        dep_list.add_dep( current_module, main_src, [ent] )
 
 
 def handle_syntax_err( s, loc, toks ):
@@ -123,8 +144,6 @@
     Handle syntax errors
     """
 
-    global _src
-
     exit("""\
 %s:%d: error: unexpected syntax:
 
@@ -137,7 +156,7 @@
 
 If you believe this is genuinely valid Verilog, see the documentation under
 Verilog support.
-""" % ( relpath(_src),
+""" % ( relpath(this_src),
            lineno( loc, s ),
            line( loc, s ),
            ' '*(col( loc, s )-1)
@@ -165,7 +184,7 @@
               )
     directive   = Group( Combine( "`" + \
                                       oneOf("define undef ifdef ifndef else endif default_nettype "
-                                            "include resetall timescale unconnected_drive "
+                                            "resetall timescale unconnected_drive "
                                             "nounconnected_drive celldefine endcelldefine") + \
                                       restOfLineWithCont ) )
 
@@ -198,6 +217,7 @@
     func_kw     = CaselessKeyword('function')
     generate_kw = CaselessKeyword('generate')
     if_kw       = CaselessKeyword('if')
+    include_dr  = Combine( '`' + CaselessKeyword( 'include' ) )
     initial_kw  = CaselessKeyword('initial')
     join_kw     = CaselessKeyword('join')
     module_kw   = CaselessKeyword('module' ) | CaselessKeyword('primitive')
@@ -230,6 +250,7 @@
     # Statements, block statements and compound statements
     statement   = Forward()
 
+    include     = t( (include_dr + quotedString).setParseAction( handle_include ), 'include' )
     process     = t( always_kw|initial_kw, 'proc' ) + statement
     evt_ctrl    = t( (Literal('@') | Literal('#')), 'evt_ctrl' ) + (paren_group | word) + statement
     ifcond      = (t( if_kw,       'if' ) + 
@@ -261,7 +282,7 @@
     simple_stmt = t( OneOrMore(~endmodule_kw + Word(printable_less_semi)) + Literal(';'),
                      'stmt' )
     statement  << Group( ~endmodule_kw +
-                          (process | evt_ctrl | function | ifcond | case | loop |
+                          (include | process | evt_ctrl | function | ifcond | case | loop |
                            generate | block | fork | instance | simple_stmt ) )
 
     #
@@ -277,15 +298,11 @@
                       ).setParseAction( handle_module ), 'mod_hdr' )
     mod_body    = t( ZeroOrMore( statement ),    'mod_bdy' )           # Module body
     mod_footer  = t( endmodule_kw,               'mod_end' )           # End module keyword
+    module      = Group( mod_header + mod_body + mod_footer )
 
     syntax_err  = OneOrMore( Word(printables) ).setParseAction( handle_syntax_err )
-    module      = Group( (mod_header | syntax_err) +
-                          mod_body                 + 
-                         (mod_footer | syntax_err)
-                         )
+    v = ZeroOrMore( include | module | statement | syntax_err )
 
-    v = ZeroOrMore( module )
-
     # No comments, no compiler directives (which can appear anywhere in the input)
     v.ignore( cppStyleComment )
     v.ignore( directive )


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