[fbt-commit] SF.net SVN: fbt:[89] trunk/bin/tool_synth_xst.py

[<dav...@us...>]

Revision: 89
          http://fbt.svn.sourceforge.net/fbt/?rev=89&view=rev
Author:   dave_infj
Date:     2010-04-09 14:56:11 +0000 (Fri, 09 Apr 2010)

Log Message:
-----------
initial commit; preliminary XST support (via XFLOW)

Added Paths:
-----------
    trunk/bin/tool_synth_xst.py

Added: trunk/bin/tool_synth_xst.py
===================================================================
--- trunk/bin/tool_synth_xst.py	                        (rev 0)
+++ trunk/bin/tool_synth_xst.py	2010-04-09 14:56:11 UTC (rev 89)
@@ -0,0 +1,99 @@
+################################################################################
+#
+# FPGA Build Tool
+# Copyright (C) 2008  David Miller
+# 
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+# 
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+# 
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+#
+# MODULE:
+#
+# tool_synth_xst.py
+#
+# PURPOSE:
+#
+# Project writer module for Xilinx's XST synthesis tool.
+#
+# $Id$
+
+from __future__ import with_statement
+from util import *
+
+import os
+
+import tool_common
+
+
+#
+# Constants
+#
+
+# Synthesis: synplify output directory
+BUILD_DIR  = 'build'
+
+# Synthesis: synthesis commands for adding HDL source files
+def lang_flag( k ):
+    try:
+        return {'.vhd' :'vhdl    work',
+                '.vhdl':'vhdl    work',
+                '.v'   :'verilog work'}[k]
+    except:
+        raise Panic( 'unknown HDL source extension %s' % k )
+
+
+def write_project(cfg):
+    """
+    Write out an XST synthesis project from the resolved sources
+    """
+    
+    # write out the synplify project file
+    proj_file = os.path.join( cfg.output_dir, '%s.prj' % (cfg.top_ent) )
+    
+    with open( proj_file, 'w' ) as pf:
+        # Generate sources and cores list
+        srcs  = []
+        cores = []
+        for ent, hdl_src, deps, core_src, alias in cfg.resolved_list:
+            srcs.append( '%s %s' % (
+                    lang_flag(os.path.splitext(hdl_src)[1]),
+                    tool_common.rel_src(cfg, hdl_src) ) )
+
+            # If it's a core, add it to the cores list
+            if core_src:
+                cores.append( (hdl_src, core_src, alias) )
+
+        # Unpack partspec
+        part, family, pkg, speed = tool_common.parse_partspec( cfg.part )
+
+        # Write out project file.
+        #
+        # NB: Much of this is hard-coded.  The intention is to add flags as
+        # required to avoid a proliferation of used arguments.
+        
+        pf.write( """\
+# XST project file automatically generated by %s.  Do not edit!
+# $Id$
+#
+
+# source files
+%s
+
+""" % (prog_name(),
+       '\n'.join( srcs ) ) )
+
+    # Write out core rules, if any
+    if cores:
+        tool_common.write_coregen_mf( cfg, cores )
+
+


Property changes on: trunk/bin/tool_synth_xst.py
___________________________________________________________________
Added: svn:keywords
   + Author Date Id Revision
Added: svn:eol-style
   + native


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