fbt-commit Mailing List for FPGA Build Tool (Page 2)
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From: <dav...@us...> - 2010-01-15 17:29:35
|
Revision: 79
http://fbt.svn.sourceforge.net/fbt/?rev=79&view=rev
Author: dave_infj
Date: 2010-01-15 17:29:09 +0000 (Fri, 15 Jan 2010)
Log Message:
-----------
exclude "attribute x: component is" case
Modified Paths:
--------------
trunk/bin/parse_vhdl.py
Modified: trunk/bin/parse_vhdl.py
===================================================================
--- trunk/bin/parse_vhdl.py 2010-01-15 15:58:15 UTC (rev 78)
+++ trunk/bin/parse_vhdl.py 2010-01-15 17:29:09 UTC (rev 79)
@@ -99,9 +99,17 @@
deps.append( match.group('inst') )
# If it's a component decl, add it so long as it's not
- # marked to be ignored
- if comp_filter.accept(match.group('comp')):
- deps.append( match.group('comp') )
+ # marked to be ignored.
+ #
+ # Without writing a proper AST, it's not easy to discern
+ # between:
+ # component icon2
+ # and
+ # attribute syn_noprune of icon2: component is true;
+ # hence 'is' is an explicitly excluded 'component'.
+ comp = match.group('comp')
+ if comp_filter.accept(comp) and comp != 'is':
+ deps.append( comp )
dep_list.add_dep( ent, hdl_src, deps )
return dep_list
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|
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From: <dav...@us...> - 2010-01-15 15:58:22
|
Revision: 78
http://fbt.svn.sourceforge.net/fbt/?rev=78&view=rev
Author: dave_infj
Date: 2010-01-15 15:58:15 +0000 (Fri, 15 Jan 2010)
Log Message:
-----------
Parameterise vsim command
Modified Paths:
--------------
trunk/bin/Makefile.inc
Modified: trunk/bin/Makefile.inc
===================================================================
--- trunk/bin/Makefile.inc 2009-02-17 15:59:58 UTC (rev 77)
+++ trunk/bin/Makefile.inc 2010-01-15 15:58:15 UTC (rev 78)
@@ -83,6 +83,7 @@
NGOLIBPATH += cores
# Default programmes
+VSIM ?= vsim
MKVDEPS ?= mkvdeps.py
MKVPROJ ?= mkvproj.py
SYNWRAP ?= synplify_wrapper.py
@@ -147,7 +148,7 @@
make -f modelsim.mk all
irun:
- vsim -i $(SIMTOP) &
+ $(VSIM) -i $(SIMTOP) $(VSIM_OPTS) &
bitstream: $(TOP).bit
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|
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From: <dav...@us...> - 2009-02-17 16:00:04
|
Revision: 77
http://fbt.svn.sourceforge.net/fbt/?rev=77&view=rev
Author: dave_infj
Date: 2009-02-17 15:59:58 +0000 (Tue, 17 Feb 2009)
Log Message:
-----------
update make clean for ise 10
Modified Paths:
--------------
trunk/bin/Makefile.inc
Modified: trunk/bin/Makefile.inc
===================================================================
--- trunk/bin/Makefile.inc 2009-02-17 10:48:40 UTC (rev 76)
+++ trunk/bin/Makefile.inc 2009-02-17 15:59:58 UTC (rev 77)
@@ -158,7 +158,7 @@
clean:
rm -rf *~ work/ cores/ transcript vsim.wlf modelsim.mk coregen.mk \
*.{prj,prd,edf,ncf,log,synlog} build/ \
- *_{fpga_editor.out} \
+ *_{fpga_editor.out,pad.txt} xlnx_auto_0* \
*.{lst,bgn,bld,drc,map,mrp,ncd,ng[dmo],pcf} \
*.{xml,pad,par,unroutes,xpi,csv,bit,xrpt,ptwx}
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From: <dav...@us...> - 2009-02-17 10:48:45
|
Revision: 76
http://fbt.svn.sourceforge.net/fbt/?rev=76&view=rev
Author: dave_infj
Date: 2009-02-17 10:48:40 +0000 (Tue, 17 Feb 2009)
Log Message:
-----------
where coregen.mk not generated, need to mask fail of existance test
Modified Paths:
--------------
trunk/bin/Makefile.inc
Modified: trunk/bin/Makefile.inc
===================================================================
--- trunk/bin/Makefile.inc 2009-02-17 10:44:50 UTC (rev 75)
+++ trunk/bin/Makefile.inc 2009-02-17 10:48:40 UTC (rev 76)
@@ -175,7 +175,7 @@
&& perl -ne '/add_file.*"(.*)"/ && print "$$1\n"' $(TOP).prj \
|| echo FORCE )
$(MKVPROJ) synth $(SYNTH_OPTS)
- [ -f coregen.mk ] && make -f coregen.mk
+ [ -f coregen.mk ] && make -f coregen.mk || true
$(SYNWRAP) -e $(SYNPLIFY) $(TOP).prj
# The list of sources for synthesis is determined by mkvproj, so there's no
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From: <dav...@us...> - 2009-02-17 10:44:55
|
Revision: 75
http://fbt.svn.sourceforge.net/fbt/?rev=75&view=rev
Author: dave_infj
Date: 2009-02-17 10:44:50 +0000 (Tue, 17 Feb 2009)
Log Message:
-----------
make disambiguation compare against absolute pathof candidate entries
Modified Paths:
--------------
trunk/bin/mkvdeps.py
Modified: trunk/bin/mkvdeps.py
===================================================================
--- trunk/bin/mkvdeps.py 2009-01-30 13:27:58 UTC (rev 74)
+++ trunk/bin/mkvdeps.py 2009-02-17 10:44:50 UTC (rev 75)
@@ -152,7 +152,7 @@
try:
filtered_list = []
for hdl_src, deps, core_src in dep_list[ent]:
- if disambig[ent].search( hdl_src ):
+ if disambig[ent].search( os.path.abspath( hdl_src ) ):
filtered_list.append( (hdl_src, deps, core_src) )
except KeyError:
# There is no rule for this entity, which is an error.
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From: <dav...@us...> - 2009-01-30 13:28:01
|
Revision: 74
http://fbt.svn.sourceforge.net/fbt/?rev=74&view=rev
Author: dave_infj
Date: 2009-01-30 13:27:58 +0000 (Fri, 30 Jan 2009)
Log Message:
-----------
Add new target synth_list, which prints list of synthesis source files
Modified Paths:
--------------
trunk/bin/Makefile.inc
Modified: trunk/bin/Makefile.inc
===================================================================
--- trunk/bin/Makefile.inc 2008-12-23 17:09:02 UTC (rev 73)
+++ trunk/bin/Makefile.inc 2009-01-30 13:27:58 UTC (rev 74)
@@ -66,6 +66,7 @@
# sim Build and compile a simulation project
# irun Run interactive simulation
# bitstream (default target) Build bitstream
+# synth_list Print (to stdout) a list of sources (for synth)
# clean Remove all build intermediates and simulation projects
#
# $Id$
@@ -150,6 +151,9 @@
bitstream: $(TOP).bit
+synth_list:
+ @$(MKVPROJ) synth -v $(SYNTH_OPTS)
+
# Remove build intermediates
clean:
rm -rf *~ work/ cores/ transcript vsim.wlf modelsim.mk coregen.mk \
@@ -200,6 +204,6 @@
$(BITGEN) $(BITGEN_OPTS) $< $@ $(if $(POSTBUILD), && $(POSTBUILD) $@)
-.PHONY: default deps alldeps sim irun bitstream clean FORCE
+.PHONY: default deps alldeps sim irun bitstream synth_list clean FORCE
.PRECIOUS: %.edf %.ngd %.ncd %-timed.ncd %.bit
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From: <dav...@us...> - 2008-12-23 17:09:06
|
Revision: 73
http://fbt.svn.sourceforge.net/fbt/?rev=73&view=rev
Author: dave_infj
Date: 2008-12-23 17:09:02 +0000 (Tue, 23 Dec 2008)
Log Message:
-----------
Add cores as a default to NGOLIBPATH
Update alldeps: find will skip cores, build and xlnx_auto_* when recursing
Also switched from -wholename to -iname (unsure why I used -wholename in the
first place)
update depends target to cover coregen projects
Modified Paths:
--------------
trunk/bin/Makefile.inc
Modified: trunk/bin/Makefile.inc
===================================================================
--- trunk/bin/Makefile.inc 2008-12-23 17:02:44 UTC (rev 72)
+++ trunk/bin/Makefile.inc 2008-12-23 17:09:02 UTC (rev 73)
@@ -79,6 +79,7 @@
SIMLIBPATH ?= +$(VROOT)/lib .
SYNTHLIBPATH ?= +$(VROOT)/lib .
+NGOLIBPATH += cores
# Default programmes
MKVDEPS ?= mkvdeps.py
@@ -130,10 +131,13 @@
deps: .depends
alldeps:
- find $(VROOT) \( -wholename '*/work' -o \
- -wholename '*/.svn' -o \
- -wholename '*/CVS' -o \
- -wholename '*/RCS' \) -prune -o \
+ find $(VROOT) \( -iname 'work' -o \
+ -iname '.svn' -o \
+ -iname 'CVS' -o \
+ -iname 'RCS' -o \
+ -iname 'cores' -o \
+ -iname 'build' -o \
+ -iname 'xlnx_auto_0_xdb' \) -prune -o \
-type d -print -exec \
make -sf $(lastword $(MAKEFILE_LIST)) -C '{}' deps \;
@@ -159,7 +163,7 @@
# Implicit rules
#
-.depends: $(wildcard *.vhd) $(wildcard *.v)
+.depends: $(wildcard *.vhd) $(wildcard *.v) $(wildcard *.xco)
$(if $^,$(MKVDEPS) -v .)
# Synplify synthesis
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From: <dav...@us...> - 2008-12-23 17:02:54
|
Revision: 72
http://fbt.svn.sourceforge.net/fbt/?rev=72&view=rev
Author: dave_infj
Date: 2008-12-23 17:02:44 +0000 (Tue, 23 Dec 2008)
Log Message:
-----------
Remove bitld. This never belonged to fbt, but happened to be in my old
phd repo vhdl/bin directory.
Removed Paths:
-------------
trunk/bin/bitld
Deleted: trunk/bin/bitld
===================================================================
--- trunk/bin/bitld 2008-12-05 14:39:02 UTC (rev 71)
+++ trunk/bin/bitld 2008-12-23 17:02:44 UTC (rev 72)
@@ -1,57 +0,0 @@
-#!/bin/bash
-
-# Bitstream loader
-#
-# Consult impact user manual for valid values of port/device, or note the
-# values used during an interactive session. Tested against iMPACT 10.1
-#
-# $Id$
-
-PORT=usb21
-DEV=2
-IDENT=false
-
-while getopts "ip:d:h" opt; do
- case $opt in
- i) IDENT=true;;
- p) PORT=$OPTARG;;
- d) DEV=$OPTARG;;
- h) cat <<EOF
-usage: bitld [-p cable_port] [-d jtag_device_no] <filename>
-or bitld -i
-EOF
-
-EOF
- exit 0;;
- *) exit 1;;
- esac
-done
-
-shift $(($OPTIND-1))
-FILE=$1
-
-if $IDENT; then
- impact -batch <<-EOF
- setMode -bscan
- setCable -p $PORT
- identify
- quit
-EOF
-else
- if [ -z "$FILE" ]; then
- echo panic: need filename
- exit 1
- fi
-
- impact -batch >/dev/null <<-EOF
- setMode -bscan
- setCable -p $PORT
- identify
- assignFile -p $DEV -file $FILE
- program -p $DEV
- quit
-EOF
-fi
-
-
-echo \ * Done
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From: <dav...@us...> - 2008-12-05 14:39:07
|
Revision: 71
http://fbt.svn.sourceforge.net/fbt/?rev=71&view=rev
Author: dave_infj
Date: 2008-12-05 14:39:02 +0000 (Fri, 05 Dec 2008)
Log Message:
-----------
Move the example makefile into its own directory
Added Paths:
-----------
trunk/example/
trunk/example/Makefile
Removed Paths:
-------------
trunk/Makefile.example
Deleted: trunk/Makefile.example
===================================================================
--- trunk/Makefile.example 2008-12-04 22:21:59 UTC (rev 70)
+++ trunk/Makefile.example 2008-12-05 14:39:02 UTC (rev 71)
@@ -1,48 +0,0 @@
-# Example project description for mkvproj.py
-#
-# $Id$
-
-# NB: Both this example and the included makefile assume $(VROOT) points to
-# the base of your HDL tree
-
-# General parameters
-SIMTOP = backplane # top entity of simulation code
-TOP = pcix_foo # top entity of synth'able code
-PART = xc2v1000fg456-6 # Target FPGA partspec
-
-# {SIM,SYN}LIBPATH tell mkvdeps.py what paths to search for HDL sources and
-# coregen descriptions (*.xco)
-# - The + prefix indicates that mkvdeps.py should recurse into the tree
-# from that point.
-# - You can exclude a subpath by prefixing it with a -.
-# - Separate multiple entries with whitespace. Paths can span multiple
-# lines by appending \. (Make sure \ is the *last* character.)
-# - See the manual for more details.
-SIMLIBPATH = +$(VROOT)/lib +.
-SYNTHLIBPATH = $(SIMLIBPATH)
-
-# NGOLIBPATH tells ngdbuild what directories to find extra .NGO and .NGC files
-# (such as for binary cores not being automatically build by coregen.)
-NGOLIBPATH = $(VROOT)/lib/pcix/core
-
-# Disambiguation rules for simulation and synthesis take the form:
-# entity_name/regex/
-#
-# The regex is applied to the filenames of competing candidates. There should
-# be exactly one match.
-SIM_DAR = pcix_lc/x133/
-SYN_DAR = $(SIM_DAR)
-
-# Synthesis constraints
-SYN_CONSTR = pcix_lat_timing.sdc
-
-# Implementation tool options, including the implementation constraints
-NGDBUILD_OPTS = -uc $(VROOT)/lib/pcix/core/constraints-$(PART).ucf
-BITGEN_OPTS = -g DriveDone:Yes \
- -g UnusedPin:Pullup
-
-# Optional script to run on successful bitstream build
-POSTBUILD = postbuild
-
-# Include the magic (adjust path appropriately)
-include $(VROOT)/bin/Makefile.inc
Copied: trunk/example/Makefile (from rev 70, trunk/Makefile.example)
===================================================================
--- trunk/example/Makefile (rev 0)
+++ trunk/example/Makefile 2008-12-05 14:39:02 UTC (rev 71)
@@ -0,0 +1,48 @@
+# Example project description for mkvproj.py
+#
+# $Id$
+
+# NB: Both this example and the included makefile assume $(VROOT) points to
+# the base of your HDL tree
+
+# General parameters
+SIMTOP = backplane # top entity of simulation code
+TOP = pcix_foo # top entity of synth'able code
+PART = xc2v1000fg456-6 # Target FPGA partspec
+
+# {SIM,SYN}LIBPATH tell mkvdeps.py what paths to search for HDL sources and
+# coregen descriptions (*.xco)
+# - The + prefix indicates that mkvdeps.py should recurse into the tree
+# from that point.
+# - You can exclude a subpath by prefixing it with a -.
+# - Separate multiple entries with whitespace. Paths can span multiple
+# lines by appending \. (Make sure \ is the *last* character.)
+# - See the manual for more details.
+SIMLIBPATH = +$(VROOT)/lib +.
+SYNTHLIBPATH = $(SIMLIBPATH)
+
+# NGOLIBPATH tells ngdbuild what directories to find extra .NGO and .NGC files
+# (such as for binary cores not being automatically build by coregen.)
+NGOLIBPATH = $(VROOT)/lib/pcix/core
+
+# Disambiguation rules for simulation and synthesis take the form:
+# entity_name/regex/
+#
+# The regex is applied to the filenames of competing candidates. There should
+# be exactly one match.
+SIM_DAR = pcix_lc/x133/
+SYN_DAR = $(SIM_DAR)
+
+# Synthesis constraints
+SYN_CONSTR = pcix_lat_timing.sdc
+
+# Implementation tool options, including the implementation constraints
+NGDBUILD_OPTS = -uc $(VROOT)/lib/pcix/core/constraints-$(PART).ucf
+BITGEN_OPTS = -g DriveDone:Yes \
+ -g UnusedPin:Pullup
+
+# Optional script to run on successful bitstream build
+POSTBUILD = postbuild
+
+# Include the magic (adjust path appropriately)
+include $(VROOT)/bin/Makefile.inc
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From: <dav...@us...> - 2008-12-04 22:22:01
|
Revision: 70
http://fbt.svn.sourceforge.net/fbt/?rev=70&view=rev
Author: dave_infj
Date: 2008-12-04 22:21:59 +0000 (Thu, 04 Dec 2008)
Log Message:
-----------
Fix attributes (no executable, eol style, keywords only on README)
Don't want keywords on Makefile.example
Modified Paths:
--------------
trunk/README
Property Changed:
----------------
trunk/LICENCE
trunk/Makefile.example
trunk/README
Property changes on: trunk/LICENCE
___________________________________________________________________
Added: svn:eol-style
+ native
Property changes on: trunk/Makefile.example
___________________________________________________________________
Deleted: svn:executable
- *
Added: svn:eol-style
+ native
Modified: trunk/README
===================================================================
--- trunk/README 2008-12-04 22:13:48 UTC (rev 69)
+++ trunk/README 2008-12-04 22:21:59 UTC (rev 70)
@@ -1,6 +1,8 @@
FPGA Build Tools
~~~~~~~~~~~~~~~~
+$Id$
+
http://fbt.sourceforge.net
More detailed documentation can be found in the distribution archive. fbt is
Property changes on: trunk/README
___________________________________________________________________
Deleted: svn:executable
- *
Added: svn:keywords
+ Author Date Id Revision
Added: svn:eol-style
+ native
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From: <dav...@us...> - 2008-12-04 22:19:07
|
Revision: 69
http://fbt.svn.sourceforge.net/fbt/?rev=69&view=rev
Author: dave_infj
Date: 2008-12-04 22:13:48 +0000 (Thu, 04 Dec 2008)
Log Message:
-----------
Add beginnings of documentation. User manual to come.
Added Paths:
-----------
trunk/Makefile.example
trunk/README
trunk/doc/
Added: trunk/Makefile.example
===================================================================
--- trunk/Makefile.example (rev 0)
+++ trunk/Makefile.example 2008-12-04 22:13:48 UTC (rev 69)
@@ -0,0 +1,48 @@
+# Example project description for mkvproj.py
+#
+# $Id$
+
+# NB: Both this example and the included makefile assume $(VROOT) points to
+# the base of your HDL tree
+
+# General parameters
+SIMTOP = backplane # top entity of simulation code
+TOP = pcix_foo # top entity of synth'able code
+PART = xc2v1000fg456-6 # Target FPGA partspec
+
+# {SIM,SYN}LIBPATH tell mkvdeps.py what paths to search for HDL sources and
+# coregen descriptions (*.xco)
+# - The + prefix indicates that mkvdeps.py should recurse into the tree
+# from that point.
+# - You can exclude a subpath by prefixing it with a -.
+# - Separate multiple entries with whitespace. Paths can span multiple
+# lines by appending \. (Make sure \ is the *last* character.)
+# - See the manual for more details.
+SIMLIBPATH = +$(VROOT)/lib +.
+SYNTHLIBPATH = $(SIMLIBPATH)
+
+# NGOLIBPATH tells ngdbuild what directories to find extra .NGO and .NGC files
+# (such as for binary cores not being automatically build by coregen.)
+NGOLIBPATH = $(VROOT)/lib/pcix/core
+
+# Disambiguation rules for simulation and synthesis take the form:
+# entity_name/regex/
+#
+# The regex is applied to the filenames of competing candidates. There should
+# be exactly one match.
+SIM_DAR = pcix_lc/x133/
+SYN_DAR = $(SIM_DAR)
+
+# Synthesis constraints
+SYN_CONSTR = pcix_lat_timing.sdc
+
+# Implementation tool options, including the implementation constraints
+NGDBUILD_OPTS = -uc $(VROOT)/lib/pcix/core/constraints-$(PART).ucf
+BITGEN_OPTS = -g DriveDone:Yes \
+ -g UnusedPin:Pullup
+
+# Optional script to run on successful bitstream build
+POSTBUILD = postbuild
+
+# Include the magic (adjust path appropriately)
+include $(VROOT)/bin/Makefile.inc
Property changes on: trunk/Makefile.example
___________________________________________________________________
Added: svn:executable
+ *
Added: trunk/README
===================================================================
--- trunk/README (rev 0)
+++ trunk/README 2008-12-04 22:13:48 UTC (rev 69)
@@ -0,0 +1,40 @@
+FPGA Build Tools
+~~~~~~~~~~~~~~~~
+
+http://fbt.sourceforge.net
+
+More detailed documentation can be found in the distribution archive. fbt is
+distributed under the LGPL. Please let me know if you find fbt useful. For
+support, please join the fbt-support mailing list at:
+
+https://lists.sourceforge.net/lists/listinfo/fbt-support
+
+
+Quick install:
+
+1. Make sure you have required software installed (python, make etc)
+
+2. Unpack archive (you've seem to have done that)
+
+3. Add the bin subdirectory to your path as appropriate
+
+
+Quick start:
+
+1. Copy the template Makefile into your project directory
+
+2. Edit as appropriate
+
+3. Run the tool:
+ make sim # to build a simulation project
+
+ # or
+
+ make # to build bitstream
+
+
+Happy hacking,
+
+
+David <dav...@us...>
+December '08
Property changes on: trunk/README
___________________________________________________________________
Added: svn:executable
+ *
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From: <dav...@us...> - 2008-12-04 21:29:53
|
Revision: 68
http://fbt.svn.sourceforge.net/fbt/?rev=68&view=rev
Author: dave_infj
Date: 2008-12-04 21:29:49 +0000 (Thu, 04 Dec 2008)
Log Message:
-----------
Add licence guff
Modified Paths:
--------------
trunk/bin/DepList.py
trunk/bin/Makefile.inc
trunk/bin/comp_filter.py
trunk/bin/mkvdeps.py
trunk/bin/mkvproj.py
trunk/bin/parse_coregen.py
trunk/bin/parse_verilog.py
trunk/bin/parse_vhdl.py
trunk/bin/synplify_wrapper.py
trunk/bin/tool_common.py
trunk/bin/tool_sim_modelsim.py
trunk/bin/tool_synth_synplify.py
trunk/bin/util.py
Added Paths:
-----------
trunk/LICENCE
Added: trunk/LICENCE
===================================================================
--- trunk/LICENCE (rev 0)
+++ trunk/LICENCE 2008-12-04 21:29:49 UTC (rev 68)
@@ -0,0 +1,458 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL. It also counts
+ as the successor of the GNU Library Public License, version 2, hence
+ the version number 2.1.]
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+ This license, the Lesser General Public License, applies to some
+specially designated software packages--typically libraries--of the
+Free Software Foundation and other authors who decide to use it. You
+can use it too, but we suggest you first think carefully about whether
+this license or the ordinary General Public License is the better
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+ END OF TERMS AND CONDITIONS
Modified: trunk/bin/DepList.py
===================================================================
--- trunk/bin/DepList.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/DepList.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,5 +1,24 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# DepList.py
#
# PURPOSE:
Modified: trunk/bin/Makefile.inc
===================================================================
--- trunk/bin/Makefile.inc 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/Makefile.inc 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,6 +1,25 @@
# -*-makefile-*-
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# Makefile.inc
#
# Implicit rules for building VHDL and Verilog projects. Include this file
Modified: trunk/bin/comp_filter.py
===================================================================
--- trunk/bin/comp_filter.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/comp_filter.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,5 +1,24 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# comp_filter.py
#
# PURPOSE:
Modified: trunk/bin/mkvdeps.py
===================================================================
--- trunk/bin/mkvdeps.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/mkvdeps.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -2,6 +2,25 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# mkvdeps.py
#
# PURPOSE:
Modified: trunk/bin/mkvproj.py
===================================================================
--- trunk/bin/mkvproj.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/mkvproj.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -2,6 +2,25 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# mkvproj.py
#
# PURPOSE:
Modified: trunk/bin/parse_coregen.py
===================================================================
--- trunk/bin/parse_coregen.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/parse_coregen.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,5 +1,24 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# parse_coregen.py
#
# PURPOSE:
Modified: trunk/bin/parse_verilog.py
===================================================================
--- trunk/bin/parse_verilog.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/parse_verilog.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,5 +1,24 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# parse_verilog.py
#
# PURPOSE:
Modified: trunk/bin/parse_vhdl.py
===================================================================
--- trunk/bin/parse_vhdl.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/parse_vhdl.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,5 +1,24 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# parse_vhdl.py
#
# PURPOSE:
Modified: trunk/bin/synplify_wrapper.py
===================================================================
--- trunk/bin/synplify_wrapper.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/synplify_wrapper.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -2,6 +2,25 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# synplify_wrapper.py
#
# PURPOSE:
Modified: trunk/bin/tool_common.py
===================================================================
--- trunk/bin/tool_common.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/tool_common.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,5 +1,24 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# tool_common.py
#
# PURPOSE:
Modified: trunk/bin/tool_sim_modelsim.py
===================================================================
--- trunk/bin/tool_sim_modelsim.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/tool_sim_modelsim.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,5 +1,24 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# tool_sim_modelsim.py
#
# PURPOSE:
Modified: trunk/bin/tool_synth_synplify.py
===================================================================
--- trunk/bin/tool_synth_synplify.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/tool_synth_synplify.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,5 +1,24 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# tool_synth_synplify.py
#
# PURPOSE:
Modified: trunk/bin/util.py
===================================================================
--- trunk/bin/util.py 2008-12-04 18:31:17 UTC (rev 67)
+++ trunk/bin/util.py 2008-12-04 21:29:49 UTC (rev 68)
@@ -1,5 +1,24 @@
################################################################################
#
+# FPGA Build Tool
+# Copyright (C) 2008 David Miller
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# MODULE:
+#
# util.py
#
# PURPOSE:
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <dav...@us...> - 2008-12-04 18:31:23
|
Revision: 67
http://fbt.svn.sourceforge.net/fbt/?rev=67&view=rev
Author: dave_infj
Date: 2008-12-04 18:31:17 +0000 (Thu, 04 Dec 2008)
Log Message:
-----------
Big reorganisation prior to release. Apologies in advance if it breaks stuff.
To summarise:
- djm_pyhelp renamed util
- Changed function def comments into docstrings
- formalised module headers
- Modularised mkvdeps and mkvproj
- Changed how mkvproj calls the tool requested, including
how the default is set
Modularisation:
* parts of mkvdeps.py split into parse_{vhdl,verilog,coregen}.py and DepList.py
Support for other languages can be fairly easily added by adding a new module
and editing src_parser_map in mkvdeps.py.
* parts of mkvproj.py split into tool_sim_modelsim.py, tool_synth_synplify.py
and tool_common.py
Support for new project writers can be added simply by writing the appropriate
module and putting it in the right place.
tool_common contains constants and utilities required by all project writers.
The default tool for a given operation can be changed by altering the
appropriate symlink.
Modified Paths:
--------------
trunk/bin/comp_filter.py
trunk/bin/mkvdeps.py
trunk/bin/mkvproj.py
trunk/bin/synplify_wrapper.py
Added Paths:
-----------
trunk/bin/DepList.py
trunk/bin/parse_coregen.py
trunk/bin/parse_verilog.py
trunk/bin/parse_vhdl.py
trunk/bin/tool_common.py
trunk/bin/tool_sim_default.py
trunk/bin/tool_sim_modelsim.py
trunk/bin/tool_synth_default.py
trunk/bin/tool_synth_synplify.py
trunk/bin/util.py
Removed Paths:
-------------
trunk/bin/djm_pyhelp.py
Copied: trunk/bin/DepList.py (from rev 66, trunk/bin/mkvdeps.py)
===================================================================
--- trunk/bin/DepList.py (rev 0)
+++ trunk/bin/DepList.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1,143 @@
+################################################################################
+#
+# DepList.py
+#
+# PURPOSE:
+#
+# Container class which maintains candidate entities and their dependencies.
+# Functions like an ordinary dictionary, but copes with ambiguous entity
+# implementations.
+#
+# $Id$
+
+from __future__ import with_statement
+from util import *
+
+import re
+import os
+
+import tool_common
+
+
+class DepList:
+ """
+ Helper class for storing lists of entity dependencies
+
+ Usage:
+ Inputs are individual candidates added via DepList.add_dep()
+ Outputs are always sets of candidates indexed by entity
+ """
+
+ def __init__(self):
+ self.list = {}
+ # Regex for parsing dependency caches
+ self.m_deps = re.compile( '(\w+)\s*\(\s*([\w.-]+)\s*\)\s*:(.*)' )
+
+
+ def add_dep(self, ent, hdl_src, deps, core_src = '' ):
+ """
+ Add a dependency to the list
+ """
+
+ try:
+ self.list[ent].append( (hdl_src, deps, core_src) )
+ except KeyError:
+ self.list[ent] = [ (hdl_src, deps, core_src) ]
+
+
+ def merge(self, src):
+ """
+ Update a dependencies dictionary with a new entry, merging if required.
+ """
+
+ for ent, dep_rec in src.list.iteritems():
+ try:
+ self.list[ent] = self.list[ent] + dep_rec
+ except KeyError:
+ self.list[ent] = dep_rec
+
+
+ def write_deps_cache(self, df):
+ """
+ Write out the DepList in a linear .depends cache file. df is an handle
+ and must already be open.
+ """
+
+ with df:
+ df.write("""\
+# Dependencies automatically generated by %s. Do not edit!
+# $Id$
+#
+
+""" % (prog_name()) )
+
+ for ent, candidates in self.iteritems():
+ for hdl_src, deps, core_src in candidates:
+ df.write( '%s(%s): %s%s\n' % (ent,
+ os.path.basename(hdl_src),
+ os.path.basename(core_src),
+ ' '.join(deps)) )
+
+
+ def read_deps_cache(self, df, path):
+ """
+ Import depencency data from a .depends cache file. df is an handle and
+ must already be open
+ """
+
+ with df:
+ for lno, dep_line in enumerate(df):
+ # Delete any comments
+ try:
+ dep_line = dep_line[:dep_line.index('#')]
+ except ValueError:
+ pass
+ dep_line = dep_line.strip()
+ if not dep_line:
+ continue
+
+ # Parse components
+ match = self.m_deps.search(dep_line)
+ if not match:
+ raise Panic("%s:%d: invalid dependency line" %
+ ( relpath(os.path.join(path,
+ tool_common.DEPS_FILE)),
+ (lno+1) )
+ )
+ ent, hdl_src, deps = match.groups()
+ deps = deps.split()
+
+ # If deps contains a single object ending in '.xco', then it
+ # is a core reference.
+ if len(deps) == 1 and deps[0].endswith('.xco'):
+ self.add_dep( ent,
+ os.path.join(tool_common.CORES_DIR, hdl_src),
+ [], # no entity dependencies
+ os.path.join(path, deps[0] ) )
+ else:
+ self.add_dep( ent,
+ os.path.join(path, hdl_src),
+ deps )
+
+
+ def iterkeys(self):
+ return self.list.iterkeys()
+
+
+ def iteritems(self):
+ return self.list.iteritems()
+
+
+ def __iter__(self):
+ return self.iterkeys()
+
+
+ def __contains__(self, ent):
+ return ent in self.list
+
+
+ def __getitem__(self, ent):
+ return self.list[ent]
+
+
+
Property changes on: trunk/bin/DepList.py
___________________________________________________________________
Added: svn:keywords
+ Author Date Id Revision
Added: svn:eol-style
+ native
Modified: trunk/bin/comp_filter.py
===================================================================
--- trunk/bin/comp_filter.py 2008-12-01 23:31:06 UTC (rev 66)
+++ trunk/bin/comp_filter.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -1,13 +1,21 @@
################################################################################
#
-# accept():
+# comp_filter.py
#
-# Entity instances for which accept() returns False will be excluded from
-# dependency lists.
+# PURPOSE:
#
+# Provides a means for the HDL parsers to reject certain entity instantiations
+# because they are provided by third party simulation libraries
+#
# $Id$
+
def accept(comp_decl):
+ """
+ Entity instances for which accept() returns False will be excluded from
+ dependency lists.
+ """
+
if not comp_decl:
# Reject None, etc
return False
Deleted: trunk/bin/djm_pyhelp.py
===================================================================
--- trunk/bin/djm_pyhelp.py 2008-12-01 23:31:06 UTC (rev 66)
+++ trunk/bin/djm_pyhelp.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -1,110 +0,0 @@
-
-# $Id$
-
-import sys
-import os
-
-#
-# prog_name()
-#
-# Returns programme name
-def prog_name():
- return os.path.basename(sys.argv[0])
-
-
-#
-# Panic exception
-#
-# For equivalent of perl die "message"
-class Panic(Exception):
- def __init__(self, value):
- self.value = value
-
- def __str__(self):
- return "%s: panic: %s" % (prog_name(), self.value)
-
-
-# relpath.py
-# R.Barran 30/08/2004
-
-def relpath(target, base=os.curdir):
- """
- Return a relative path to the target from either the current dir or an optional base dir.
- Base can be a directory specified either as absolute or relative to current dir.
- """
-
-# check commented out: not clear this is required, djm 11/6/08
-# if not os.path.exists(target):
-# raise OSError, 'Target does not exist: '+target
-
- if not os.path.isdir(base):
- raise OSError, 'Base is not a directory or does not exist: '+base
-
- base_list = (os.path.abspath(base)).split(os.sep)
- target_list = (os.path.abspath(target)).split(os.sep)
-
- # On the windows platform the target may be on a completely different drive from the base.
- if os.name in ['nt','dos','os2'] and base_list[0] <> target_list[0]:
- raise OSError, 'Target is on a different drive to base. Target: '+target_list[0].upper()+', base: '+base_list[0].upper()
-
- # Starting from the filepath root, work out how much of the filepath is
- # shared by base and target.
- for i in range(min(len(base_list), len(target_list))):
- if base_list[i] <> target_list[i]: break
- else:
- # If we broke out of the loop, i is pointing to the first differing
- # path elements. If we didn't break out of the loop, i is pointing to
- # identical path elements. Increment i so that in all cases it points
- # to the first differing path elements.
- i+=1
-
- rel_list = [os.pardir] * (len(base_list)-i) + target_list[i:]
- return os.path.join(*rel_list)
-
-#
-# walk_dirlist()
-#
-# Conditionally walks the list of directories given. Only directories
-# beginning with a + will be searched recursively. Version control directories
-# will be filtered out along the way.
-def walk_dirlist(dirlist):
- excl_dirs = []
- for dir in dirlist:
- dir = dir.strip()
- if not dir:
- continue
-
- # Those directories with a leading - should be excluded from the walk.
- if dir.startswith('-'):
- excl_dirs.append( dir.lstrip('-') )
- continue
-
- # Only those directories with a leading + should be recursed into.
- recurse = dir.startswith('+')
- for path, dirs, files in os.walk( dir.lstrip('+') ):
- if not recurse:
- del dirs[:]
-
- # Skip revision control directories
- try:
- del dirs[dirs.index('.svn')]
- del dirs[dirs.index('CVS')]
- del dirs[dirs.index('RCS')]
- del dirs[dirs.index('work')]
- except ValueError:
- pass
-
- # Skip any excludes
- for i in reversed(xrange(len(dirs))):
- for excl in excl_dirs:
- try:
- if os.path.samefile( os.path.join(path, dirs[i]), excl ):
- del dirs[i]
- except OSError:
- sys.stderr.write( "%s: ignoring invalid ignore %s\n" % (
- prog_name(),
- excl ) )
-
- yield (path, dirs, files)
-
-
Modified: trunk/bin/mkvdeps.py
===================================================================
--- trunk/bin/mkvdeps.py 2008-12-01 23:31:06 UTC (rev 66)
+++ trunk/bin/mkvdeps.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -1,294 +1,52 @@
#!/usr/bin/python
+################################################################################
+#
+# mkvdeps.py
+#
+# PURPOSE:
+#
+# Auto depencies resolver. When used stand-alone, it will write a dependency
+# cache in the specified directories. Can be imported as a module such as to
+# provide dependency resolution in mkvproj.py.
+#
# $Id$
from __future__ import with_statement
+from util import *
+
import sys
import getopt
import re
import os
-import glob
-import comp_filter
-from djm_pyhelp import *
+import DepList
+import parse_vhdl
+import parse_verilog
+import parse_coregen
+import tool_common
-#
-# Constants
-#
-# Output directory for coregen
-CORES_DIR = 'cores'
-
-# Dependency cache file name
-DEPS_FILE = '.depends'
-
-################################################################################
-#
-# Helper class for storing lists of entity dependencies
-#
-# Usage:
-# Inputs are individual candidates added via DepList.add_dep()
-# Outputs are always sets of candidates indexed by entity
-class DepList:
- def __init__(self):
- self.list = {}
- # Regex for parsing dependency caches
- self.m_deps = re.compile( '(\w+)\s*\(\s*([\w.-]+)\s*\)\s*:(.*)' )
-
- #
- # add_dep()
- #
- # Add a dependency to the list
- def add_dep(self, ent, hdl_src, deps, core_src = '' ):
- try:
- self.list[ent].append( (hdl_src, deps, core_src) )
- except KeyError:
- self.list[ent] = [ (hdl_src, deps, core_src) ]
-
- #
- # merge_deps()
- #
- # Update a dependencies dictionary with a new entry, merging if required.
- def merge(self, src):
- for ent, dep_rec in src.list.iteritems():
- try:
- self.list[ent] = self.list[ent] + dep_rec
- except KeyError:
- self.list[ent] = dep_rec
-
- #
- # write_deps_cache()
- #
- # Write out the DepList in a linear .depends cache file. df is an handle
- # and must already be open.
- def write_deps_cache(self, df):
- with df:
- df.write("""\
-# Dependencies automatically generated by %s. Do not edit!
-# $Id$
-#
-
-""" % (prog_name()) )
-
- for ent, candidates in self.iteritems():
- for hdl_src, deps, core_src in candidates:
- df.write( '%s(%s): %s%s\n' % (ent,
- os.path.basename(hdl_src),
- os.path.basename(core_src),
- ' '.join(deps)) )
- #
- # read_deps_cache()
- #
- # Import depencency data from a .depends cache file. df is an handle and
- # must already be open
- def read_deps_cache(self, df, path):
- with df:
- for lno, dep_line in enumerate(df):
- # Delete any comments
- try:
- dep_line = dep_line[:dep_line.index('#')]
- except ValueError:
- pass
- dep_line = dep_line.strip()
- if not dep_line:
- continue
-
- # Parse components
- match = self.m_deps.search(dep_line)
- if not match:
- raise Panic("%s:%d: invalid dependency line" %
- ( relpath(os.path.join(path, DEPS_FILE)),
- (lno+1) )
- )
- ent, hdl_src, deps = match.groups()
- deps = deps.split()
-
- # If deps contains a single object ending in '.xco', then it
- # is a core reference.
- if len(deps) == 1 and deps[0].endswith('.xco'):
- self.add_dep( ent,
- os.path.join(CORES_DIR, hdl_src),
- [], # no entity dependencies
- os.path.join(path, deps[0] ) )
- else:
- self.add_dep( ent,
- os.path.join(path, hdl_src),
- deps )
-
-
- def iterkeys(self):
- return self.list.iterkeys()
-
- def iteritems(self):
- return self.list.iteritems()
-
- def __iter__(self):
- return self.iterkeys()
-
- def __contains__(self, ent):
- return ent in self.list
-
- def __getitem__(self, ent):
- return self.list[ent]
-
-
-
-################################################################################
-#
-# parse_deps_vhdl()
-#
-# Determine dependencies for a given file (VHDL mode)
-
-m_dep_vhdl = re.compile("""
- use \s+ (?P<lib> \w+) \. (?P<pkg> \w+) \.all \s* ; | # pkg import
-
- (?: entity|package) \s+ (?P<ent> \w+) \s+ is | # entity decl
-
- component \s+ (?P<comp> \w+) | # component decl
-
- \w+ \s* : \s* entity \s+ (?: work\.)? (?P<inst> \w+) # instance decl
- """, re.I|re.X)
-
-def parse_deps_vhdl(hdl_src):
- ent = None
- deps = []
- dep_list = DepList()
-
- with open(hdl_src) as vf:
- for line in vf:
- # Delete any comments.
- try:
- line = line[:line.index('--')]
- except ValueError:
- pass
- # Since VHDL is case insensitive, convert everything to lowercase
- line = line.lower()
-
- match = m_dep_vhdl.search(line)
- if match:
- # A package import decl after an entity or package body is
- # defined means we have hit a new entity, so we must output
- # what we've got and start over
- if match.group('pkg') and ent:
- dep_list.add_dep( ent, hdl_src, deps )
- ent = None
- deps = []
-
- # Find out what we've matched and handle appropriately
- if match.group('ent'):
- if ent:
- raise Panic("""\
-%s: unexpected entity %s found when processing entity %s. missing package imports?""" % (relpath(self.hdl_src),
- e,
- self.ent) )
-
- else:
- ent = match.group('ent')
-
- if ent in dep_list:
- raise Panic( "duplicate entity %s declaration found in %s (previous in %s)" % (ent, relpath(hdl_src), relpath(dep_list[ent][0]) ) )
-
- # If it's a package import decl, then lib and pkg will be
- # defined. Only add a package if the library is 'work'.
- if match.group('lib') == 'work':
- deps.append( match.group('pkg') )
-
- # If it's an instance decl, then inst will be defined.
- if match.group('inst'):
- deps.append( match.group('inst') )
-
- # If it's a component decl, add it so long as it's not
- # marked to be ignored
- if comp_filter.accept(match.group('comp')):
- deps.append( match.group('comp') )
-
- dep_list.add_dep( ent, hdl_src, deps )
- return dep_list
-
-
-#
-# parse_deps_verilog()
-#
-# Determine dependencies for a given file (verilog mode)
-def parse_deps_verilog(hdl_src):
- sys.stderr.write('%s:%s: warning: unsupported verilog source ignored.\n' %
- ( prog_name(), relpath(hdl_src) ))
-
- return DepList()
-
-
-m_parse_xco = re.compile( "^\s*\w+\s+(\w+)\s*=\s*(.*)$" )
-
-#
-# parse_coregen()
-#
-# Determine the entity and HDL source provided by the given core
-def parse_coregen(hdl_src):
- def bool(s):
- return s in ['yes', 'true', '1']
-
- attribs = {}
-
- # Read in project settings and attributes
- with open(hdl_src) as vf:
- for line in vf:
- # Delete any comments.
- try:
- line = line[:line.index('#')]
- except ValueError:
- pass
-
- match = m_parse_xco.search( line )
- if match:
- attribs[match.group(1).lower()] = match.group(2)
-
- # sanity check
- try:
- ent = attribs['component_name']
- use_vhdl = bool(attribs['vhdlsim'])
- use_verilog = bool(attribs['verilogsim'])
- except KeyError, e:
- raise Panic( '%s: missing parameter %s' % (hdl_src, e) )
-
- if not use_vhdl ^ use_verilog:
- raise Panic( "%s: exactly one simulation (VHDL or verilog) is required" % relpath(hdl_src) )
-
- # The simulation source file will be the entity name with the appropriate
- # extension attached
- sim_src = os.path.join( CORES_DIR, ent )
- if use_vhdl:
- sim_src += '.vhd'
- else:
- sim_src += '.v'
-
- # Generate dependency record and return
- dep_list = DepList()
- dep_list.add_dep( ent, sim_src, [], hdl_src )
-
- return dep_list
-
-#
-# source_get_all_deps()
-#
-# Generate a list of dependencies in all VHDL and verilog files in the given
-# list of directories, optionally writing out a cache of the results
-#
-# Returns a hash indexed by entity of lists in which the first element is the
-# path to where that entity is declared, and the remaining elements are the
-# entities on which that entity depends.
-#
src_parser_map = {
- '.vhd' : parse_deps_vhdl,
- '.vhdl': parse_deps_vhdl,
- '.v' : parse_deps_verilog,
+ '.vhd' : parse_vhdl,
+ '.vhdl': parse_vhdl,
+ '.v' : parse_verilog,
'.xco' : parse_coregen
}
def source_get_all_deps(src_dirs, write_cache=False, verbose=False):
- dep_list = DepList()
+ """
+ Generate a list of dependencies in all VHDL and verilog files in the given
+ list of directories, optionally writing out a cache of the results
+
+ Returns a hash indexed by entity of lists in which the first element is the
+ path to where that entity is declared, and the remaining elements are the
+ entities on which that entity depends.
+ """
+ dep_list = DepList.DepList()
for path, dirs, hdl_srcs in walk_dirlist(src_dirs):
- dir_deps = DepList()
+ dir_deps = DepList.DepList()
for src in hdl_srcs:
path_src = os.path.join(path, src)
@@ -300,60 +58,61 @@
print path_src
# Parse this file
- src_ent_list = src_parser_map[src_ext](path_src)
+ src_ent_list = src_parser_map[src_ext].parse(path_src)
dep_list.merge( src_ent_list )
dir_deps.merge( src_ent_list )
# Write out cache if that option is enabled
if write_cache and dir_deps:
- with open(os.path.join(path, DEPS_FILE), 'w') as deps_file:
- dir_deps.write_deps_cache( deps_file )
+ with open(os.path.join(path, tool_common.DEPS_FILE), 'w') as df:
+ dir_deps.write_deps_cache( df )
return dep_list
-#
-# cache_get_all_deps()
-#
-# like source_get_all_deps(), but reads from .depends cache
+
def cache_get_all_deps(src_dirs, verbose=False):
- dep_list = DepList()
+ """
+ like source_get_all_deps(), but reads from .depends cache
+ """
+ dep_list = DepList.DepList()
# Read in all .depends files
for path, dirs, files in walk_dirlist(src_dirs):
# Not all directories will have cache files
- if DEPS_FILE not in files:
+ if tool_common.DEPS_FILE not in files:
continue
# Read through .depends file and build dependencies list
- with open(os.path.join(path, DEPS_FILE)) as deps_file:
- dep_list.read_deps_cache( deps_file, path )
+ with open(os.path.join(path, tool_common.DEPS_FILE)) as df:
+ dep_list.read_deps_cache( df, path )
return dep_list
-#
-# resolve_deps()
-#
-# Resolve the dependencies arising from the top module as specified in the
-# configuration. Returns an ordered list of sources.
+
def resolve_deps(top_ent, dep_list, disambig):
- #
- # what_srcs()
- #
- # Return a list of files that depend on the specified entity
+ """
+ Resolve the dependencies arising from the top module as specified in the
+ configuration. Returns an ordered list of sources.
+ """
+
def what_srcs(what_ent):
+ """
+ Return a list of files that depend on the specified entity
+ """
ws = []
for ent, allcand in dep_list.iteritems():
for hdl_src, deps, core_src in allcand:
if what_ent in deps:
ws.append(hdl_src)
return ws
+
- #
- # disambiguate()
- #
- # Error check, select and return the dependencies for the given entity
- # according to the disambiguation rules.
def disambiguate(ent):
+ """
+ Error check, select and return the dependencies for the given entity
+ according to the disambiguation rules.
+ """
+
# Check to make sure we know about unresolved entity ent
if ent not in dep_list:
raise Panic( """\
@@ -436,12 +195,12 @@
return resolved
-################################################################################
-#
-# print_help()
-#
-# Print help message
+
def print_help():
+ """
+ Print help message
+ """
+
print """
Dependency cache builder
@@ -465,7 +224,7 @@
""" % (prog_name())
sys.exit(0)
-# main
+
def main(argv):
verbose = False
Modified: trunk/bin/mkvproj.py
===================================================================
--- trunk/bin/mkvproj.py 2008-12-01 23:31:06 UTC (rev 66)
+++ trunk/bin/mkvproj.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -1,305 +1,33 @@
#!/usr/bin/python
-from __future__ import with_statement
-import sys
-import os
-import re
-import getopt
-
-from djm_pyhelp import *
-import mkvdeps
-
-#
-# Constants
-#
-
-# Simulation/synthesis: the name of the makefile containing coregen build rules
-COREGEN_MK = 'coregen.mk'
-
-# Simulation: name of the makefile containing modelsim build rules
-MDLSIM_MK = 'modelsim.mk'
-
-# Synthesis: synplify output directory
-BUILD_DIR = 'build'
-
-# Simulation: modelsim commands for compiling HDL source files
-mdlsim_compile = {
- '.vhd' : '$(VCOM) $(VCOM_OPTS)',
- '.vhdl': '$(VCOM) $(VCOM_OPTS)',
- '.v' : '$(VLOG) $(VLOG_OPTS)'
- }
-
-# Synthesis: synthesis commands for adding HDL source files
-lang_flag = {'.vhd' :'-vhdl -lib work',
- '.vhdl':'-vhdl -lib work',
- '.v' :'-verilog'}
-
-# Synthesis: FPGA Family name expansion from shorthand
-family_tab = {'2V' : 'VIRTEX2',
- '2VP' : 'VIRTEX2P',
- '2S' : 'SPARTAN2',
- '2SE' : 'SPARTAN2E',
- '3S' : 'SPARTAN3'}
-
-
-
-#
-# class Config
-#
-# Storage object for configuration
-class Config:
- def __init__(self):
- #
- # Defaults
- #
- self.verbose = False
- self.output_dir = '.'
- self.libpath = []
- self.disambig = {}
- self.part = '<unspecified>'
- self.top_ent = ''
- self.tool = 'default'
- self.cache_deps = None
- self.relative_paths = True
- self.constraints = []
-
################################################################################
#
-# rel_src()
+# mkvproj.py
#
-# Conditionally return relative path of the given source file, with (some)
-# error checking
-def rel_src(cfg, hdl_src):
- if cfg.relative_paths:
- try:
- return relpath(hdl_src, cfg.output_dir)
- except OSError:
- raise Panic( "missing source file %s. Is dependency cache out of date?" % (x[1]) )
- else:
- return hdl_src
-
-################################################################################
+# PURPOSE:
#
-# mk_coregen_mf()
+# Simulation and synthesis project writer. Uses autodeps service from
+# mkvdeps.py.
#
-# Write out a coregen makefile from the list of (hdl_src, core_src).
-def mk_coregen_mf(cfg, cores):
-
- # Make the cores directory, if it doesn't already exist
- cores_dir = os.path.join( cfg.output_dir, mkvdeps.CORES_DIR )
- if not os.path.isdir( cores_dir ):
- sys.stderr.write( 'mkdir %s\n' % (cores_dir) )
- os.mkdir( cores_dir )
-
- with open( os.path.join(cfg.output_dir, COREGEN_MK), 'w' ) as mf:
- # Write out header
- mf.write( """\
-# Coregen makefile automatically generated by %s. Do not edit!
# $Id$
-#
-COREGEN ?= coregen
+from __future__ import with_statement
+from util import *
-# default target
-""" % (prog_name()) )
-
- # Write out default target
- mf.write( 'all: %s\n\n' % (' '.join( [hdl_src
- for hdl_src, core_src in cores] )) )
+import sys
+import os
+import re
+import getopt
- # Write out coregen invocation rules
- for hdl_src, core_src in cores:
- mf.write( """\
-%s: %s
-\tcd %s; $(COREGEN) -b ../%s
-""" % (hdl_src, # the build target (sim source)
- rel_src(cfg, core_src), # its dependency (core description [.xco])
- mkvdeps.CORES_DIR, # the cores subdirectory
- rel_src(cfg, core_src) ) ) # the core description file [.xco]
-
-################################################################################
-#
-# mk_mdlsim_proj()
-#
-# Write out a modelsim simulation project using the resolved sources
-def mk_mdlsim_proj(cfg):
- #
- # msim_lib()
- #
- # Helper macro for mk_mdlsim_proj() to express the filename of a modelsim
- # library entity for the given entity
- def msim_lib(ent):
- return os.path.join( 'work', ent, '_primary.dat' )
+import mkvdeps
+import tool_common
- # make the work library, if it doesn't exist
- worklib = os.path.join(cfg.output_dir, 'work')
- if not os.path.isdir(worklib):
- sys.stderr.write( 'vlib %s\n' % (worklib) )
- os.system( 'vlib %s' % (worklib) )
- # write out the modelsim makefile
- cores = []
- with open( os.path.join(cfg.output_dir, MDLSIM_MK), 'w' ) as mf:
- mf.write( """\
-# Modelsim makefile automatically generated by %s. Do not edit!
-# $Id$
-#
-
-VCOM ?= vcom
-VLOG ?= vlog
-
-# default target
-""" % (prog_name()) )
-
- # Write out default target
- mf.write( "all: %s\n\n" % (msim_lib(cfg.top_ent)) )
-
- for ent, hdl_src, deps, core_src in cfg.resolved_list:
- rel_hdl_src = rel_src( cfg, hdl_src )
-
- # Write rules to express this source's dependencies, if any
- if deps:
- mf.write( '%s: %s\n' % (
- msim_lib(ent),
- ' '.join( [msim_lib(x) for x in deps]) ) )
-
- # Write rule to compile a source file into the library
- mf.write( """\
-%s: %s
-\t%s %s || (rm -f $@; false)
-
-""" % ( msim_lib(ent), # The build target (entity in library WORK)
- rel_hdl_src, # The HDL source
- mdlsim_compile[os.path.splitext(rel_hdl_src)[1]], # compile command
- rel_hdl_src)) # The HDL source
-
- # If it's a core, add it to the cores list
- if core_src:
- cores.append( (hdl_src, core_src) )
-
- # Include core rules, if any
- if cores:
- mf.write( '\ninclude %s\n' % (COREGEN_MK) )
-
- # Write out core rules, if any
- if cores:
- mk_coregen_mf( cfg, cores )
-
-
-
-################################################################################
-#
-# mk_synplify_proj()
-#
-# Write out a synplify synthesis project from the resolved sources
-def mk_synplify_proj(cfg):
- # write out the synplify project file
- cores = []
- proj_file = os.path.join( cfg.output_dir, '%s.prj' % (cfg.top_ent) )
- with open( proj_file, 'w' ) as pf:
- # Unpack partspec
- match = re.search( "(XC(\d[A-Z]+)\d+)([A-Z]+\d+)(-\d+)", cfg.part.upper() )
- if not match:
- raise Panic( "unknown partspec %s" % (cfg.part) )
- part, family, pkg, speed = match.groups()
-
- # Write out header
- pf.write( """\
-# Synplify project file automatically generated by %s. Do not edit!
-# $Id$
-#
-
-# source files
-""" % (prog_name()) )
-
- # Write out source list
- for ent, hdl_src, deps, core_src in cfg.resolved_list:
- pf.write( 'add_file %s "%s"\n' % (
- lang_flag[os.path.splitext(hdl_src)[1]],
- rel_src(cfg, hdl_src) ) )
-
- # If it's a core, add it to the cores list
- if core_src:
- cores.append( (hdl_src, core_src) )
-
- # Write out the rest of the project
- pf.write( """\
-%s
-
-# output file
-#set result format/file last
-project -result_file "%s"
-
-# build directory
-impl -add %s -type fpga
-impl -active "%s"
-
-# device options
-set_option -technology %s
-set_option -part %s
-set_option -package %s
-set_option -speed_grade %s
-
-#compilation/mapping options
-set_option -default_enum_encoding default
-set_option -resource_sharing 1
-set_option -use_fsm_explorer 0
-
-#map options
-set_option -frequency auto
-set_option -run_prop_extract 1
-set_option -fanout_limit 10000
-set_option -disable_io_insertion 0
-set_option -pipe 1
-set_option -update_models_cp 0
-set_option -verification_mode 0
-set_option -retiming 0
-set_option -no_sequential_opt 0
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-
-
-#sequential_optimizations options
-set_option -symbolic_fsm_compiler 1
-
-#simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 0
-
-#VIF options
-set_option -write_vif 1
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -synthesis_onoff_pragma 0
-set_option -project_relative_includes 1
-
-""" % ('\n'.join( ['add_file -constraint "%s"' % ( rel_src(cfg, hdl_src) )
- for hdl_src in cfg.constraints] ),
- os.path.join( BUILD_DIR, '%s.edf' % (cfg.top_ent) ), # Output netlist
- BUILD_DIR, # Implementation output directory
- BUILD_DIR, # Active implementation
- family_tab[family], # Device family
- part, # Device name
- pkg, # Device package
- speed ) ) # and speed grade
-
- # Write out core rules, if any
- if cores:
- mk_coregen_mf( cfg, cores )
-
-
-################################################################################
-#
-# print_help()
-#
-# Print help message
def print_help():
+ """
+ Print help message
+ """
+
print """
VHDL/verilog project builder
@@ -349,13 +77,6 @@
sys.exit(0)
-# Tool map: Match --tool values to appropriate builder
-tool_map = {'sim': { 'default':mk_mdlsim_proj,
- 'modelsim':mk_mdlsim_proj} ,
- 'synth': { 'default':mk_synplify_proj,
- 'synplify':mk_synplify_proj} }
-
-# Main
def main(argv):
#
# Parse options
@@ -381,7 +102,7 @@
# Temporary list
dlist = []
- cfg = Config()
+ cfg = tool_common.Config()
for arg, val in opts:
if arg in ['-v', '--verbose']: cfg.verbose = True
if arg in ['-d', '--dir']: cfg.output_dir = val
@@ -436,7 +157,7 @@
# of the time. It can always be overridden from the commandline.
if cfg.cache_deps == None:
cfg.cache_deps = os.path.isfile( os.path.join(cfg.output_dir,
- mkvdeps.DEPS_FILE) )
+ tool_common.DEPS_FILE) )
#
# Do job
#
@@ -460,10 +181,11 @@
# Write out project
try:
- tool_proc = tool_map[cfg.oper][cfg.tool]
- except KeyError:
+ exec( 'import tool_%s_%s as tool' % (cfg.oper, cfg.tool) )
+ except ImportError:
raise Panic( "Unknown combination %s/%s" % (cfg.oper, cfg.tool) )
- tool_proc( cfg )
+
+ tool.write_project( cfg )
if __name__ == '__main__':
Copied: trunk/bin/parse_coregen.py (from rev 66, trunk/bin/mkvdeps.py)
===================================================================
--- trunk/bin/parse_coregen.py (rev 0)
+++ trunk/bin/parse_coregen.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1,72 @@
+################################################################################
+#
+# parse_coregen.py
+#
+# PURPOSE:
+#
+# Parses Xilinx Coregen project description files for what entities are
+# provided (and the kind of simulation source provided)
+#
+# $Id$
+
+from __future__ import with_statement
+from util import *
+
+import re
+import os
+
+import DepList
+import tool_common
+
+
+m_parse_xco = re.compile( "^\s*\w+\s+(\w+)\s*=\s*(.*)$" )
+
+def parse(hdl_src):
+ """
+ Determine the entity and HDL source provided by the given core
+ """
+
+ def bool(s):
+ return s.lower() in ['yes', 'true', '1']
+
+
+ attribs = {}
+
+ # Read in project settings and attributes
+ with open(hdl_src) as vf:
+ for line in vf:
+ # Delete any comments.
+ try:
+ line = line[:line.index('#')]
+ except ValueError:
+ pass
+
+ match = m_parse_xco.search( line )
+ if match:
+ attribs[match.group(1).lower()] = match.group(2)
+
+ # sanity check
+ try:
+ ent = attribs['component_name']
+ use_vhdl = bool(attribs['vhdlsim'])
+ use_verilog = bool(attribs['verilogsim'])
+ except KeyError, e:
+ raise Panic( '%s: missing parameter %s' % (hdl_src, e) )
+
+ if not use_vhdl ^ use_verilog:
+ raise Panic( "%s: exactly one simulation (VHDL or verilog) is required" % relpath(hdl_src) )
+
+ # The simulation source file will be the entity name with the appropriate
+ # extension attached
+ sim_src = os.path.join( tool_common.CORES_DIR, ent )
+ if use_vhdl:
+ sim_src += '.vhd'
+ else:
+ sim_src += '.v'
+
+ # Generate dependency record and return
+ dep_list = DepList.DepList()
+ dep_list.add_dep( ent, sim_src, [], hdl_src )
+
+ return dep_list
+
Property changes on: trunk/bin/parse_coregen.py
___________________________________________________________________
Added: svn:keywords
+ Author Date Id Revision
Added: svn:eol-style
+ native
Copied: trunk/bin/parse_verilog.py (from rev 66, trunk/bin/mkvdeps.py)
===================================================================
--- trunk/bin/parse_verilog.py (rev 0)
+++ trunk/bin/parse_verilog.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1,31 @@
+################################################################################
+#
+# parse_verilog.py
+#
+# PURPOSE:
+#
+# Parses Verilog source for entity dependencies
+#
+# $Id$
+
+from __future__ import with_statement
+from util import *
+
+import sys
+import re
+
+import DepList
+import comp_filter
+
+
+def parse(hdl_src):
+ """
+ Determine dependencies for a given file (verilog mode)
+ """
+
+ sys.stderr.write('%s:%s: warning: unsupported verilog source ignored.\n' %
+ ( prog_name(), relpath(hdl_src) ))
+
+ return DepList.DepList()
+
+
Property changes on: trunk/bin/parse_verilog.py
___________________________________________________________________
Added: svn:keywords
+ Author Date Id Revision
Added: svn:eol-style
+ native
Copied: trunk/bin/parse_vhdl.py (from rev 66, trunk/bin/mkvdeps.py)
===================================================================
--- trunk/bin/parse_vhdl.py (rev 0)
+++ trunk/bin/parse_vhdl.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1,90 @@
+################################################################################
+#
+# parse_vhdl.py
+#
+# PURPOSE:
+#
+# Parses VHDL source for entity dependencies
+#
+# $Id$
+
+from __future__ import with_statement
+from util import *
+
+import re
+
+import DepList
+import comp_filter
+
+
+m_dep_vhdl = re.compile("""
+ use \s+ (?P<lib> \w+) \. (?P<pkg> \w+) \.all \s* ; | # pkg import
+
+ (?: entity|package) \s+ (?P<ent> \w+) \s+ is | # entity decl
+
+ component \s+ (?P<comp> \w+) | # component decl
+
+ \w+ \s* : \s* entity \s+ (?: work\.)? (?P<inst> \w+) # instance decl
+ """, re.I|re.X)
+
+def parse(hdl_src):
+ """
+ Determine dependencies for a given file (VHDL mode)
+ """
+
+ ent = None
+ deps = []
+ dep_list = DepList.DepList()
+
+ with open(hdl_src) as vf:
+ for line in vf:
+ # Delete any comments.
+ try:
+ line = line[:line.index('--')]
+ except ValueError:
+ pass
+ # Since VHDL is case insensitive, convert everything to lowercase
+ line = line.lower()
+
+ match = m_dep_vhdl.search(line)
+ if match:
+ # A package import decl after an entity or package body is
+ # defined means we have hit a new entity, so we must output
+ # what we've got and start over
+ if match.group('pkg') and ent:
+ dep_list.add_dep( ent, hdl_src, deps )
+ ent = None
+ deps = []
+
+ # Find out what we've matched and handle appropriately
+ if match.group('ent'):
+ if ent:
+ raise Panic("""\
+%s: unexpected entity %s found when processing entity %s. missing package imports?""" % (relpath(self.hdl_src),
+ e,
+ self.ent) )
+
+ else:
+ ent = match.group('ent')
+
+ if ent in dep_list:
+ raise Panic( "duplicate entity %s declaration found in %s (previous in %s)" % (ent, relpath(hdl_src), relpath(dep_list[ent][0]) ) )
+
+ # If it's a package import decl, then lib and pkg will be
+ # defined. Only add a package if the library is 'work'.
+ if match.group('lib') == 'work':
+ deps.append( match.group('pkg') )
+
+ # If it's an instance decl, then inst will be defined.
+ if match.group('inst'):
+ deps.append( match.group('inst') )
+
+ # If it's a component decl, add it so long as it's not
+ # marked to be ignored
+ if comp_filter.accept(match.group('comp')):
+ deps.append( match.group('comp') )
+
+ dep_list.add_dep( ent, hdl_src, deps )
+ return dep_list
+
+
Property changes on: trunk/bin/parse_vhdl.py
___________________________________________________________________
Added: svn:keywords
+ Author Date Id Revision
Added: svn:eol-style
+ native
Modified: trunk/bin/synplify_wrapper.py
===================================================================
--- trunk/bin/synplify_wrapper.py 2008-12-01 23:31:06 UTC (rev 66)
+++ trunk/bin/synplify_wrapper.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -1,13 +1,24 @@
#!/usr/bin/python
+################################################################################
+#
+# synplify_wrapper.py
+#
+# PURPOSE:
+#
+# Invokes and prints only the salient log messages from synplify's log output
+#
+# $Id$
+
from __future__ import with_statement
+from util import *
+
import sys
import os
import errno
import re
import getopt
-from djm_pyhelp import *
DEF_SYN_EXE = 'synplify_premier_dp'
BUILD_DIR = 'build'
@@ -171,12 +182,12 @@
else:
return 1
-################################################################################
-#
-# print_help()
-#
-# Print help message
+
def print_help():
+ """
+ Print help message
+ """
+
print """
Synplify synthesis tool wrapper
@@ -196,6 +207,7 @@
""" % (prog_name(), DEF_SYN_EXE)
sys.exit(0)
+
# main
def main(argv):
verbose = False
Copied: trunk/bin/tool_common.py (from rev 66, trunk/bin/mkvproj.py)
===================================================================
--- trunk/bin/tool_common.py (rev 0)
+++ trunk/bin/tool_common.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1,103 @@
+################################################################################
+#
+# tool_common.py
+#
+# PURPOSE:
+#
+# Routines and constants common to other project writer modules
+#
+# $Id$
+
+from __future__ import with_statement
+from util import *
+
+import sys
+import os
+
+
+#
+# Constants
+#
+
+# Dependency cache file name
+DEPS_FILE = '.depends'
+
+# the name of the makefile containing coregen build rules
+COREGEN_MK = 'coregen.mk'
+
+# Output directory for coregen
+CORES_DIR = 'cores'
+
+class Config:
+ """
+ Storage object for configuration
+ """
+ def __init__(self):
+ """
+ Defaults
+ """
+
+ self.verbose = False
+ self.output_dir = '.'
+ self.libpath = []
+ self.disambig = {}
+ self.part = '<unspecified>'
+ self.top_ent = ''
+ self.tool = 'default'
+ self.cache_deps = None
+ self.relative_paths = True
+ self.constraints = []
+
+
+def rel_src(cfg, hdl_src):
+ """
+ Conditionally return relative path of the given source file, with (some)
+ error checking
+ """
+
+ if cfg.relative_paths:
+ try:
+ return relpath(hdl_src, cfg.output_dir)
+ except OSError:
+ raise Panic( "missing source file %s. Is dependency cache out of date?" % (x[1]) )
+ else:
+ return hdl_src
+
+
+def write_coregen_mf(cfg, cores):
+ """
+ Write out a coregen makefile from the list of (hdl_src, core_src).
+ """
+
+ # Make the cores directory, if it doesn't already exist
+ cores_dir = os.path.join( cfg.output_dir, CORES_DIR )
+ if not os.path.isdir( cores_dir ):
+ sys.stderr.write( 'mkdir %s\n' % (cores_dir) )
+ os.mkdir( cores_dir )
+
+ with open( os.path.join(cfg.output_dir, COREGEN_MK), 'w' ) as mf:
+ # Write out header
+ mf.write( """\
+# Coregen makefile automatically generated by %s. Do not edit!
+# $Id$
+#
+
+COREGEN ?= coregen
+
+# default target
+""" % (prog_name()) )
+
+ # Write out default target
+ mf.write( 'all: %s\n\n' % (' '.join( [hdl_src
+ for hdl_src, core_src in cores] )) )
+
+ # Write out coregen invocation rules
+ for hdl_src, core_src in cores:
+ mf.write( """\
+%s: %s
+\tcd %s; $(COREGEN) -b ../%s
+""" % (hdl_src, # the build target (sim source)
+ rel_src(cfg, core_src), # its dependency (core description [.xco])
+ CORES_DIR, # the cores subdirectory
+ rel_src(cfg, core_src) ) ) # the core description file [.xco]
+
Property changes on: trunk/bin/tool_common.py
___________________________________________________________________
Added: svn:keywords
+ Author Date Id Revision
Added: svn:eol-style
+ native
Added: trunk/bin/tool_sim_default.py
===================================================================
--- trunk/bin/tool_sim_default.py (rev 0)
+++ trunk/bin/tool_sim_default.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1 @@
+link tool_sim_modelsim.py
\ No newline at end of file
Property changes on: trunk/bin/tool_sim_default.py
___________________________________________________________________
Added: svn:special
+ *
Copied: trunk/bin/tool_sim_modelsim.py (from rev 66, trunk/bin/mkvproj.py)
===================================================================
--- trunk/bin/tool_sim_modelsim.py (rev 0)
+++ trunk/bin/tool_sim_modelsim.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1,104 @@
+################################################################################
+#
+# tool_sim_modelsim.py
+#
+# PURPOSE:
+#
+# Project writer module for Mentor Graphics' ModelSim HDL simulator
+#
+# $Id$
+
+from __future__ import with_statement
+from util import *
+
+import sys
+import os
+
+import tool_common
+
+
+#
+# Constants
+#
+
+# name of the makefile containing modelsim build rules
+MDLSIM_MK = 'modelsim.mk'
+
+# modelsim commands for compiling HDL source files
+mdlsim_compile = {
+ '.vhd' : '$(VCOM) $(VCOM_OPTS)',
+ '.vhdl': '$(VCOM) $(VCOM_OPTS)',
+ '.v' : '$(VLOG) $(VLOG_OPTS)'
+ }
+
+
+def write_project(cfg):
+ """
+ Write out a modelsim simulation project using the resolved sources
+ """
+
+ def msim_lib(ent):
+ """
+ Helper macro for mk_mdlsim_proj() to express the filename of a modelsim
+ library entity for the given entity
+ """
+
+ return os.path.join( 'work', ent, '_primary.dat' )
+
+
+ # make the work library, if it doesn't exist
+ worklib = os.path.join(cfg.output_dir, 'work')
+ if not os.path.isdir(worklib):
+ sys.stderr.write( 'vlib %s\n' % (worklib) )
+ os.system( 'vlib %s' % (worklib) )
+
+ # write out the modelsim makefile
+ cores = []
+ with open( os.path.join(cfg.output_dir, MDLSIM_MK), 'w' ) as mf:
+ mf.write( """\
+# Modelsim makefile automatically generated by %s. Do not edit!
+# $Id$
+#
+
+VCOM ?= vcom
+VLOG ?= vlog
+
+# default target
+""" % (prog_name()) )
+
+ # Write out default target
+ mf.write( "all: %s\n\n" % (msim_lib(cfg.top_ent)) )
+
+ for ent, hdl_src, deps, core_src in cfg.resolved_list:
+ rel_hdl_src = tool_common.rel_src( cfg, hdl_src )
+
+ # Write rules to express this source's dependencies, if any
+ if deps:
+ mf.write( '%s: %s\n' % (
+ msim_lib(ent),
+ ' '.join( [msim_lib(x) for x in deps]) ) )
+
+ # Write rule to compile a source file into the library
+ mf.write( """\
+%s: %s
+\t%s %s || (rm -f $@; false)
+
+""" % ( msim_lib(ent), # The build target (entity in library WORK)
+ rel_hdl_src, # The HDL source
+ mdlsim_compile[os.path.splitext(rel_hdl_src)[1]], # compile command
+ rel_hdl_src)) # The HDL source
+
+ # If it's a core, add it to the cores list
+ if core_src:
+ cores.append( (hdl_src, core_src) )
+
+ # Include core rules, if any
+ if cores:
+ mf.write( '\ninclude %s\n' % (tool_common.COREGEN_MK) )
+
+ # Write out core rules, if any
+ if cores:
+ tool_common.write_coregen_mf( cfg, cores )
+
+
+
Property changes on: trunk/bin/tool_sim_modelsim.py
___________________________________________________________________
Added: svn:keywords
+ Author Date Id Revision
Added: svn:eol-style
+ native
Added: trunk/bin/tool_synth_default.py
===================================================================
--- trunk/bin/tool_synth_default.py (rev 0)
+++ trunk/bin/tool_synth_default.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1 @@
+link tool_synth_synplify.py
\ No newline at end of file
Property changes on: trunk/bin/tool_synth_default.py
___________________________________________________________________
Added: svn:special
+ *
Copied: trunk/bin/tool_synth_synplify.py (from rev 66, trunk/bin/mkvproj.py)
===================================================================
--- trunk/bin/tool_synth_synplify.py (rev 0)
+++ trunk/bin/tool_synth_synplify.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1,145 @@
+################################################################################
+#
+# tool_synth_synplify.py
+#
+# PURPOSE:
+#
+# Project writer module for Synplicity's Synplify synthesis tool.
+#
+# $Id$
+
+from __future__ import with_statement
+from util import *
+
+import os
+import re
+
+import tool_common
+
+
+#
+# Constants
+#
+
+# Synthesis: synplify output directory
+BUILD_DIR = 'build'
+
+# Synthesis: synthesis commands for adding HDL source files
+lang_flag = {'.vhd' :'-vhdl -lib work',
+ '.vhdl':'-vhdl -lib work',
+ '.v' :'-verilog'}
+
+# Synthesis: FPGA Family name expansion from shorthand
+family_tab = {'2V' : 'VIRTEX2',
+ '2VP' : 'VIRTEX2P',
+ '2S' : 'SPARTAN2',
+ '2SE' : 'SPARTAN2E',
+ '3S' : 'SPARTAN3'}
+
+
+def write_project(cfg):
+ """
+ Write out a synplify synthesis project from the resolved sources
+ """
+ # write out the synplify project file
+ cores = []
+ proj_file = os.path.join( cfg.output_dir, '%s.prj' % (cfg.top_ent) )
+ with open( proj_file, 'w' ) as pf:
+ # Unpack partspec
+ match = re.search( "(XC(\d[A-Z]+)\d+)([A-Z]+\d+)(-\d+)", cfg.part.upper() )
+ if not match:
+ raise Panic( "unknown partspec %s" % (cfg.part) )
+ part, family, pkg, speed = match.groups()
+
+ # Write out header
+ pf.write( """\
+# Synplify project file automatically generated by %s. Do not edit!
+# $Id$
+#
+
+# source files
+""" % (prog_name()) )
+
+ # Write out source list
+ for ent, hdl_src, deps, core_src in cfg.resolved_list:
+ pf.write( 'add_file %s "%s"\n' % (
+ lang_flag[os.path.splitext(hdl_src)[1]],
+ tool_common.rel_src(cfg, hdl_src) ) )
+
+ # If it's a core, add it to the cores list
+ if core_src:
+ cores.append( (hdl_src, core_src) )
+
+ # Write out the rest of the project
+ pf.write( """\
+%s
+
+# output file
+#set result format/file last
+project -result_file "%s"
+
+# build directory
+impl -add %s -type fpga
+impl -active "%s"
+
+# device options
+set_option -technology %s
+set_option -part %s
+set_option -package %s
+set_option -speed_grade %s
+
+#compilation/mapping options
+set_option -default_enum_encoding default
+set_option -resource_sharing 1
+set_option -use_fsm_explorer 0
+
+#map options
+set_option -frequency auto
+set_option -run_prop_extract 1
+set_option -fanout_limit 10000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -verification_mode 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+
+
+#sequential_optimizations options
+set_option -symbolic_fsm_compiler 1
+
+#simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -synthesis_onoff_pragma 0
+set_option -project_relative_includes 1
+
+""" % ('\n'.join( ['add_file -constraint "%s"' % (
+ tool_common.rel_src(cfg, hdl_src) )
+ for hdl_src in cfg.constraints] ),
+ os.path.join( BUILD_DIR, '%s.edf' % (cfg.top_ent) ), # Output netlist
+ BUILD_DIR, # Implementation output directory
+ BUILD_DIR, # Active implementation
+ family_tab[family], # Device family
+ part, # Device name
+ pkg, # Device package
+ speed ) ) # and speed grade
+
+ # Write out core rules, if any
+ if cores:
+ tool_common.write_coregen_mf( cfg, cores )
+
+
Property changes on: trunk/bin/tool_synth_synplify.py
___________________________________________________________________
Added: svn:keywords
+ Author Date Id Revision
Added: svn:eol-style
+ native
Copied: trunk/bin/util.py (from rev 66, trunk/bin/djm_pyhelp.py)
===================================================================
--- trunk/bin/util.py (rev 0)
+++ trunk/bin/util.py 2008-12-04 18:31:17 UTC (rev 67)
@@ -0,0 +1,120 @@
+################################################################################
+#
+# util.py
+#
+# PURPOSE:
+#
+# Simple generic support functions
+#
+# $Id$
+
+import sys
+import os
+
+
+def prog_name():
+ """
+ Returns programme name
+ """
+
+ return os.path.basename(sys.argv[0])
+
+
+class Panic(Exception):
+ """
+ For equivalent of perl die "message"
+ """
+
+ def __init__(self, value):
+ self.value = value
+
+ def __str__(self):
+ return "%s: panic: %s" % (prog_name(), self.value)
+
+
+# relpath.py
+# R.Barran 30/08/2004
+
+def relpath(target, base=os.curdir):
+ """
+ Return a relative path to the target from either the current dir or an
+ optional base dir. Base can be a directory specified either as absolute or
+ relative to current dir.
+ """
+
+# check commented out: not clear this is required, djm 11/6/08
+# if not os.path.exists(target):
+# raise OSError, 'Target does not exist: '+target
+
+ if not os.path.isdir(base):
+ raise OSError, 'Base is not a directory or does not exist: '+base
+
+ base_list = (os.path.abspath(base)).split(os.sep)
+ target_list = (os.path.abspath(target)).split(os.sep)
+
+ # On the windows platform the target may be on a completely different drive from the base.
+ if os.name in ['nt','dos','os2'] and base_list[0] <> target_list[0]:
+ raise OSError, 'Target is on a different drive to base. Target: '+target_list[0].upper()+', base: '+base_list[0].upper()
+
+ # Starting from the filepath root, work out how much of the filepath is
+ # shared by base and target.
+ for i in range(min(len(base_list), len(target_list))):
+ if base_list[i] <> target_list[i]: break
+ else:
+ # If we broke out of the loop, i is pointing to the first differing
+ # path elements. If we didn't break out of the loop, i is pointing to
+ # identical path elements. Increment i so that in all cases it points
+ # to the first differing path elements.
+ i+=1
+
+ rel_list = [os.pardir] * (len(base_list)-i) + target_list[i:]
+ return os.path.join(*rel_list)
+
+
+def walk_dirlist(dirlist):
+ """
+ Conditionally walks the list of directories given. Only directories
+ beginning with a + will be searched recursively. Version control
+ directories will be filtered out along the way.
+ """
+
+ excl_dirs = []
+ for dir in dirlist:
+ dir = dir.strip()
+ if not dir:
+ continue
+
+ # Those directories with a leading - should be excluded from the walk.
+ if dir.startswith('-'):
+ excl_dirs.append( dir.lstrip('-') )
+ continue
+
+ # Only those directories with a leading + should be recursed into.
+ recurse = dir.startswith('+')
+ for path, dirs, files in os.walk( dir.lstrip('+') ):
+ if not recurse:
+ del dirs[:]
+
+ # Skip revision control directories
+ try:
+ del dirs[dirs.index('.svn')]
+ del dirs[dirs.index('CVS')]
+ del dirs[dirs.index('RCS')]
+ del dirs[dirs.index('work')]
+ except ValueError:
+ pass
+
+ # Skip any excludes
+ for i in reversed(xrange(len(dirs))):
+ for excl in excl_dirs:
+ try:
+ if os.path.samefile( os.path.join(path, dirs[i]), excl ):
+ del dirs[i]
+ except OSError:
+ sys.stderr.write( "%s: ignoring invalid ignor...
[truncated message content] |
|
From: <dav...@us...> - 2008-12-04 12:49:58
|
Revision: 1
http://fbt.svn.sourceforge.net/fbt/?rev=1&view=rev
Author: dave_infj
Date: 2008-12-04 12:49:54 +0000 (Thu, 04 Dec 2008)
Log Message:
-----------
Initial structure
Added Paths:
-----------
branches/
tags/
trunk/
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
