Re: [Etherboot-developers] I've just checked and ...

[Eric W B. <ebi...@ln...>]

Ronald G Minnich <rmi...@la...> writes:

> The 5.0.5 timer.[ch] is identical it seems with the 5.0.7 version. So my
> 5.0.5 version should be fine with 5.0.7. My version has the "don't use
> timer2" patch. I am attaching it for all of you to take a look see and
> comment. I think this might help with my current problems as Smartcore
> systems don't actually have a TIMER2 -- all timeouts go to 0.
> 
> ron

Ron in playing with this code I wanted to see how accurate it's
estimates were. 

> // this is the "no timer2" version. 
> // to calibrate tsc, we get a TSC reading, then to 1,000,000 outbs to port 0x80
> // then we read TSC again, and divide the difference by 1,000,000
> // we have found on a wide range of machines that this gives us a a good
> microsecond value
> 
> // to +- 10%. On a dual AMD 1.6 Ghz box, it gives us .97 microseconds, and on a
> 
> // 267 Mhz. p5, it gives us 1.1 microseconds. 
> // also, since gcc now supports long long, we use that. 
> // also no unsigned long long / operator, so we play games. 
> // about the only thing you can do with long longs, it seems, is return them and
> assign them.

I am getting a reading of about 1.37 to 1.4 microseconds for an outb,
on a dual 2.4 Xeon.

I guess this isn't too bad as the delays will take longer than expected
with an estimate of 1.0 microsecond per outb.  But the estimate is so
inaccurate at + 40% that I'm not really certain it is useful.

Eric