Re: [Etherboot-developers] [PATCH] PCI updates to avoid e1000 chaos

[<ebi...@ln...>]

Christopher Li <ch...@gn...> writes:

> On 13 Mar 2002, Eric W. Biederman wrote:
> 
> > ke...@us... (Ken Yap) writes:
> > 
> > > Thanks very much for that cleanup, Eric. I'll commit to CVS and put out
> > > a new megapatch for rc3 in a moment.
> > 
> > Cool.  I have just tested the e1000 and the eepro100 under LinuxBIOS
> Good to heard that e1000 works.
> 
> BTW, Ken. e1000 is mem base address not io base. It is no harm though
> to mask out the lowest two bit of the base address.

O.k. Let me clarify a little what I did.  The current
etherboot values of pcidev->membase && pcidev->iobase are
bogus concepts from a generic pci perspective.  In generic pci 
you have 6 base registers that can either be io or memory mapped
io addresses.

So I still compute pcidev->membase && pcidev->iobase for backwards
compatibility but I have depricated their use for new things.  
For the e1000 I slightly modified it to read the value of
PCI_BASE_ADDRESS_0 directly.

Aditionally the generic etherboot code no longer makes checks to 
see if the any of the pci resources are populated.

So from a pci device perspective this is the general solution that
works for everything.

Eric