Menu
▾
▴
SF.net SVN: edk2-buildtools:[2590] trunk/BaseTools
|
From: <oli...@us...> - 2013-07-31 10:44:02
|
Revision: 2590
http://sourceforge.net/p/edk2-buildtools/code/2590
Author: oliviermartin
Date: 2013-07-31 10:43:59 +0000 (Wed, 31 Jul 2013)
Log Message:
-----------
BaseTools: Added support for Aarch64 ARM architecture
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Har...@ar...>
Signed-off-by: Olivier Martin <oli...@ar...>
Reviewed-by: Yingke Liu <yin...@in...>
Modified Paths:
--------------
trunk/BaseTools/Conf/target.template
trunk/BaseTools/Conf/tools_def.template
trunk/BaseTools/Source/C/Common/BasePeCoff.c
trunk/BaseTools/Source/C/Common/PeCoffLoaderEx.c
trunk/BaseTools/Source/C/GenFv/GenFvInternalLib.c
trunk/BaseTools/Source/C/GenFw/Elf64Convert.c
trunk/BaseTools/Source/C/GenFw/elf_common.h
trunk/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
trunk/BaseTools/Source/Python/Common/DataType.py
trunk/BaseTools/Source/Python/Common/EdkIIWorkspaceBuild.py
trunk/BaseTools/Source/Python/Common/FdfParserLite.py
trunk/BaseTools/Source/Python/Common/MigrationUtilities.py
trunk/BaseTools/Source/Python/CommonDataClass/CommonClass.py
trunk/BaseTools/Source/Python/CommonDataClass/ModuleClass.py
trunk/BaseTools/Source/Python/CommonDataClass/PlatformClass.py
trunk/BaseTools/Source/Python/Ecc/Check.py
trunk/BaseTools/Source/Python/GenFds/FdfParser.py
trunk/BaseTools/Source/Python/GenFds/FfsInfStatement.py
trunk/BaseTools/Source/Python/GenFds/GenFds.py
trunk/BaseTools/Source/Python/TargetTool/TargetTool.py
trunk/BaseTools/Source/Python/UPT/Library/DataType.py
trunk/BaseTools/Source/Python/build/build.py
Added Paths:
-----------
trunk/BaseTools/Source/C/Include/AArch64/
trunk/BaseTools/Source/C/Include/AArch64/ProcessorBind.h
Modified: trunk/BaseTools/Conf/target.template
===================================================================
--- trunk/BaseTools/Conf/target.template 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Conf/target.template 2013-07-31 10:43:59 UTC (rev 2590)
@@ -34,7 +34,8 @@
TARGET = DEBUG
# TARGET_ARCH List Optional What kind of architecture is the binary being target for.
-# One, or more, of the following, IA32, IPF, X64, EBC or ARM.
+# One, or more, of the following, IA32, IPF, X64, EBC, ARM
+# or AArch64.
# Multiple values can be specified on a single line, using
# space charaters to separate the values. These are used
# during the parsing of a platform description file,
Modified: trunk/BaseTools/Conf/tools_def.template
===================================================================
--- trunk/BaseTools/Conf/tools_def.template 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Conf/tools_def.template 2013-07-31 10:43:59 UTC (rev 2590)
@@ -2577,6 +2577,7 @@
DEFINE GCC_X64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mno-red-zone -Wno-address -mno-stack-arg-probe
DEFINE GCC_IPF_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -minline-int-divide-min-latency
DEFINE GCC_ARMGCC_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mword-relocations -mlittle-endian -mabi=aapcs -mapcs -fno-short-enums -save-temps -fsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-address
+DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mcmodel=large -mlittle-endian -fno-short-enums -save-temps -fverbose-asm -fsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-builtin -Wno-address
DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie
DEFINE GCC_IA32_X64_DLINK_COMMON = DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections
DEFINE GCC_IA32_X64_ASLDLINK_FLAGS = DEF(GCC_IA32_X64_DLINK_COMMON) --entry _ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT)
@@ -4789,6 +4790,8 @@
*_RVCTLINUX_*_*_FAMILY = RVCT
*_RVCTLINUX_*_*_BUILDRULEFAMILY = RVCTLINUX
+*_RVCTLINUX_*_MAKE_PATH = make
+
#
# Use default values, or override in DSC file
#
@@ -4803,7 +4806,6 @@
*_RVCTLINUX_ARM_ASM_FLAGS = $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) DEF(RVCT_ALL_ASM_FLAGS)
*_RVCTLINUX_ARM_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -E
*_RVCTLINUX_ARM_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -E -DVFRCOMPILE --preinclude $(DEST_DIR_DEBUG)/$(MODULE_NAME)StrDefs.h
-*_RVCTLINUX_ARM_MAKE_PATH = make
*_RVCTLINUX_ARM_SLINK_FLAGS = --partial -o
DEBUG_RVCTLINUX_ARM_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(RVCT_ALL_CC_FLAGS) -O1 -g
RELEASE_RVCTLINUX_ARM_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) --diag_suppress=550 DEF(RVCT_ALL_CC_FLAGS) -O2
@@ -4925,6 +4927,42 @@
DEBUG_ARMGCC_ARM_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_ARMGCC_CC_FLAGS) -O0
RELEASE_ARMGCC_ARM_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_ARMGCC_CC_FLAGS) -Wno-unused
+######################
+# AArch64 definitions
+######################
+# AARCH64 64bit ARM Bare-metal GCC (ARM Architecture 64)
+
+*_ARMGCC_AARCH64_ASLCC_PATH = ENV(CROSS_COMPILE)gcc
+*_ARMGCC_AARCH64_ASLDLINK_PATH = ENV(CROSS_COMPILE)ld
+*_ARMGCC_AARCH64_ASLPP_PATH = ENV(CROSS_COMPILE)gcc
+
+*_ARMGCC_AARCH64_CC_PATH = ENV(CROSS_COMPILE)gcc
+*_ARMGCC_AARCH64_SLINK_PATH = ENV(CROSS_COMPILE)ar
+*_ARMGCC_AARCH64_DLINK_PATH = ENV(CROSS_COMPILE)ld
+*_ARMGCC_AARCH64_ASM_PATH = ENV(CROSS_COMPILE)as
+*_ARMGCC_AARCH64_PP_PATH = ENV(CROSS_COMPILE)gcc
+*_ARMGCC_AARCH64_VFRPP_PATH = ENV(CROSS_COMPILE)gcc
+
+#
+# Use default values, or override in DSC file
+#
+*_ARMGCC_AARCH64_ARCHCC_FLAGS =
+*_ARMGCC_AARCH64_ARCHASM_FLAGS =
+*_ARMGCC_AARCH64_ARCHDLINK_FLAGS =
+*_ARMGCC_AARCH64_PLATFORM_FLAGS =
+
+ DEBUG_ARMGCC_AARCH64_ASM_FLAGS = $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) -g
+RELEASE_ARMGCC_AARCH64_ASM_FLAGS = $(ARCHASM_FLAGS) $(PLATFORM_FLAGS)
+
+*_ARMGCC_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -E -x assembler-with-cpp -include $(DEST_DIR_DEBUG)/AutoGen.h
+*_ARMGCC_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -x c -E -P -DVFRCOMPILE --include $(DEST_DIR_DEBUG)/$(MODULE_NAME)StrDefs.h
+
+*_ARMGCC_AARCH64_SLINK_FLAGS = -rc
+*_ARMGCC_AARCH64_DLINK_FLAGS = $(ARCHDLINK_FLAGS) -Ttext=0x0 --emit-relocs -nostdlib -u $(IMAGE_ENTRY_POINT) -e $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
+
+ DEBUG_ARMGCC_AARCH64_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_AARCH64_CC_FLAGS) -Wno-address -O0
+RELEASE_ARMGCC_AARCH64_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_AARCH64_CC_FLAGS) -Wno-address -Wno-unused-but-set-variable
+
####################################################################################
#
# ARM GNU/Linux GCC
@@ -4983,6 +5021,42 @@
DEBUG_ARMLINUXGCC_ARM_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_ARMGCC_CC_FLAGS) -fno-stack-protector -mno-unaligned-access -O0
RELEASE_ARMLINUXGCC_ARM_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_ARMGCC_CC_FLAGS) -fno-stack-protector -mno-unaligned-access -Wno-unused-but-set-variable
+######################
+# AArch64 definitions
+######################
+# AARCH64 64bit ARM GNU/Linux GCC (ARM Architecture 64)
+
+*_ARMLINUXGCC_AARCH64_ASLCC_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
+*_ARMLINUXGCC_AARCH64_ASLDLINK_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-ld
+*_ARMLINUXGCC_AARCH64_ASLPP_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
+
+*_ARMLINUXGCC_AARCH64_CC_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
+*_ARMLINUXGCC_AARCH64_SLINK_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-ar
+*_ARMLINUXGCC_AARCH64_DLINK_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-ld
+*_ARMLINUXGCC_AARCH64_ASM_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-as
+*_ARMLINUXGCC_AARCH64_PP_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
+*_ARMLINUXGCC_AARCH64_VFRPP_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
+
+#
+# Use default values, or override in DSC file
+#
+*_ARMLINUXGCC_AARCH64_ARCHCC_FLAGS =
+*_ARMLINUXGCC_AARCH64_ARCHASM_FLAGS =
+*_ARMLINUXGCC_AARCH64_ARCHDLINK_FLAGS =
+*_ARMLINUXGCC_AARCH64_PLATFORM_FLAGS =
+
+ DEBUG_ARMLINUXGCC_AARCH64_ASM_FLAGS = $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) -g
+RELEASE_ARMLINUXGCC_AARCH64_ASM_FLAGS = $(ARCHASM_FLAGS) $(PLATFORM_FLAGS)
+
+*_ARMLINUXGCC_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -E -x assembler-with-cpp -include $(DEST_DIR_DEBUG)/AutoGen.h
+*_ARMLINUXGCC_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -x c -E -P -DVFRCOMPILE --include $(DEST_DIR_DEBUG)/$(MODULE_NAME)StrDefs.h
+
+*_ARMLINUXGCC_AARCH64_SLINK_FLAGS = -rc
+*_ARMLINUXGCC_AARCH64_DLINK_FLAGS = $(ARCHDLINK_FLAGS) -Ttext=0x0 --emit-relocs -nostdlib -u $(IMAGE_ENTRY_POINT) -e $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
+
+ DEBUG_ARMLINUXGCC_AARCH64_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_AARCH64_CC_FLAGS) -Wno-address -O0
+RELEASE_ARMLINUXGCC_AARCH64_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_AARCH64_CC_FLAGS) -Wno-address -Wno-unused-but-set-variable
+
#################
# ASM 16 linker defintions
#################
Modified: trunk/BaseTools/Source/C/Common/BasePeCoff.c
===================================================================
--- trunk/BaseTools/Source/C/Common/BasePeCoff.c 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/C/Common/BasePeCoff.c 2013-07-31 10:43:59 UTC (rev 2590)
@@ -3,6 +3,7 @@
Functions to get info and load PE/COFF image.
Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.<BR>
+Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -79,6 +80,14 @@
IN UINT64 Adjust
);
+RETURN_STATUS
+PeCoffLoaderRelocateAArch64Image (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ );
+
STATIC
RETURN_STATUS
PeCoffLoaderGetPeHeader (
@@ -194,7 +203,8 @@
ImageContext->Machine != EFI_IMAGE_MACHINE_IA64 && \
ImageContext->Machine != EFI_IMAGE_MACHINE_X64 && \
ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_EBC) {
+ ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
+ ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64) {
if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
//
// There are two types of ARM images. Pure ARM and ARM/Thumb.
@@ -791,6 +801,9 @@
case EFI_IMAGE_MACHINE_IA64:
Status = PeCoffLoaderRelocateIpfImage (Reloc, Fixup, &FixupData, Adjust);
break;
+ case EFI_IMAGE_MACHINE_AARCH64:
+ Status = PeCoffLoaderRelocateAArch64Image (Reloc, Fixup, &FixupData, Adjust);
+ break;
default:
Status = RETURN_UNSUPPORTED;
break;
Modified: trunk/BaseTools/Source/C/Common/PeCoffLoaderEx.c
===================================================================
--- trunk/BaseTools/Source/C/Common/PeCoffLoaderEx.c 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/C/Common/PeCoffLoaderEx.c 2013-07-31 10:43:59 UTC (rev 2590)
@@ -1,6 +1,7 @@
/** @file
Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
+Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,7 +16,7 @@
Abstract:
- IA32, X64 and IPF Specific relocation fixups
+ IA32, X64, IPF, ARM and AArch64 Specific relocation fixups
Revision History
@@ -25,6 +26,7 @@
#include <IndustryStandard/PeImage.h>
#include "PeCoffLib.h"
#include "CommonLib.h"
+#include "EfiUtilityMsgs.h"
#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
@@ -472,3 +474,43 @@
return RETURN_SUCCESS;
}
+
+RETURN_STATUS
+PeCoffLoaderRelocateAArch64Image (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+/**
+ Performs an AArch64 specific relocation fixup
+
+ @param Reloc Pointer to the relocation record
+ @param Fixup Pointer to the address to fix up
+ @param FixupData Pointer to a buffer to log the fixups
+ @param Adjust The offset to adjust the fixup
+
+ @retval RETURN_SUCCESS Success to perform relocation
+ @retval RETURN_UNSUPPORTED Unsupported.
+**/
+{
+ UINT64 *F64;
+
+ switch ((*Reloc) >> 12) {
+
+ case EFI_IMAGE_REL_BASED_DIR64:
+ F64 = (UINT64 *) Fixup;
+ *F64 = *F64 + (UINT64) Adjust;
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
+ *(UINT64 *)(*FixupData) = *F64;
+ *FixupData = *FixupData + sizeof(UINT64);
+ }
+ break;
+
+ default:
+ return RETURN_UNSUPPORTED;
+ }
+
+ return RETURN_SUCCESS;
+}
Modified: trunk/BaseTools/Source/C/GenFv/GenFvInternalLib.c
===================================================================
--- trunk/BaseTools/Source/C/GenFv/GenFvInternalLib.c 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/C/GenFv/GenFvInternalLib.c 2013-07-31 10:43:59 UTC (rev 2590)
@@ -1,6 +1,7 @@
/** @file
Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
+Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1580,6 +1581,11 @@
// Since the ARM reset vector is in the FV Header you really don't need a
// Volume Top File, but if you have one for some reason don't crash...
//
+ } else if (MachineType == EFI_IMAGE_MACHINE_AARCH64) {
+ //
+ // Since the AArch64 reset vector is in the FV Header you really don't need a
+ // Volume Top File, but if you have one for some reason don't crash...
+ //
} else {
Error (NULL, 0, 3000, "Invalid", "machine type=0x%X in PEI core.", MachineType);
return EFI_ABORTED;
@@ -1617,9 +1623,11 @@
This parses the FV looking for SEC and patches that address into the
beginning of the FV header.
- For ARM the reset vector is at 0x00000000 or 0xFFFF0000.
+ For ARM32 the reset vector is at 0x00000000 or 0xFFFF0000.
+ For AArch64 the reset vector is at 0x00000000.
+
This would commonly map to the first entry in the ROM.
- ARM Exceptions:
+ ARM32 Exceptions:
Reset +0
Undefined +4
SWI +8
@@ -1633,11 +1641,10 @@
2) Reset vector is data bytes FDF file and that code branches to reset vector
in the beginning of the FV (fixed size offset).
-
Need to have the jump for the reset vector at location zero.
We also need to store the address or PEI (if it exists).
We stub out a return from interrupt in case the debugger
- is using SWI.
+ is using SWI (not done for AArch64, not enough space in struct).
The optional entry to the common exception handler is
to support full featured exception handling from ROM and is currently
not support by this tool.
@@ -1664,10 +1671,14 @@
UINT16 MachineType;
EFI_PHYSICAL_ADDRESS PeiCorePhysicalAddress;
EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
- INT32 ResetVector[4]; // 0 - is branch relative to SEC entry point
+ INT32 ResetVector[4]; // ARM32:
+ // 0 - is branch relative to SEC entry point
// 1 - PEI Entry Point
// 2 - movs pc,lr for a SWI handler
// 3 - Place holder for Common Exception Handler
+ // AArch64: Used as UINT64 ResetVector[2]
+ // 0 - is branch relative to SEC entry point
+ // 1 - PEI Entry Point
//
// Verify input parameters
@@ -1727,7 +1738,7 @@
PeiCorePhysicalAddress += EntryPoint;
DebugMsg (NULL, 0, 9, "PeiCore physical entry point address", "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
- if (MachineType == EFI_IMAGE_MACHINE_ARMT) {
+ if (MachineType == EFI_IMAGE_MACHINE_ARMT || MachineType == EFI_IMAGE_MACHINE_AARCH64) {
memset (ResetVector, 0, sizeof (ResetVector));
// Address of PEI Core, if we have one
ResetVector[1] = (UINT32)PeiCorePhysicalAddress;
@@ -1767,7 +1778,7 @@
return EFI_ABORTED;
}
- if (MachineType != EFI_IMAGE_MACHINE_ARMT) {
+ if ((MachineType != EFI_IMAGE_MACHINE_ARMT) && (MachineType != EFI_IMAGE_MACHINE_AARCH64)) {
//
// If SEC is not ARM we have nothing to do
//
@@ -1821,32 +1832,61 @@
DebugMsg (NULL, 0, 9, "PeiCore physical entry point address", "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
}
+ if (MachineType == EFI_IMAGE_MACHINE_ARMT) {
+ // B SecEntryPoint - signed_immed_24 part +/-32MB offset
+ // on ARM, the PC is always 8 ahead, so we're not really jumping from the base address, but from base address + 8
+ ResetVector[0] = (INT32)(SecCorePhysicalAddress - FvInfo->BaseAddress - 8) >> 2;
+
+ if (ResetVector[0] > 0x00FFFFFF) {
+ Error (NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the start of the FV");
+ return EFI_ABORTED;
+ }
- // B SecEntryPoint - signed_immed_24 part +/-32MB offset
- // on ARM, the PC is always 8 ahead, so we're not really jumping from the base address, but from base address + 8
- ResetVector[0] = (INT32)(SecCorePhysicalAddress - FvInfo->BaseAddress - 8) >> 2;
+ // Add opcode for an uncondional branch with no link. AKA B SecEntryPoint
+ ResetVector[0] |= 0xEB000000;
- if (ResetVector[0] > 0x00FFFFFF) {
- Error (NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the start of the FV");
- return EFI_ABORTED;
- }
- // Add opcode for an uncondional branch with no link. AKA B SecEntryPoint
- ResetVector[0] |= 0xEB000000;
+ // Address of PEI Core, if we have one
+ ResetVector[1] = (UINT32)PeiCorePhysicalAddress;
+ // SWI handler movs pc,lr. Just in case a debugger uses SWI
+ ResetVector[2] = 0xE1B0F07E;
- // Address of PEI Core, if we have one
- ResetVector[1] = (UINT32)PeiCorePhysicalAddress;
-
- // SWI handler movs pc,lr. Just in case a debugger uses SWI
- ResetVector[2] = 0xE1B0F07E;
-
- // Place holder to support a common interrupt handler from ROM.
- // Currently not suppprted. For this to be used the reset vector would not be in this FV
- // and the exception vectors would be hard coded in the ROM and just through this address
- // to find a common handler in the a module in the FV.
- ResetVector[3] = 0;
+ // Place holder to support a common interrupt handler from ROM.
+ // Currently not suppprted. For this to be used the reset vector would not be in this FV
+ // and the exception vectors would be hard coded in the ROM and just through this address
+ // to find a common handler in the a module in the FV.
+ ResetVector[3] = 0;
+ } else if (MachineType == EFI_IMAGE_MACHINE_AARCH64) {
+ /* NOTE:
+ ARMT above has an entry in ResetVector[2] for SWI. The way we are using the ResetVector
+ array at the moment, for AArch64, does not allow us space for this as the header only
+ allows for a fixed amount of bytes at the start. If we are sure that UEFI will live
+ within the first 4GB of addressable RAM we could potensioally adopt the same ResetVector
+ layout as above. But for the moment we replace the four 32bit vectors with two 64bit
+ vectors in the same area of the Image heasder. This allows UEFI to start from a 64bit
+ base.
+ */
+
+ ((UINT64*)ResetVector)[0] = (UINT64)(SecCorePhysicalAddress - FvInfo->BaseAddress) >> 2;
+
+ // B SecEntryPoint - signed_immed_26 part +/-128MB offset
+ if ( ((UINT64*)ResetVector)[0] > 0x03FFFFFF) {
+ Error (NULL, 0, 3000, "Invalid", "SEC Entry point must be within 128MB of the start of the FV");
+ return EFI_ABORTED;
+ }
+ // Add opcode for an uncondional branch with no link. AKA B SecEntryPoint
+ ((UINT64*)ResetVector)[0] |= 0x14000000;
+
+ // Address of PEI Core, if we have one
+ ((UINT64*)ResetVector)[1] = (UINT64)PeiCorePhysicalAddress;
+
+ } else {
+ Error (NULL, 0, 3000, "Invalid", "Unknown ARM machine type");
+ return EFI_ABORTED;
+ }
+
//
// Copy to the beginning of the FV
//
@@ -1948,8 +1988,8 @@
//
// Verify machine type is supported
//
- if (*MachineType != EFI_IMAGE_MACHINE_IA32 && *MachineType != EFI_IMAGE_MACHINE_IA64 && *MachineType != EFI_IMAGE_MACHINE_X64 && *MachineType != EFI_IMAGE_MACHINE_EBC &&
- *MachineType != EFI_IMAGE_MACHINE_ARMT) {
+ if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType != EFI_IMAGE_MACHINE_IA64) && (*MachineType != EFI_IMAGE_MACHINE_X64) && (*MachineType != EFI_IMAGE_MACHINE_EBC) &&
+ (*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64)) {
Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32 file.");
return EFI_UNSUPPORTED;
}
@@ -2895,7 +2935,8 @@
return Status;
}
- if (ImageContext.Machine == EFI_IMAGE_MACHINE_ARMT) {
+ if ( (ImageContext.Machine == EFI_IMAGE_MACHINE_ARMT) ||
+ (ImageContext.Machine == EFI_IMAGE_MACHINE_AARCH64) ) {
mArm = TRUE;
}
@@ -3163,7 +3204,8 @@
return Status;
}
- if (ImageContext.Machine == EFI_IMAGE_MACHINE_ARMT) {
+ if ( (ImageContext.Machine == EFI_IMAGE_MACHINE_ARMT) ||
+ (ImageContext.Machine == EFI_IMAGE_MACHINE_AARCH64) ) {
mArm = TRUE;
}
Modified: trunk/BaseTools/Source/C/GenFw/Elf64Convert.c
===================================================================
--- trunk/BaseTools/Source/C/GenFw/Elf64Convert.c 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/C/GenFw/Elf64Convert.c 2013-07-31 10:43:59 UTC (rev 2590)
@@ -1,6 +1,7 @@
/** @file
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
@@ -146,8 +147,8 @@
Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
return FALSE;
}
- if (!((mEhdr->e_machine == EM_X86_64))) {
- Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64");
+ if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64))) {
+ Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64 or EM_AARCH64");
return FALSE;
}
if (mEhdr->e_version != EV_CURRENT) {
@@ -269,6 +270,7 @@
switch (mEhdr->e_machine) {
case EM_X86_64:
case EM_IA_64:
+ case EM_AARCH64:
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
break;
default:
@@ -412,6 +414,10 @@
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_IPF;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
+ case EM_AARCH64:
+ NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_AARCH64;
+ NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
+ break;
default:
VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
@@ -542,22 +548,55 @@
//
VerboseMsg ("Applying Relocations...");
for (Idx = 0; Idx < mEhdr->e_shnum; Idx++) {
+ //
+ // Determine if this is a relocation section.
+ //
Elf_Shdr *RelShdr = GetShdrByIndex(Idx);
if ((RelShdr->sh_type != SHT_REL) && (RelShdr->sh_type != SHT_RELA)) {
continue;
}
+
+ //
+ // Relocation section found. Now extract section information that the relocations
+ // apply to in the ELF data and the new COFF data.
+ //
SecShdr = GetShdrByIndex(RelShdr->sh_info);
SecOffset = mCoffSectionsOffset[RelShdr->sh_info];
+
+ //
+ // Only process relocations for the current filter type.
+ //
if (RelShdr->sh_type == SHT_RELA && (*Filter)(SecShdr)) {
UINT64 RelIdx;
+
+ //
+ // Determine the symbol table referenced by the relocation data.
+ //
Elf_Shdr *SymtabShdr = GetShdrByIndex(RelShdr->sh_link);
UINT8 *Symtab = (UINT8*)mEhdr + SymtabShdr->sh_offset;
+
+ //
+ // Process all relocation entries for this section.
+ //
for (RelIdx = 0; RelIdx < RelShdr->sh_size; RelIdx += (UINT32) RelShdr->sh_entsize) {
+
+ //
+ // Set pointer to relocation entry
+ //
Elf_Rela *Rel = (Elf_Rela *)((UINT8*)mEhdr + RelShdr->sh_offset + RelIdx);
+
+ //
+ // Set pointer to symbol table entry associated with the relocation entry.
+ //
Elf_Sym *Sym = (Elf_Sym *)(Symtab + ELF_R_SYM(Rel->r_info) * SymtabShdr->sh_entsize);
+
Elf_Shdr *SymShdr;
UINT8 *Targ;
+ //
+ // Check section header index found in symbol table and get the section
+ // header location.
+ //
if (Sym->st_shndx == SHN_UNDEF
|| Sym->st_shndx == SHN_ABS
|| Sym->st_shndx > mEhdr->e_shnum) {
@@ -566,11 +605,20 @@
SymShdr = GetShdrByIndex(Sym->st_shndx);
//
- // Note: r_offset in a memory address.
- // Convert it to a pointer in the coff file.
+ // Convert the relocation data to a pointer into the coff file.
//
+ // Note:
+ // r_offset is the virtual address of the storage unit to be relocated.
+ // sh_addr is the virtual address for the base of the section.
+ //
+ // r_offset in a memory address.
+ // Convert it to a pointer in the coff file.
+ //
Targ = mCoffFile + SecOffset + (Rel->r_offset - SecShdr->sh_addr);
+ //
+ // Determine how to handle each relocation type based on the machine type.
+ //
if (mEhdr->e_machine == EM_X86_64) {
switch (ELF_R_TYPE(Rel->r_info)) {
case R_X86_64_NONE:
@@ -618,8 +666,51 @@
default:
Error (NULL, 0, 3000, "Invalid", "%s unsupported ELF EM_X86_64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
}
+ } else if (mEhdr->e_machine == EM_AARCH64) {
+
+ // AARCH64 GCC uses RELA relocation, so all relocations have to be fixed up.
+ // As opposed to ARM32 using REL.
+
+ switch (ELF_R_TYPE(Rel->r_info)) {
+
+ case R_AARCH64_LD_PREL_LO19:
+ if (Rel->r_addend != 0 ) { /* TODO */
+ Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_LD_PREL_LO19 Need to fixup with addend!.");
+ }
+ break;
+
+ case R_AARCH64_CALL26:
+ if (Rel->r_addend != 0 ) { /* TODO */
+ Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_CALL26 Need to fixup with addend!.");
+ }
+ break;
+
+ case R_AARCH64_JUMP26:
+ if (Rel->r_addend != 0 ) { /* TODO : AArch64 '-O2' optimisation. */
+ Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_JUMP26 Need to fixup with addend!.");
+ }
+ break;
+
+ case R_AARCH64_ADR_PREL_PG_HI21:
+ // TODO : AArch64 'small' memory model.
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);
+ break;
+
+ case R_AARCH64_ADD_ABS_LO12_NC:
+ // TODO : AArch64 'small' memory model.
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);
+ break;
+
+ // Absolute relocations.
+ case R_AARCH64_ABS64:
+ *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ break;
+
+ default:
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
+ }
} else {
- Error (NULL, 0, 3000, "Invalid", "Not EM_X86_X64");
+ Error (NULL, 0, 3000, "Invalid", "Not a supported machine type");
}
}
}
@@ -673,6 +764,45 @@
default:
Error (NULL, 0, 3000, "Invalid", "%s unsupported ELF EM_X86_64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
}
+ } else if (mEhdr->e_machine == EM_AARCH64) {
+ // AArch64 GCC uses RELA relocation, so all relocations has to be fixed up. ARM32 uses REL.
+ switch (ELF_R_TYPE(Rel->r_info)) {
+ case R_AARCH64_LD_PREL_LO19:
+ break;
+
+ case R_AARCH64_CALL26:
+ break;
+
+ case R_AARCH64_JUMP26:
+ break;
+
+ case R_AARCH64_ADR_PREL_PG_HI21:
+ // TODO : AArch64 'small' memory model.
+ Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);
+ break;
+
+ case R_AARCH64_ADD_ABS_LO12_NC:
+ // TODO : AArch64 'small' memory model.
+ Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);
+ break;
+
+ case R_AARCH64_ABS64:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_DIR64);
+ break;
+
+ case R_AARCH64_ABS32:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_HIGHLOW);
+ break;
+
+ default:
+ Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
+ }
} else {
Error (NULL, 0, 3000, "Not Supported", "This tool does not support relocations for ELF with e_machine %u (processor type).", (unsigned) mEhdr->e_machine);
}
Modified: trunk/BaseTools/Source/C/GenFw/elf_common.h
===================================================================
--- trunk/BaseTools/Source/C/GenFw/elf_common.h 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/C/GenFw/elf_common.h 2013-07-31 10:43:59 UTC (rev 2590)
@@ -2,6 +2,7 @@
Ported ELF include files from FreeBSD
Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
+Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -183,6 +184,7 @@
#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ processor. */
#define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
#define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */
+#define EM_AARCH64 183 /* ARM 64bit Architecture */
/* Non-standard or deprecated. */
#define EM_486 6 /* Intel i486. */
@@ -543,6 +545,135 @@
#define R_386_TLS_DTPOFF32 36 /* GOT entry containing TLS offset */
#define R_386_TLS_TPOFF32 37 /* GOT entry of -ve static TLS offset */
+/* Null relocation */
+#define R_AARCH64_NONE 256 /* No relocation */
+/* Static AArch64 relocations */
+ /* Static data relocations */
+#define R_AARCH64_ABS64 257 /* S + A */
+#define R_AARCH64_ABS32 258 /* S + A */
+#define R_AARCH64_ABS16 259 /* S + A */
+#define R_AARCH64_PREL64 260 /* S + A - P */
+#define R_AARCH64_PREL32 261 /* S + A - P */
+#define R_AARCH64_PREL16 262 /* S + A - P */
+ /* Group relocations to create a 16, 32, 48, or 64 bit unsigned data value or address inline */
+#define R_AARCH64_MOVW_UABS_G0 263 /* S + A */
+#define R_AARCH64_MOVW_UABS_G0_NC 264 /* S + A */
+#define R_AARCH64_MOVW_UABS_G1 265 /* S + A */
+#define R_AARCH64_MOVW_UABS_G1_NC 266 /* S + A */
+#define R_AARCH64_MOVW_UABS_G2 267 /* S + A */
+#define R_AARCH64_MOVW_UABS_G2_NC 268 /* S + A */
+#define R_AARCH64_MOVW_UABS_G3 269 /* S + A */
+ /* Group relocations to create a 16, 32, 48, or 64 bit signed data or offset value inline */
+#define R_AARCH64_MOVW_SABS_G0 270 /* S + A */
+#define R_AARCH64_MOVW_SABS_G1 271 /* S + A */
+#define R_AARCH64_MOVW_SABS_G2 272 /* S + A */
+ /* Relocations to generate 19, 21 and 33 bit PC-relative addresses */
+#define R_AARCH64_LD_PREL_LO19 273 /* S + A - P */
+#define R_AARCH64_ADR_PREL_LO21 274 /* S + A - P */
+#define R_AARCH64_ADR_PREL_PG_HI21 275 /* Page(S+A) - Page(P) */
+#define R_AARCH64_ADR_PREL_PG_HI21_NC 276 /* Page(S+A) - Page(P) */
+#define R_AARCH64_ADD_ABS_LO12_NC 277 /* S + A */
+#define R_AARCH64_LDST8_ABS_LO12_NC 278 /* S + A */
+#define R_AARCH64_LDST16_ABS_LO12_NC 284 /* S + A */
+#define R_AARCH64_LDST32_ABS_LO12_NC 285 /* S + A */
+#define R_AARCH64_LDST64_ABS_LO12_NC 286 /* S + A */
+#define R_AARCH64_LDST128_ABS_LO12_NC 299 /* S + A */
+ /* Relocations for control-flow instructions - all offsets are a multiple of 4 */
+#define R_AARCH64_TSTBR14 279 /* S+A-P */
+#define R_AARCH64_CONDBR19 280 /* S+A-P */
+#define R_AARCH64_JUMP26 282 /* S+A-P */
+#define R_AARCH64_CALL26 283 /* S+A-P */
+ /* Group relocations to create a 16, 32, 48, or 64 bit PC-relative offset inline */
+#define R_AARCH64_MOVW_PREL_G0 287 /* S+A-P */
+#define R_AARCH64_MOVW_PREL_G0_NC 288 /* S+A-P */
+#define R_AARCH64_MOVW_PREL_G1 289 /* S+A-P */
+#define R_AARCH64_MOVW_PREL_G1_NC 290 /* S+A-P */
+#define R_AARCH64_MOVW_PREL_G2 291 /* S+A-P */
+#define R_AARCH64_MOVW_PREL_G2_NC 292 /* S+A-P */
+#define R_AARCH64_MOVW_PREL_G3 293 /* S+A-P */
+ /* Group relocations to create a 16, 32, 48, or 64 bit GOT-relative offsets inline */
+#define R_AARCH64_MOVW_GOTOFF_G0 300 /* G(S)-GOT */
+#define R_AARCH64_MOVW_GOTOFF_G0_NC 301 /* G(S)-GOT */
+#define R_AARCH64_MOVW_GOTOFF_G1 302 /* G(S)-GOT */
+#define R_AARCH64_MOVW_GOTOFF_G1_NC 303 /* G(S)-GOT */
+#define R_AARCH64_MOVW_GOTOFF_G2 304 /* G(S)-GOT */
+#define R_AARCH64_MOVW_GOTOFF_G2_NC 305 /* G(S)-GOT */
+#define R_AARCH64_MOVW_GOTOFF_G3 306 /* G(S)-GOT */
+ /* GOT-relative data relocations */
+#define R_AARCH64_GOTREL64 307 /* S+A-GOT */
+#define R_AARCH64_GOTREL32 308 /* S+A-GOT */
+ /* GOT-relative instruction relocations */
+#define R_AARCH64_GOT_LD_PREL19 309 /* G(S)-P */
+#define R_AARCH64_LD64_GOTOFF_LO15 310 /* G(S)-GOT */
+#define R_AARCH64_ADR_GOT_PAGE 311 /* Page(G(S))-Page(P) */
+#define R_AARCH64_LD64_GOT_LO12_NC 312 /* G(S) */
+#define R_AARCH64_LD64_GOTPAGE_LO15 313 /* G(S)-Page(GOT) */
+/* Relocations for thread-local storage */
+ /* General Dynamic TLS relocations */
+#define R_AARCH64_TLSGD_ADR_PREL21 512 /* G(TLSIDX(S+A)) - P */
+#define R_AARCH64_TLSGD_ADR_PAGE21 513 /* Page(G(TLSIDX(S+A))) - Page(P) */
+#define R_AARCH64_TLSGD_ADD_LO12_NC 514 /* G(TLSIDX(S+A)) */
+#define R_AARCH64_TLSGD_MOVW_G1 515 /* G(TLSIDX(S+A)) - GOT */
+#define R_AARCH64_TLSGD_MOVW_G0_NC 516 /* G(TLSIDX(S+A)) - GOT */
+ /* Local Dynamic TLS relocations */
+#define R_AARCH64_TLSLD_ADR_PREL21 517 /* G(LDM(S))) - P */
+#define R_AARCH64_TLSLD_ADR_PAGE21 518 /* Page(G(LDM(S)))-Page(P) */
+#define R_AARCH64_TLSLD_ADD_LO12_NC 519 /* G(LDM(S)) */
+#define R_AARCH64_TLSLD_MOVW_G1 520 /* G(LDM(S)) - GOT */
+#define R_AARCH64_TLSLD_MOVW_G0_NC 521 /* G(LDM(S)) - GOT */
+#define R_AARCH64_TLSLD_LD_PREL19 522 /* G(LDM(S)) - P */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 527 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 /* DTPREL(S+A) */
+ /* Initial Exec TLS relocations */
+#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 /* G(TPREL(S+A)) - GOT */
+#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 /* G(TPREL(S+A)) - GOT */
+#define R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 /* Page(G(TPREL(S+A))) - Page(P) */
+#define R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 /* G(TPREL(S+A)) */
+#define R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 /* G(TPREL(S+A)) - P */
+ /* Local Exec TLS relocations */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G2 544 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G1 545 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G1_NC 546 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G0 547 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G0_NC 548 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_ADD_TPREL_HI12 549 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_ADD_TPREL_LO12 550 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_ADD_TPREL_LO12_NC 551 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_LDST8_TPREL_LO12 552 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 553 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_LDST16_TPREL_LO12 554 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 555 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_LDST32_TPREL_LO12 556 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 557 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_LDST64_TPREL_LO12 558 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 559 /* TPREL(S+A) */
+/* Dynamic relocations */
+ /* Dynamic relocations */
+#define R_AARCH64_COPY 1024
+#define R_AARCH64_GLOB_DAT 1025 /* S + A */
+#define R_AARCH64_JUMP_SLOT 1026 /* S + A */
+#define R_AARCH64_RELATIVE 1027 /* Delta(S) + A , Delta(P) + A */
+#define R_AARCH64_TLS_DTPREL64 1028 /* DTPREL(S+A) */
+#define R_AARCH64_TLS_DTPMOD64 1029 /* LDM(S) */
+#define R_AARCH64_TLS_TPREL64 1030 /* TPREL(S+A) */
+#define R_AARCH64_TLS_DTPREL32 1031 /* DTPREL(S+A) */
+#define R_AARCH64_TLS_DTPMOD32 1032 /* LDM(S) */
+#define R_AARCH64_TLS_TPREL32 1033 /* DTPREL(S+A) */
+
#define R_ALPHA_NONE 0 /* No reloc */
#define R_ALPHA_REFLONG 1 /* Direct 32 bit */
#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */
Added: trunk/BaseTools/Source/C/Include/AArch64/ProcessorBind.h
===================================================================
--- trunk/BaseTools/Source/C/Include/AArch64/ProcessorBind.h (rev 0)
+++ trunk/BaseTools/Source/C/Include/AArch64/ProcessorBind.h 2013-07-31 10:43:59 UTC (rev 2590)
@@ -0,0 +1,159 @@
+/** @file
+ Processor or Compiler specific defines and types for AArch64.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PROCESSOR_BIND_H__
+#define __PROCESSOR_BIND_H__
+
+///
+/// Define the processor type so other code can make processor based choices
+///
+#define MDE_CPU_AARCH64
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#ifndef __GNUC__
+#pragma pack()
+#endif
+
+#if _MSC_EXTENSIONS
+ //
+ // use Microsoft* C complier dependent integer width types
+ //
+ typedef unsigned __int64 UINT64;
+ typedef __int64 INT64;
+ typedef unsigned __int32 UINT32;
+ typedef __int32 INT32;
+ typedef unsigned short UINT16;
+ typedef unsigned short CHAR16;
+ typedef short INT16;
+ typedef unsigned char BOOLEAN;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef signed char INT8;
+#else
+ //
+ // Assume standard AARCH64 alignment.
+ //
+ typedef unsigned long long UINT64;
+ typedef long long INT64;
+ typedef unsigned int UINT32;
+ typedef int INT32;
+ typedef unsigned short UINT16;
+ typedef unsigned short CHAR16;
+ typedef short INT16;
+ typedef unsigned char BOOLEAN;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef signed char INT8;
+
+ #define UINT8_MAX 0xff
+#endif
+
+///
+/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef UINT64 UINTN;
+
+///
+/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef INT64 INTN;
+
+//
+// Processor specific defines
+//
+
+///
+/// A value of native width with the highest bit set.
+///
+#define MAX_BIT 0x8000000000000000
+
+///
+/// A value of native width with the two highest bits set.
+///
+#define MAX_2_BITS 0xC000000000000000
+
+///
+/// Maximum legal AARCH64 address
+///
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFF
+
+///
+/// The stack alignment required for AARCH64
+///
+#define CPU_STACK_ALIGNMENT 16
+
+//
+// Modifier to ensure that all protocol member functions and EFI intrinsics
+// use the correct C calling convention. All protocol member functions and
+// EFI intrinsics are required to modify their member functions with EFIAPI.
+//
+#define EFIAPI
+
+#if defined(__GNUC__)
+ ///
+ /// For GNU assembly code, .global or .globl can declare global symbols.
+ /// Define this macro to unify the usage.
+ ///
+ #define ASM_GLOBAL .globl
+
+ #if !defined(__APPLE__)
+ ///
+ /// ARM EABI defines that the linker should not manipulate call relocations
+ /// (do bl/blx conversion) unless the target symbol has function type.
+ /// CodeSourcery 2010.09 started requiring the .type to function properly
+ ///
+ #define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function
+
+ #define GCC_ASM_EXPORT(func__) \
+ .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
+ .type ASM_PFX(func__), %function
+
+ #define GCC_ASM_IMPORT(func__) \
+ .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
+
+ #else
+ //
+ // .type not supported by Apple Xcode tools
+ //
+ #define INTERWORK_FUNC(func__)
+
+ #define GCC_ASM_EXPORT(func__) \
+ .globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \
+
+ #define GCC_ASM_IMPORT(name)
+
+ #endif
+#endif
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On ARM CPU architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#endif
+
Property changes on: trunk/BaseTools/Source/C/Include/AArch64/ProcessorBind.h
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Modified: trunk/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
===================================================================
--- trunk/BaseTools/Source/C/Include/IndustryStandard/PeImage.h 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/C/Include/IndustryStandard/PeImage.h 2013-07-31 10:43:59 UTC (rev 2590)
@@ -5,6 +5,7 @@
@bug Fix text - doc as defined in MSFT EFI specification.
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
@@ -48,6 +49,7 @@
#define IMAGE_FILE_MACHINE_X64 0x8664
#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/Thumb 2 Little Endian
+#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Little Endian
//
// Support old names for backward compatible
@@ -58,6 +60,7 @@
#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
+#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
#define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
#define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
Modified: trunk/BaseTools/Source/Python/Common/DataType.py
===================================================================
--- trunk/BaseTools/Source/Python/Common/DataType.py 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/Python/Common/DataType.py 2013-07-31 10:43:59 UTC (rev 2590)
@@ -2,6 +2,7 @@
# This file is used to define common static strings used by INF/DEC/DSC files
#
# Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -51,8 +52,9 @@
TAB_ARCH_IPF = 'IPF'
TAB_ARCH_ARM = 'ARM'
TAB_ARCH_EBC = 'EBC'
+TAB_ARCH_AARCH64 = 'AARCH64'
-ARCH_LIST = [TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_IPF, TAB_ARCH_ARM, TAB_ARCH_EBC]
+ARCH_LIST = [TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_IPF, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64]
ARCH_LIST_FULL = [TAB_ARCH_COMMON] + ARCH_LIST
SUP_MODULE_BASE = 'BASE'
@@ -118,6 +120,7 @@
TAB_SOURCES_IPF = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_IPF
TAB_SOURCES_ARM = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_ARM
TAB_SOURCES_EBC = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_EBC
+TAB_SOURCES_AARCH64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_BINARIES = 'Binaries'
TAB_BINARIES_COMMON = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_COMMON
@@ -126,6 +129,7 @@
TAB_BINARIES_IPF = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_IPF
TAB_BINARIES_ARM = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_ARM
TAB_BINARIES_EBC = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_EBC
+TAB_BINARIES_AARCH64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_INCLUDES = 'Includes'
TAB_INCLUDES_COMMON = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_COMMON
@@ -134,6 +138,7 @@
TAB_INCLUDES_IPF = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_IPF
TAB_INCLUDES_ARM = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_ARM
TAB_INCLUDES_EBC = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_EBC
+TAB_INCLUDES_AARCH64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_GUIDS = 'Guids'
TAB_GUIDS_COMMON = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_COMMON
@@ -142,6 +147,7 @@
TAB_GUIDS_IPF = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_IPF
TAB_GUIDS_ARM = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_ARM
TAB_GUIDS_EBC = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_EBC
+TAB_GUIDS_AARCH64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_PROTOCOLS = 'Protocols'
TAB_PROTOCOLS_COMMON = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_COMMON
@@ -150,6 +156,7 @@
TAB_PROTOCOLS_IPF = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_IPF
TAB_PROTOCOLS_ARM = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_ARM
TAB_PROTOCOLS_EBC = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_EBC
+TAB_PROTOCOLS_AARCH64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_PPIS = 'Ppis'
TAB_PPIS_COMMON = TAB_PPIS + TAB_SPLIT + TAB_ARCH_COMMON
@@ -158,6 +165,7 @@
TAB_PPIS_IPF = TAB_PPIS + TAB_SPLIT + TAB_ARCH_IPF
TAB_PPIS_ARM = TAB_PPIS + TAB_SPLIT + TAB_ARCH_ARM
TAB_PPIS_EBC = TAB_PPIS + TAB_SPLIT + TAB_ARCH_EBC
+TAB_PPIS_AARCH64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_LIBRARY_CLASSES = 'LibraryClasses'
TAB_LIBRARY_CLASSES_COMMON = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_COMMON
@@ -166,6 +174,7 @@
TAB_LIBRARY_CLASSES_IPF = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_IPF
TAB_LIBRARY_CLASSES_ARM = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_ARM
TAB_LIBRARY_CLASSES_EBC = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_EBC
+TAB_LIBRARY_CLASSES_AARCH64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_PACKAGES = 'Packages'
TAB_PACKAGES_COMMON = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_COMMON
@@ -174,6 +183,7 @@
TAB_PACKAGES_IPF = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_IPF
TAB_PACKAGES_ARM = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_ARM
TAB_PACKAGES_EBC = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_EBC
+TAB_PACKAGES_AARCH64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_PCDS = 'Pcds'
TAB_PCDS_FIXED_AT_BUILD = 'FixedAtBuild'
@@ -201,6 +211,7 @@
TAB_PCDS_FIXED_AT_BUILD_IPF = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_IPF
TAB_PCDS_FIXED_AT_BUILD_ARM = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_FIXED_AT_BUILD_EBC = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_EBC
+TAB_PCDS_FIXED_AT_BUILD_AARCH64 = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_PCDS_PATCHABLE_IN_MODULE_NULL = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE
TAB_PCDS_PATCHABLE_IN_MODULE_COMMON = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_COMMON
@@ -209,6 +220,7 @@
TAB_PCDS_PATCHABLE_IN_MODULE_IPF = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_IPF
TAB_PCDS_PATCHABLE_IN_MODULE_ARM = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_PATCHABLE_IN_MODULE_EBC = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_EBC
+TAB_PCDS_PATCHABLE_IN_MODULE_AARCH64 = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_PCDS_FEATURE_FLAG_NULL = TAB_PCDS + TAB_PCDS_FEATURE_FLAG
TAB_PCDS_FEATURE_FLAG_COMMON = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_COMMON
@@ -217,6 +229,7 @@
TAB_PCDS_FEATURE_FLAG_IPF = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_IPF
TAB_PCDS_FEATURE_FLAG_ARM = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_FEATURE_FLAG_EBC = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_EBC
+TAB_PCDS_FEATURE_FLAG_AARCH64 = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_PCDS_DYNAMIC_EX_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC_EX
TAB_PCDS_DYNAMIC_EX_DEFAULT_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC_EX_DEFAULT
@@ -228,6 +241,7 @@
TAB_PCDS_DYNAMIC_EX_IPF = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_IPF
TAB_PCDS_DYNAMIC_EX_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_DYNAMIC_EX_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_EBC
+TAB_PCDS_DYNAMIC_EX_AARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_PCDS_DYNAMIC_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC
TAB_PCDS_DYNAMIC_DEFAULT_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC_DEFAULT
@@ -239,6 +253,7 @@
TAB_PCDS_DYNAMIC_IPF = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_IPF
TAB_PCDS_DYNAMIC_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_DYNAMIC_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_EBC
+TAB_PCDS_DYNAMIC_AARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_PCD_DYNAMIC_TYPE_LIST = [TAB_PCDS_DYNAMIC_DEFAULT_NULL, TAB_PCDS_DYNAMIC_VPD_NULL, TAB_PCDS_DYNAMIC_HII_NULL]
TAB_PCD_DYNAMIC_EX_TYPE_LIST = [TAB_PCDS_DYNAMIC_EX_DEFAULT_NULL, TAB_PCDS_DYNAMIC_EX_VPD_NULL, TAB_PCDS_DYNAMIC_EX_HII_NULL]
@@ -263,6 +278,7 @@
TAB_DEPEX_IPF = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_IPF
TAB_DEPEX_ARM = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_ARM
TAB_DEPEX_EBC = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_EBC
+TAB_DEPEX_AARCH64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_SKUIDS = 'SkuIds'
@@ -273,6 +289,7 @@
TAB_LIBRARIES_IPF = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_IPF
TAB_LIBRARIES_ARM = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_ARM
TAB_LIBRARIES_EBC = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_EBC
+TAB_LIBRARIES_AARCH64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_COMPONENTS = 'Components'
TAB_COMPONENTS_COMMON = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_COMMON
@@ -281,6 +298,7 @@
TAB_COMPONENTS_IPF = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_IPF
TAB_COMPONENTS_ARM = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_ARM
TAB_COMPONENTS_EBC = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_EBC
+TAB_COMPONENTS_AARCH64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_AARCH64
TAB_COMPONENTS_SOURCE_OVERRIDE_PATH = 'SOURCE_OVERRIDE_PATH'
Modified: trunk/BaseTools/Source/Python/Common/EdkIIWorkspaceBuild.py
===================================================================
--- trunk/BaseTools/Source/Python/Common/EdkIIWorkspaceBuild.py 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/Python/Common/EdkIIWorkspaceBuild.py 2013-07-31 10:43:59 UTC (rev 2590)
@@ -405,7 +405,7 @@
#
# @var WorkspaceDir: To store value for WorkspaceDir
# @var SupArchList: To store value for SupArchList, selection scope is in below list
-# EBC | IA32 | X64 | IPF | ARM | PPC
+# EBC | IA32 | X64 | IPF | ARM | PPC | AARCH64
# @var BuildTarget: To store value for WorkspaceDir, selection scope is in below list
# RELEASE | DEBUG
# @var SkuId: To store value for SkuId
Modified: trunk/BaseTools/Source/Python/Common/FdfParserLite.py
===================================================================
--- trunk/BaseTools/Source/Python/Common/FdfParserLite.py 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/Python/Common/FdfParserLite.py 2013-07-31 10:43:59 UTC (rev 2590)
@@ -2769,7 +2769,7 @@
raise Warning("expected '.' At Line ", self.FileName, self.CurrentLineNumber)
Arch = self.__SkippedChars.rstrip(".")
- if Arch.upper() not in ("IA32", "X64", "IPF", "EBC", "ARM", "COMMON"):
+ if Arch.upper() not in ("IA32", "X64", "IPF", "EBC", "ARM", "AARCH64", "COMMON"):
raise Warning("Unknown Arch '%s'" % Arch, self.FileName, self.CurrentLineNumber)
ModuleType = self.__GetModuleType()
@@ -3356,7 +3356,7 @@
raise Warning("expected '.' At Line ", self.FileName, self.CurrentLineNumber)
Arch = self.__SkippedChars.rstrip(".").upper()
- if Arch not in ("IA32", "X64", "IPF", "ARM"):
+ if Arch not in ("IA32", "X64", "IPF", "ARM", "AARCH64"):
raise Warning("Unknown Arch At line ", self.FileName, self.CurrentLineNumber)
if not self.__GetNextWord():
@@ -3370,7 +3370,7 @@
if self.__IsToken(","):
if not self.__GetNextWord():
raise Warning("expected Arch list At Line ", self.FileName, self.CurrentLineNumber)
- if self.__Token.upper() not in ("IA32", "X64", "IPF", "ARM"):
+ if self.__Token.upper() not in ("IA32", "X64", "IPF", "ARM", "AARCH64"):
raise Warning("Unknown Arch At line ", self.FileName, self.CurrentLineNumber)
VtfObj.ArchList = self.__Token.upper()
Modified: trunk/BaseTools/Source/Python/Common/MigrationUtilities.py
===================================================================
--- trunk/BaseTools/Source/Python/Common/MigrationUtilities.py 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/Python/Common/MigrationUtilities.py 2013-07-31 10:43:59 UTC (rev 2590)
@@ -360,7 +360,7 @@
# The possible duplication is ensured to be removed.
#
# @param Section Section dictionary indexed by CPU architecture.
-# @param Arch CPU architecture: Ia32, X64, Ipf, ARM, Ebc or Common.
+# @param Arch CPU architecture: Ia32, X64, Ipf, ARM, AARCH64, Ebc or Common.
# @param Item The Item to be added to section dictionary.
#
def AddToSection(Section, Arch, Item):
@@ -382,7 +382,7 @@
# @retval Section The string content of a section.
#
def GetSection(SectionName, Method, ObjectList):
- SupportedArches = ["common", "Ia32", "X64", "Ipf", "Ebc", "ARM"]
+ SupportedArches = ["common", "Ia32", "X64", "Ipf", "Ebc", "ARM", "AARCH64"]
SectionDict = {}
for Object in ObjectList:
Item = Method(Object)
Modified: trunk/BaseTools/Source/Python/CommonDataClass/CommonClass.py
===================================================================
--- trunk/BaseTools/Source/Python/CommonDataClass/CommonClass.py 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/Python/CommonDataClass/CommonClass.py 2013-07-31 10:43:59 UTC (rev 2590)
@@ -38,7 +38,7 @@
# ALWAYS_CONSUMED | SOMETIMES_CONSUMED | ALWAYS_PRODUCED | SOMETIMES_PRODUCED | TO_START | BY_START | PRIVATE
# @var FeatureFlag: To store value for FeatureFlag
# @var SupArchList: To store value for SupArchList, selection scope is in below list
-# EBC | IA32 | X64 | IPF | ARM | PPC
+# EBC | IA32 | X64 | IPF | ARM | PPC | AARCH64
# @var HelpText: To store value for HelpText
#
class CommonClass(object):
@@ -400,7 +400,7 @@
# @var TagName: To store value for TagName
# @var ToolCode: To store value for ToolCode
# @var SupArchList: To store value for SupArchList, selection scope is in below list
-# EBC | IA32 | X64 | IPF | ARM | PPC
+# EBC | IA32 | X64 | IPF | ARM | PPC | AARCH64
#
class BuildOptionClass(IncludeStatementClass):
def __init__(self, ToolChainFamily = '', ToolChain = '', Option = ''):
Modified: trunk/BaseTools/Source/Python/CommonDataClass/ModuleClass.py
===================================================================
--- trunk/BaseTools/Source/Python/CommonDataClass/ModuleClass.py 2013-07-19 06:39:08 UTC (rev 2589)
+++ trunk/BaseTools/Source/Python/CommonDataClass/ModuleClass.py 2013-07-31 10:43:59 UTC (rev 2590)
@@ -25,7 +25,7 @@
#
# @var ModuleType: To store value for ModuleType
# @var SupArchList: To store value for SupArchList, selection scope is in below list
-# EBC | IA32 | X64 | IPF | ARM | PPC
+# EBC | IA32 | X64 | IPF | ARM | PPC | AARCH64
# @var BinaryModule: To store value for BinaryModule
# @var OutputFileBasename: To store value for OutputFileBase...
[truncated message content] |
