ClockSkew modified by Anonymous

Anonymous — Mon, 16 Mar 2015 20:30:19 -0000

While the original paper focused on six broader topics, we will focus on clock skew, the "chief difficulty in designing high-speed synchronous systems." (Hatamian, 1987)

Main points

Min delay effects in
1. edge-triggered system
2. level-triggered
3. two-phase
Clock period effects in
1. edge-triggered system
2. level-triggered
3. two-phase
Techniques to handle clock skew
1. Buffering
2. Distribution networks

Effects include:

Latency
Throughput

Variables

Tpt - cell propagation time
Tst - cell computation delay or settling time
Tsr - register settling time
Tpr - register propagation time
Tck - clock skew with respect to a global reference
Tpi - interconnect propagation time
Notes:
propagation delay is the earliest change in the output
settling time is when the output has settled
The paper assumes the same values in all modules of the pipeline; we will not relax that assumption here.

Some sample code to demonstrate delay modeling in vhdl:

begin
    process(clk)
    begin
        if clk'event and clk='1' then --just use "clk='1'" for single-phase model
                R1 <= R1in;
        R2 <= transport C1out after delta;
        end if;
    end process;

    R1out(0) <= transport R1(0) after tpr;
    R1out(1) <= transport R1(1) after tsr;
    C1in <= transport R1out after tpi;
    C1 = C1in + 1;
    C1out(0) <= transport C1(0) after tpl;
    C1out(1) <= transport C1(1) after tsl;

end architecture;

Recent changes to ClockSkew

ClockSkew modified by Anonymous