PCB top/bottom not visible? [FC 0.19, FC-PCB latest Addon Mgr version]

[David Smart]

This is quite curious, but things happen... I updated to the released version of FreeCAD 0.19. Moments ago I also updated via the Addon manager to the latest FreeCAD-PCB. Suggestion: in the add-on manager, can you show a version/release number to reference?

The oddity today is that the PCB top/bottom layer is not visible, but everything else is, including traces, annular rings and parts.

It seems quite possible that I altered a setting to cause this but I'm not sure where it would be. the "edge" of the PCB shows in the color selected in the Preference dialog.

.brd file from Eagle 7.7.0.

Example attached, and thanks for any advice you can give!

[Mariusz]

Hello,
often one of these three things causes this behavior:
- overlapping holes
- shape of the edge is not closed (micro gap)
- the round corner is "inverted" (wrong direction)

[Anonymous]

Hi Marius,
I've been noodling on this - and made a mistake - I had two computers, almost identical versions of Eagle,the project of interest, and FreeCAD/FreeCAD-PCB. On the other computer it rendered correctly. As I was comparing files in the FreeCAD tree, only pyc files were actually different, and the component db. I compared model libraries as well, and there were minor library part differences, but nothing obvious. Then I compared projects - examining the XML files, and I didn't see a cause. Then the mistake. After merging (from working PC to not-rendering-correctly-PC) of all of these items , now they both do not render the PCB layer, but all other parts look good. I went back in my project history for an older version, and it does not render correctly.

I'm suspicious that it may be a library part that is somehow causing this.

Are there a few locations where I could add some report-view logging operations to narrow this down?

In the meantime, I'm going to revert to older 3d model components to see if that might be the cause.

[David Smart]

Ah, I didn't realize I wasn't logged in - yet it let me reply...
And other projects are rendering fine - so it seems to something about this one Eagle .brd project, or the 3d models that it uses (and others don't). Reverting the Eagle project/.brd file to an older version did not help. Reverting the 3d model libraries didn't go so well - so I can't rule that out yet. I did turn on logging during the import process, and there are a few errors - parts that have not been configured/rendered, but maybe there is something else in there. I'm attaching that report.

[Mariusz]

Hello,
In my opinion, one of the models causes this error. Without the brd file it will be hard to find the reason, but try to import it without holes. Later import without this model: DRILEGEND.

[David Smart]

Thank you for your ongoing help!

I fixed a few component models that were not rendering, but the problem remained.

I did import with the option to exclude holes, and then it renders as it should.

The pcb in this model is generated not in the Eagle pcb layout directly, but from a library part which is sized to fit into a standard enclosure. I'll check out this Eagle lib part and see if I can sort out if there are duplicate or overlapping holes. There are 4 mounting holes (which I'll verify).

Update: As noted above, I had a component with no PCB features (no holes or pads). This was named for the standard Bud Industries enclosure. The footprint for this part was intended to be the PCB itself - the outline on the dimension layer to fit the enclosure, along with mounting holes. The generated gerber files worked, I have PCBs. As described here, I think FreeCAD-PCB does not recognize the board information that is not in the <plain> section.</plain>

But in the project shown above I apparently replicated those features (outline, holes) to appear in the Eagle .brd <plain> section, where these features would normally exist. I think because of this, there were [mounting] holes directly on top of each other - causing the problem.</plain>

class EaglePCB(baseModel):
    def __init__(self, filename, parent):
        self.fileName = filename
        self.dialogMAIN = dialogMAIN(self.fileName)
        self.databaseType = "eagle"
        self.parent = parent
        #
        self.libraries = {}
        self.elements = []

    def setProject(self):
        self.projektBRD = minidom.parse(self.fileName)

    def getPCB(self, borderObject):
        dane = self.getSection('plain')

        for i in self.getWires(dane, 20):

I've been experimenting to see if there is an easy solution - to leverage this library part which represented the standard PCB form, and not have to redraw a complex outline for each design. I do not yet have a solution.

That theory makes sense based on what I see in eagle.py, although the LOC after that snippet appear that they do inspect other components...

From my .brd file

<library name="Enclosures-PCBs">
<packages>
<package name="ENCLOSURE-BUD-HP-3651-B">
<description>&lt;b&gt;Bud Industries Enclosure - HP-3651-B PCB&lt;/b&gt;&lt;br/&gt;</description>
<wire x1="49.9618" y1="20.9042" x2="53.2892" y2="17.5768" width="0.127" layer="20" curve="90"/>
<wire x1="53.2892" y1="24.2316" x2="49.9618" y2="20.9042" width="0.127" layer="20" curve="90"/>
<wire x1="53.3146" y1="58.42" x2="49.9872" y2="61.7474" width="0.127" layer="20" curve="-90"/>
<wire x1="49.9872" y1="61.7474" x2="53.3146" y2="65.0748" width="0.127" layer="20" curve="-90"/>
<wire x1="3.302" y1="65.0748" x2="6.6294" y2="61.7474" width="0.127" layer="20" curve="-90"/>
<wire x1="6.6294" y1="61.7474" x2="3.302" y2="58.42" width="0.127" layer="20" curve="-90"/>
<wire x1="6.604" y1="20.9042" x2="3.2766" y2="24.2316" width="0.127" layer="20" curve="90"/>
<wire x1="3.2766" y1="17.5768" x2="6.604" y2="20.9042" width="0.127" layer="20" curve="90"/>
<hole x="42.3164" y="68.326" drill="3.2"/>
<hole x="14.3256" y="14.3002" drill="3.2"/>
<hole x="42.3164" y="14.3256" drill="3.2"/>
<circle x="42.3164" y="68.326" radius="3.175" width="0.127" layer="39"/>
<circle x="14.3256" y="14.3002" radius="3.175" width="0.127" layer="39"/>
<circle x="42.3164" y="14.3256" radius="3.175" width="0.127" layer="39"/>
<circle x="14.3256" y="14.3002" radius="3.175" width="0.127" layer="40"/>
<circle x="42.3164" y="14.3256" radius="3.175" width="0.127" layer="40"/>
<circle x="42.3164" y="68.326" radius="3.175" width="0.127" layer="40"/>
<wire x1="0" y1="0" x2="56.6166" y2="0" width="0.127" layer="20"/>
<wire x1="56.6166" y1="0" x2="56.6166" y2="17.5768" width="0.127" layer="20"/>
<wire x1="49.9618" y1="20.9042" x2="53.2892" y2="17.5768" width="0.127" layer="20" curve="90"/>
<wire x1="53.2892" y1="17.5768" x2="56.6166" y2="17.5768" width="0.127" layer="20"/>
<wire x1="56.6166" y1="24.2316" x2="53.2892" y2="24.2316" width="0.127" layer="20"/>
<wire x1="53.2892" y1="24.2316" x2="49.9618" y2="20.9042" width="0.127" layer="20" curve="90"/>
<wire x1="56.6166" y1="24.2316" x2="56.6166" y2="58.42" width="0.127" layer="20"/>
<wire x1="56.6166" y1="58.42" x2="53.3146" y2="58.42" width="0.127" layer="20"/>
<wire x1="53.3146" y1="58.42" x2="49.9872" y2="61.7474" width="0.127" layer="20" curve="-90"/>
<wire x1="49.9872" y1="61.7474" x2="53.3146" y2="65.0748" width="0.127" layer="20" curve="-90"/>
<wire x1="53.3146" y1="65.0748" x2="56.6166" y2="65.0748" width="0.127" layer="20"/>
<wire x1="56.6166" y1="65.0748" x2="56.6166" y2="82.6516" width="0.127" layer="20"/>
<wire x1="56.6166" y1="82.6516" x2="0" y2="82.6516" width="0.127" layer="20"/>
<wire x1="0" y1="82.6516" x2="0" y2="65.0748" width="0.127" layer="20"/>
<wire x1="0" y1="65.0748" x2="3.302" y2="65.0748" width="0.127" layer="20"/>
<wire x1="3.302" y1="65.0748" x2="6.6294" y2="61.7474" width="0.127" layer="20" curve="-90"/>
<wire x1="6.6294" y1="61.7474" x2="3.302" y2="58.42" width="0.127" layer="20" curve="-90"/>
<wire x1="3.302" y1="58.42" x2="0" y2="58.42" width="0.127" layer="20"/>
<wire x1="0" y1="58.42" x2="0" y2="24.2316" width="0.127" layer="20"/>
<wire x1="6.604" y1="20.9042" x2="3.2766" y2="24.2316" width="0.127" layer="20" curve="90"/>
<wire x1="3.2766" y1="24.2316" x2="0" y2="24.2316" width="0.127" layer="20"/>
<wire x1="0" y1="17.5768" x2="3.2766" y2="17.5768" width="0.127" layer="20"/>
<wire x1="3.2766" y1="17.5768" x2="6.604" y2="20.9042" width="0.127" layer="20" curve="90"/>
<wire x1="0" y1="17.5768" x2="0" y2="0" width="0.127" layer="20"/>
<hole x="14.3256" y="68.326" drill="3.2"/>
<circle x="14.3256" y="68.326" radius="3.175" width="0.127" layer="39"/>
<circle x="14.3256" y="68.326" radius="3.175" width="0.127" layer="40"/>
</package>
</packages>
</library>

And further down in the .brd file ...

    <element name="U$1" library="Enclosures-PCBs" package="ENCLOSURE-BUD-HP-3651-B" value="BUD-HP-3651-B" x="50.8" y="50.8"/>
</elements>

[Mariusz]

Hello,
"I've been experimenting to see if there is an easy solution - to leverage this library part which represented the standard PCB form, and not have to redraw a complex outline for each design. I do not yet have a solution."
This is implemented for PCB holes and outlines :) - automatic process, so redrawing is not necessary.

About the error - model ENCLOSURE-BUD-HP-3651-B does it, as you noticed. There are double arcs in the lower section.
Load PCB (without redrawn contour lines), double click PCB-> Board-> PCB_Border. Delete double lines and close the sketcher. Other solution - update library in eagl

[David Smart]

SOLVED: With your expertise, this is solved. Thank you!