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From: GitLab M. <git...@ke...> - 2021-09-27 13:03:47
|
xf86drmMode.h | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
New commits:
commit 02ac4a0a36c2aabbd39dab0c7cd13ed2516a2bed
Author: Simon Ser <co...@em...>
Date: Tue Jun 15 14:48:28 2021 +0200
xf86drmMode: simplify drm_property_type_is
No need to have two branches depending on DRM_MODE_PROP_EXTENDED_TYPE.
We can just use drmModeGetPropertyType instead.
This does introduce a slight change: previously, drm_property_type_is()
could be called with non-type flags such as IMMUTABLE. However no user
seems to do this (checked KWin/Mutter/Sway/Weston/Xorg).
Signed-off-by: Simon Ser <co...@em...>
Reviewed-by: Emil Velikov <emi...@co...>
diff --git a/xf86drmMode.h b/xf86drmMode.h
index 14ffdf3d..de0e2fdb 100644
--- a/xf86drmMode.h
+++ b/xf86drmMode.h
@@ -142,18 +142,15 @@ typedef struct _drmModeProperty {
uint32_t *blob_ids; /* store the blob IDs */
} drmModePropertyRes, *drmModePropertyPtr;
-static inline int drm_property_type_is(const drmModePropertyPtr property,
- uint32_t type)
+static inline uint32_t drmModeGetPropertyType(const drmModePropertyRes *prop)
{
- /* instanceof for props.. handles extended type vs original types: */
- if (property->flags & DRM_MODE_PROP_EXTENDED_TYPE)
- return (property->flags & DRM_MODE_PROP_EXTENDED_TYPE) == type;
- return property->flags & type;
+ return prop->flags & (DRM_MODE_PROP_LEGACY_TYPE | DRM_MODE_PROP_EXTENDED_TYPE);
}
-static inline uint32_t drmModeGetPropertyType(const drmModePropertyRes *prop)
+static inline int drm_property_type_is(const drmModePropertyPtr property,
+ uint32_t type)
{
- return prop->flags & (DRM_MODE_PROP_LEGACY_TYPE | DRM_MODE_PROP_EXTENDED_TYPE);
+ return drmModeGetPropertyType(property) == type;
}
typedef struct _drmModeCrtc {
commit bb709e60233d457f0c63d7b77baaab80f264ba16
Author: Simon Ser <co...@em...>
Date: Tue Jun 15 14:47:04 2021 +0200
xf86drmMode: switch to standard inline qualifier
__inline is non-standard, inline is.
Signed-off-by: Simon Ser <co...@em...>
Reviewed-by: Emil Velikov <emi...@co...>
diff --git a/xf86drmMode.h b/xf86drmMode.h
index c1434e1d..14ffdf3d 100644
--- a/xf86drmMode.h
+++ b/xf86drmMode.h
@@ -142,7 +142,7 @@ typedef struct _drmModeProperty {
uint32_t *blob_ids; /* store the blob IDs */
} drmModePropertyRes, *drmModePropertyPtr;
-static __inline int drm_property_type_is(const drmModePropertyPtr property,
+static inline int drm_property_type_is(const drmModePropertyPtr property,
uint32_t type)
{
/* instanceof for props.. handles extended type vs original types: */
commit e939bd1e8c6737b6ae84c5e2f2045542e6e2beb5
Author: Simon Ser <co...@em...>
Date: Tue Jun 15 14:46:05 2021 +0200
xf86drmMode: make drm_property_type_is arg const
This function only needs read-only access to the property. This is
not a breaking ABI change.
Signed-off-by: Simon Ser <co...@em...>
Reviewed-by: Emil Velikov <emi...@co...>
diff --git a/xf86drmMode.h b/xf86drmMode.h
index 4bde6e35..c1434e1d 100644
--- a/xf86drmMode.h
+++ b/xf86drmMode.h
@@ -142,7 +142,7 @@ typedef struct _drmModeProperty {
uint32_t *blob_ids; /* store the blob IDs */
} drmModePropertyRes, *drmModePropertyPtr;
-static __inline int drm_property_type_is(drmModePropertyPtr property,
+static __inline int drm_property_type_is(const drmModePropertyPtr property,
uint32_t type)
{
/* instanceof for props.. handles extended type vs original types: */
|
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From: GitLab M. <git...@ke...> - 2022-01-20 17:55:02
|
amdgpu/amdgpu-symbols.txt | 1 +
amdgpu/amdgpu.h | 15 +++++++++++++++
amdgpu/amdgpu_cs.c | 22 ++++++++++++++++++++++
include/drm/amdgpu_drm.h | 32 +++++++++++++++++++++++---------
tests/amdgpu/basic_tests.c | 32 ++++++++++++++++++++++++++++++++
5 files changed, 93 insertions(+), 9 deletions(-)
New commits:
commit 847be2651fd02e452b59a7462e9829d87430a3d3
Author: Samuel Pitoiset <sam...@gm...>
Date: Mon Jan 3 10:21:00 2022 +0100
tests/amdgpu: add a test for new CTX OP to get/set stable pstates
Signed-off-by: Samuel Pitoiset <sam...@gm...>
Reviewed-by: Marek Olšák <mar...@am...>
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 0180f9ce..8afd05c1 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -62,6 +62,7 @@ static void amdgpu_compute_dispatch_test(void);
static void amdgpu_gfx_dispatch_test(void);
static void amdgpu_draw_test(void);
static void amdgpu_gpu_reset_test(void);
+static void amdgpu_stable_pstate_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -87,6 +88,7 @@ CU_TestInfo basic_tests[] = {
{ "Dispatch Test (GFX)", amdgpu_gfx_dispatch_test },
{ "Draw Test", amdgpu_draw_test },
{ "GPU reset Test", amdgpu_gpu_reset_test },
+ { "Stable pstate Test", amdgpu_stable_pstate_test },
CU_TEST_INFO_NULL,
};
#define BUFFER_SIZE (MAX2(8 * 1024, getpagesize()))
@@ -3881,3 +3883,33 @@ static void amdgpu_gpu_reset_test(void)
amdgpu_compute_dispatch_test();
amdgpu_gfx_dispatch_test();
}
+
+static void amdgpu_stable_pstate_test(void)
+{
+ int r;
+ amdgpu_context_handle context_handle;
+ uint32_t current_pstate = 0, new_pstate = 0;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_ctx_stable_pstate(context_handle,
+ AMDGPU_CTX_OP_GET_STABLE_PSTATE,
+ 0, ¤t_pstate);
+ CU_ASSERT_EQUAL(r, 0);
+ CU_ASSERT_EQUAL(new_pstate, AMDGPU_CTX_STABLE_PSTATE_NONE);
+
+ r = amdgpu_cs_ctx_stable_pstate(context_handle,
+ AMDGPU_CTX_OP_SET_STABLE_PSTATE,
+ AMDGPU_CTX_STABLE_PSTATE_PEAK, NULL);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_ctx_stable_pstate(context_handle,
+ AMDGPU_CTX_OP_GET_STABLE_PSTATE,
+ 0, &new_pstate);
+ CU_ASSERT_EQUAL(r, 0);
+ CU_ASSERT_EQUAL(new_pstate, AMDGPU_CTX_STABLE_PSTATE_PEAK);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ CU_ASSERT_EQUAL(r, 0);
+}
commit de84cdc563ecc0d054a20454a5fa4f00648548ba
Author: Samuel Pitoiset <sam...@gm...>
Date: Fri Dec 31 09:10:03 2021 +0100
amdgpu: implement new CTX OP to set/get stable pstates
Signed-off-by: Samuel Pitoiset <sam...@gm...>
Reviewed-by: Marek Olšák <mar...@am...>
diff --git a/amdgpu/amdgpu-symbols.txt b/amdgpu/amdgpu-symbols.txt
index af2b6439..d41d9c24 100644
--- a/amdgpu/amdgpu-symbols.txt
+++ b/amdgpu/amdgpu-symbols.txt
@@ -25,6 +25,7 @@ amdgpu_cs_ctx_create
amdgpu_cs_ctx_create2
amdgpu_cs_ctx_free
amdgpu_cs_ctx_override_priority
+amdgpu_cs_ctx_stable_pstate
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
amdgpu_cs_export_syncobj
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index cde8585c..5ef2524a 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -939,6 +939,21 @@ int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
int master_fd,
unsigned priority);
+/**
+ * Set or query the stable power state for GPU profiling.
+ *
+ * \param dev - \c [in] device handle
+ * \param op - \c [in] AMDGPU_CTX_OP_{GET,SET}_STABLE_PSTATE
+ * \param flags - \c [in] AMDGPU_CTX_STABLE_PSTATE_*
+ * \param out_flags - \c [out] output current stable pstate
+ *
+ * \return 0 on success otherwise POSIX Error code.
+ */
+int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context,
+ uint32_t op,
+ uint32_t flags,
+ uint32_t *out_flags);
+
/**
* Query reset state for the specific GPU Context
*
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index fad484bf..638fd7d6 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -167,6 +167,28 @@ drm_public int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
return 0;
}
+drm_public int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context,
+ uint32_t op,
+ uint32_t flags,
+ uint32_t *out_flags)
+{
+ union drm_amdgpu_ctx args;
+ int r;
+
+ if (!context)
+ return -EINVAL;
+
+ memset(&args, 0, sizeof(args));
+ args.in.op = op;
+ args.in.ctx_id = context->id;
+ args.in.flags = flags;
+ r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
+ &args, sizeof(args));
+ if (!r && out_flags)
+ *out_flags = args.out.pstate.flags;
+ return r;
+}
+
drm_public int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
uint32_t *state, uint32_t *hangs)
{
commit 94bc8144167eed215621ef61a3dd3435d4faf26e
Author: Samuel Pitoiset <sam...@gm...>
Date: Fri Dec 31 08:54:34 2021 +0100
amdgpu: update_drm.h for new CTX OP to set/get stable pstates
Based on agd5f/drm-next.
Signed-off-by: Samuel Pitoiset <sam...@gm...>
Reviewed-by: Marek Olšák <mar...@am...>
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 0cbd1540..7f01f983 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -80,7 +80,7 @@ extern "C" {
*
* %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
* GPU's virtual address space via gart. Gart memory linearizes non-contiguous
- * pages of system memory, allows GPU access system memory in a linezrized
+ * pages of system memory, allows GPU access system memory in a linearized
* fashion.
*
* %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
@@ -206,6 +206,8 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_OP_FREE_CTX 2
#define AMDGPU_CTX_OP_QUERY_STATE 3
#define AMDGPU_CTX_OP_QUERY_STATE2 4
+#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
+#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
/* GPU reset status */
#define AMDGPU_CTX_NO_RESET 0
@@ -238,10 +240,18 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_PRIORITY_HIGH 512
#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
+/* select a stable profiling pstate for perfmon tools */
+#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
+#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
+#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
+#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
+#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
+#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
+
struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
__u32 op;
- /** For future use, no flags defined so far */
+ /** Flags */
__u32 flags;
__u32 ctx_id;
/** AMDGPU_CTX_PRIORITY_* */
@@ -262,6 +272,11 @@ union drm_amdgpu_ctx_out {
/** Reset status since the last call of the ioctl. */
__u32 reset_status;
} state;
+
+ struct {
+ __u32 flags;
+ __u32 _pad;
+ } pstate;
};
union drm_amdgpu_ctx {
@@ -786,13 +801,6 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
/* query ras mask of enabled features*/
#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
-/* query video encode/decode caps */
-#define AMDGPU_INFO_VIDEO_CAPS 0x21
- /* Subquery id: Decode */
- #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
- /* Subquery id: Encode */
- #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
-
/* RAS MASK: UMC (VRAM) */
#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
/* RAS MASK: SDMA */
@@ -821,6 +829,12 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
/* RAS MASK: FUSE */
#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
+/* query video encode/decode caps */
+#define AMDGPU_INFO_VIDEO_CAPS 0x21
+ /* Subquery id: Decode */
+ #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
+ /* Subquery id: Encode */
+ #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
|
|
From: GitLab M. <git...@ke...> - 2022-05-09 13:13:55
|
tests/modeprint/modeprint.c | 2 +-
tests/modetest/modetest.c | 2 +-
tests/proptest/proptest.c | 2 +-
xf86drm.c | 3 ++-
4 files changed, 5 insertions(+), 4 deletions(-)
New commits:
commit ae6d81da2093b139ece952913f8f00dcc26ce7b9
Author: Eleni Maria Stea <ele...@gm...>
Date: Mon May 9 15:00:54 2022 +0300
tests/modeprint: fix argument type
Replaced the type PRId64 with PRIu64 in a printf as the argument was
unsigned to fix the related compiler warning.
Signed-off-by: Eleni Maria Stea <ele...@gm...>
Reviewed-by: Simon Ser <co...@em...>
diff --git a/tests/modeprint/modeprint.c b/tests/modeprint/modeprint.c
index 880269b0..9372ad92 100644
--- a/tests/modeprint/modeprint.c
+++ b/tests/modeprint/modeprint.c
@@ -113,7 +113,7 @@ static int printProperty(int fd, drmModeResPtr res, drmModePropertyPtr props, ui
} else {
for (j = 0; j < props->count_enums; j++) {
- printf("\t\t%" PRId64" = %s\n", (uint64_t)props->enums[j].value, props->enums[j].name);
+ printf("\t\t%" PRIu64" = %s\n", (uint64_t)props->enums[j].value, props->enums[j].name);
if (props->enums[j].value == value)
name = props->enums[j].name;
}
commit 4caec56fb8ebfe475a83315a12941d80808f4dee
Author: Eleni Maria Stea <ele...@gm...>
Date: Mon May 9 14:59:37 2022 +0300
modeprint, modetest, proptest: cast __u64 to uint64_t
It seems that __u64 values are defined differently across systems. In
glibc it's defined as unsigned long, in Linux kernel headers
(int-ll64.h) as unsigned long long, and on FreeBSD as uint64_t so it
matches glibc. A temporal solution is to cast all __u64 values to
uint64_t to avoid warnings on Linux, but ideally we'd like a better fix
in the future.
See also: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/212
for discussion.
Signed-off-by: Eleni Maria Stea <ele...@gm...>
diff --git a/tests/modeprint/modeprint.c b/tests/modeprint/modeprint.c
index f424f19d..880269b0 100644
--- a/tests/modeprint/modeprint.c
+++ b/tests/modeprint/modeprint.c
@@ -113,7 +113,7 @@ static int printProperty(int fd, drmModeResPtr res, drmModePropertyPtr props, ui
} else {
for (j = 0; j < props->count_enums; j++) {
- printf("\t\t%" PRId64 " = %s\n", props->enums[j].value, props->enums[j].name);
+ printf("\t\t%" PRId64" = %s\n", (uint64_t)props->enums[j].value, props->enums[j].name);
if (props->enums[j].value == value)
name = props->enums[j].name;
}
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index 5fd22f79..d6ab9dc8 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -376,7 +376,7 @@ static void dump_prop(struct device *dev, drmModePropertyPtr prop,
printf("\t\tenums:");
for (i = 0; i < prop->count_enums; i++)
printf(" %s=%"PRIu64, prop->enums[i].name,
- prop->enums[i].value);
+ (uint64_t)prop->enums[i].value);
printf("\n");
} else if (drm_property_type_is(prop, DRM_MODE_PROP_BITMASK)) {
printf("\t\tvalues:");
diff --git a/tests/proptest/proptest.c b/tests/proptest/proptest.c
index 0ab0907d..88bed10b 100644
--- a/tests/proptest/proptest.c
+++ b/tests/proptest/proptest.c
@@ -127,7 +127,7 @@ dump_prop(uint32_t prop_id, uint64_t value)
printf("\t\tenums:");
for (i = 0; i < prop->count_enums; i++)
printf(" %s=%"PRIu64, prop->enums[i].name,
- prop->enums[i].value);
+ (uint64_t)prop->enums[i].value);
printf("\n");
} else if (drm_property_type_is(prop, DRM_MODE_PROP_BITMASK)) {
printf("\t\tvalues:");
commit c907d4ade13a0ef883972f4bafdc94bc8c1f3573
Author: Eleni Maria Stea <ele...@gm...>
Date: Mon May 9 14:56:11 2022 +0300
xf86drm.c: fix C99 warning
Moved declaration to the top to resolve C99 compliance warning.
Signed-off-by: Eleni Maria Stea <ele...@gm...>
Reviewed-by: Simon Ser <co...@em...>
diff --git a/xf86drm.c b/xf86drm.c
index 5933e4bc..76fdfaab 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -261,6 +261,7 @@ drmGetAfbcFormatModifierNameFromArm(uint64_t modifier, FILE *fp)
static bool
drmGetAfrcFormatModifierNameFromArm(uint64_t modifier, FILE *fp)
{
+ bool scan_layout;
for (unsigned int i = 0; i < 2; ++i) {
uint64_t coding_unit_block =
(modifier >> (i * 4)) & AFRC_FORMAT_MOD_CU_SIZE_MASK;
@@ -292,7 +293,7 @@ drmGetAfrcFormatModifierNameFromArm(uint64_t modifier, FILE *fp)
}
}
- bool scan_layout =
+ scan_layout =
(modifier & AFRC_FORMAT_MOD_LAYOUT_SCAN) == AFRC_FORMAT_MOD_LAYOUT_SCAN;
if (scan_layout) {
fprintf(fp, "SCAN");
|
|
From: GitLab M. <git...@ke...> - 2022-07-20 22:26:41
|
include/drm/amdgpu_drm.h | 4
tests/amdgpu/vcn_tests.c | 383 +++++++++++++++++++++++++++++++++++++++--------
2 files changed, 325 insertions(+), 62 deletions(-)
New commits:
commit 6070e6a798a12eb13e4ea4a6f6dea6878b86c4f4
Author: Ruijing Dong <rui...@am...>
Date: Mon Jul 18 11:41:23 2022 -0400
tests/amdgpu/vcn: add unified queue support in vcn4
add unified queue headers on the existing tests.
Reviewed-by: Boyuan Zhang <Boy...@am...>
Signed-off-by: Ruijing Dong <rui...@am...>
diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index e094b455..5e20fb65 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -63,6 +63,7 @@
#define DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER (0x00100000)
static bool vcn_dec_sw_ring = false;
+static bool vcn_unified_ring = false;
#define H264_NAL_TYPE_NON_IDR_SLICE 1
#define H264_NAL_TYPE_DP_A_SLICE 2
@@ -172,6 +173,9 @@ static amdgpu_bo_handle ib_handle;
static amdgpu_va_handle ib_va_handle;
static uint64_t ib_mc_address;
static uint32_t *ib_cpu;
+static uint32_t *ib_checksum;
+static uint32_t *ib_size_in_dw;
+
static rvcn_decode_buffer_t *decode_buffer;
static amdgpu_bo_handle resources[MAX_RESOURCES];
@@ -185,8 +189,8 @@ static struct amdgpu_vcn_reg reg[] = {
};
uint32_t gWidth, gHeight, gSliceType;
-struct drm_amdgpu_info_hw_ip einfo;
-
+static uint32_t vcn_ip_version_major;
+static uint32_t vcn_ip_version_minor;
static void amdgpu_cs_vcn_dec_create(void);
static void amdgpu_cs_vcn_dec_decode(void);
static void amdgpu_cs_vcn_dec_destroy(void);
@@ -195,6 +199,8 @@ static void amdgpu_cs_vcn_enc_create(void);
static void amdgpu_cs_vcn_enc_encode(void);
static void amdgpu_cs_vcn_enc_destroy(void);
+static void amdgpu_cs_sq_head(uint32_t *base, int *offset, bool enc);
+static void amdgpu_cs_sq_ib_tail(uint32_t *end);
static void h264_check_0s (bufferInfo * bufInfo, int count);
static int32_t h264_se (bufferInfo * bufInfo);
static inline uint32_t bs_read_u1(bufferInfo *bufinfo);
@@ -224,7 +230,8 @@ CU_TestInfo vcn_tests[] = {
CU_BOOL suite_vcn_tests_enable(void)
{
struct drm_amdgpu_info_hw_ip info;
- int r, ret;
+ bool enc_ring, dec_ring;
+ int r;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
@@ -235,13 +242,31 @@ CU_BOOL suite_vcn_tests_enable(void)
chip_rev = device_handle->info.chip_rev;
chip_id = device_handle->info.chip_external_rev;
- r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_DEC, 0, &info);
- ret = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_ENC, 0, &einfo);
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_ENC, 0, &info);
+ if (!r) {
+ vcn_ip_version_major = info.hw_ip_version_major;
+ vcn_ip_version_minor = info.hw_ip_version_minor;
+ enc_ring = !!info.available_rings;
+ /* in vcn 4.0 it re-uses encoding queue as unified queue */
+ if (vcn_ip_version_major >= 4) {
+ vcn_unified_ring = true;
+ vcn_dec_sw_ring = true;
+ dec_ring = enc_ring;
+ } else {
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_DEC, 0, &info);
+ dec_ring = !!info.available_rings;
+ }
+ }
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
- if (r != 0 || !info.available_rings ||
+ if (r) {
+ printf("\n\nASIC query hw info failed\n");
+ return CU_FALSE;
+ }
+
+ if (!(dec_ring || enc_ring) ||
(family_id < AMDGPU_FAMILY_RV &&
(family_id == AMDGPU_FAMILY_AI &&
(chip_id - chip_rev) < 0x32))) { /* Arcturus */
@@ -249,22 +274,25 @@ CU_BOOL suite_vcn_tests_enable(void)
return CU_FALSE;
}
- if (family_id == AMDGPU_FAMILY_AI || (ret != 0) ||
- (!einfo.available_rings)) {
+ if (!dec_ring) {
+ amdgpu_set_test_active("VCN Tests", "VCN DEC create", CU_FALSE);
+ amdgpu_set_test_active("VCN Tests", "VCN DEC decode", CU_FALSE);
+ amdgpu_set_test_active("VCN Tests", "VCN DEC destroy", CU_FALSE);
+ }
+
+ if (family_id == AMDGPU_FAMILY_AI || !enc_ring) {
amdgpu_set_test_active("VCN Tests", "VCN ENC create", CU_FALSE);
amdgpu_set_test_active("VCN Tests", "VCN ENC encode", CU_FALSE);
amdgpu_set_test_active("VCN Tests", "VCN ENC destroy", CU_FALSE);
}
- if (info.hw_ip_version_major == 1)
+ if (vcn_ip_version_major == 1)
vcn_reg_index = 0;
- else if (info.hw_ip_version_major == 2 && info.hw_ip_version_minor == 0)
+ else if (vcn_ip_version_major == 2 && vcn_ip_version_minor == 0)
vcn_reg_index = 1;
- else if ((info.hw_ip_version_major == 2 && info.hw_ip_version_minor >= 5) ||
- info.hw_ip_version_major == 3)
+ else if ((vcn_ip_version_major == 2 && vcn_ip_version_minor >= 5) ||
+ vcn_ip_version_major == 3)
vcn_reg_index = 2;
- else
- vcn_dec_sw_ring = true;
return CU_TRUE;
}
@@ -314,6 +342,43 @@ int suite_vcn_tests_clean(void)
return CUE_SUCCESS;
}
+static void amdgpu_cs_sq_head(uint32_t *base, int *offset, bool enc)
+{
+ /* signature */
+ *(base + (*offset)++) = 0x00000010;
+ *(base + (*offset)++) = 0x30000002;
+ ib_checksum = base + (*offset)++;
+ ib_size_in_dw = base + (*offset)++;
+
+ /* engine info */
+ *(base + (*offset)++) = 0x00000010;
+ *(base + (*offset)++) = 0x30000001;
+ *(base + (*offset)++) = enc ? 2 : 3;
+ *(base + (*offset)++) = 0x00000000;
+}
+
+static void amdgpu_cs_sq_ib_tail(uint32_t *end)
+{
+ uint32_t size_in_dw;
+ uint32_t checksum = 0;
+
+ /* if the pointers are invalid, no need to process */
+ if (ib_checksum == NULL || ib_size_in_dw == NULL)
+ return;
+
+ size_in_dw = end - ib_size_in_dw - 1;
+ *ib_size_in_dw = size_in_dw;
+ *(ib_size_in_dw + 4) = size_in_dw * sizeof(uint32_t);
+
+ for (int i = 0; i < size_in_dw; i++)
+ checksum += *(ib_checksum + 2 + i);
+
+ *ib_checksum = checksum;
+
+ ib_checksum = NULL;
+ ib_size_in_dw = NULL;
+}
+
static int submit(unsigned ndw, unsigned ip)
{
struct amdgpu_cs_request ibs_request = {0};
@@ -419,10 +484,15 @@ static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
/* Support decode software ring message */
if (!(*idx)) {
- rvcn_decode_ib_package_t *ib_header = (rvcn_decode_ib_package_t *)ib_cpu;
+ rvcn_decode_ib_package_t *ib_header;
+ if (vcn_unified_ring)
+ amdgpu_cs_sq_head(ib_cpu, idx, false);
+
+ ib_header = (rvcn_decode_ib_package_t *)&ib_cpu[*idx];
ib_header->package_size = sizeof(struct rvcn_decode_buffer_s) +
sizeof(struct rvcn_decode_ib_package_s);
+
(*idx)++;
ib_header->package_type = (DECODE_IB_PARAM_DECODE_BUFFER);
(*idx)++;
@@ -486,6 +556,7 @@ static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
static void amdgpu_cs_vcn_dec_create(void)
{
struct amdgpu_vcn_bo msg_buf;
+ unsigned ip;
int len, r;
num_resources = 0;
@@ -500,9 +571,9 @@ static void amdgpu_cs_vcn_dec_create(void)
memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
len = 0;
- if (vcn_dec_sw_ring == true) {
+ if (vcn_dec_sw_ring == true)
vcn_dec_cmd(msg_buf.addr, 0, &len);
- } else {
+ else {
ib_cpu[len++] = reg[vcn_reg_index].data0;
ib_cpu[len++] = msg_buf.addr;
ib_cpu[len++] = reg[vcn_reg_index].data1;
@@ -515,7 +586,14 @@ static void amdgpu_cs_vcn_dec_create(void)
}
}
- r = submit(len, AMDGPU_HW_IP_VCN_DEC);
+ if (vcn_unified_ring) {
+ amdgpu_cs_sq_ib_tail(ib_cpu + len);
+ ip = AMDGPU_HW_IP_VCN_ENC;
+ } else
+ ip = AMDGPU_HW_IP_VCN_DEC;
+
+ r = submit(len, ip);
+
CU_ASSERT_EQUAL(r, 0);
free_resource(&msg_buf);
@@ -527,6 +605,7 @@ static void amdgpu_cs_vcn_dec_decode(void)
uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
struct amdgpu_vcn_bo dec_buf;
int size, len, i, r;
+ unsigned ip;
uint8_t *dec;
size = 4*1024; /* msg */
@@ -588,7 +667,13 @@ static void amdgpu_cs_vcn_dec_decode(void)
}
}
- r = submit(len, AMDGPU_HW_IP_VCN_DEC);
+ if (vcn_unified_ring) {
+ amdgpu_cs_sq_ib_tail(ib_cpu + len);
+ ip = AMDGPU_HW_IP_VCN_ENC;
+ } else
+ ip = AMDGPU_HW_IP_VCN_DEC;
+
+ r = submit(len, ip);
CU_ASSERT_EQUAL(r, 0);
for (i = 0, sum = 0; i < dt_size; ++i)
@@ -602,6 +687,7 @@ static void amdgpu_cs_vcn_dec_decode(void)
static void amdgpu_cs_vcn_dec_destroy(void)
{
struct amdgpu_vcn_bo msg_buf;
+ unsigned ip;
int len, r;
num_resources = 0;
@@ -616,9 +702,9 @@ static void amdgpu_cs_vcn_dec_destroy(void)
memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
len = 0;
- if (vcn_dec_sw_ring == true) {
+ if (vcn_dec_sw_ring == true)
vcn_dec_cmd(msg_buf.addr, 0, &len);
- } else {
+ else {
ib_cpu[len++] = reg[vcn_reg_index].data0;
ib_cpu[len++] = msg_buf.addr;
ib_cpu[len++] = reg[vcn_reg_index].data1;
@@ -631,7 +717,13 @@ static void amdgpu_cs_vcn_dec_destroy(void)
}
}
- r = submit(len, AMDGPU_HW_IP_VCN_DEC);
+ if (vcn_unified_ring) {
+ amdgpu_cs_sq_ib_tail(ib_cpu + len);
+ ip = AMDGPU_HW_IP_VCN_ENC;
+ } else
+ ip = AMDGPU_HW_IP_VCN_DEC;
+
+ r = submit(len, ip);
CU_ASSERT_EQUAL(r, 0);
free_resource(&msg_buf);
@@ -646,10 +738,10 @@ static void amdgpu_cs_vcn_enc_create(void)
unsigned width = 160, height = 128, buf_size;
uint32_t fw_maj = 1, fw_min = 9;
- if (einfo.hw_ip_version_major == 2) {
+ if (vcn_ip_version_major == 2) {
fw_maj = 1;
fw_min = 1;
- } else if (einfo.hw_ip_version_major == 3) {
+ } else if (vcn_ip_version_major == 3) {
fw_maj = 1;
fw_min = 0;
}
@@ -675,6 +767,10 @@ static void amdgpu_cs_vcn_enc_create(void)
r = amdgpu_bo_cpu_unmap(cpb_buf.handle);
len = 0;
+
+ if (vcn_unified_ring)
+ amdgpu_cs_sq_head(ib_cpu, &len, true);
+
/* session info */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
@@ -733,7 +829,7 @@ static void amdgpu_cs_vcn_enc_create(void)
ib_cpu[len++] = 1; /* quarter pel enabled */
ib_cpu[len++] = 100; /* BASELINE profile */
ib_cpu[len++] = 11; /* level */
- if (einfo.hw_ip_version_major == 3) {
+ if (vcn_ip_version_major == 3) {
ib_cpu[len++] = 0; /* b_picture_enabled */
ib_cpu[len++] = 0; /* weighted_bipred_idc */
}
@@ -774,7 +870,7 @@ static void amdgpu_cs_vcn_enc_create(void)
ib_cpu[len++] = 0; /* scene change sensitivity */
ib_cpu[len++] = 0; /* scene change min idr interval */
ib_cpu[len++] = 0;
- if (einfo.hw_ip_version_major == 3)
+ if (vcn_ip_version_major == 3)
ib_cpu[len++] = 0;
*st_size = (len - st_offset) * 4;
@@ -833,6 +929,9 @@ static void amdgpu_cs_vcn_enc_create(void)
*p_task_size = (len - task_offset) * 4;
+ if (vcn_unified_ring)
+ amdgpu_cs_sq_ib_tail(ib_cpu + len);
+
r = submit(len, AMDGPU_HW_IP_VCN_ENC);
CU_ASSERT_EQUAL(r, 0);
}
@@ -1176,10 +1275,10 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
uint32_t *st_size = NULL;
uint32_t fw_maj = 1, fw_min = 9;
- if (einfo.hw_ip_version_major == 2) {
+ if (vcn_ip_version_major == 2) {
fw_maj = 1;
fw_min = 1;
- } else if (einfo.hw_ip_version_major == 3) {
+ } else if (vcn_ip_version_major == 3) {
fw_maj = 1;
fw_min = 0;
}
@@ -1216,6 +1315,10 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
CU_ASSERT_EQUAL(r, 0);
len = 0;
+
+ if (vcn_unified_ring)
+ amdgpu_cs_sq_head(ib_cpu, &len, true);
+
/* session info */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
@@ -1240,7 +1343,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
/* sps */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
- if(einfo.hw_ip_version_major == 1)
+ if(vcn_ip_version_major == 1)
ib_cpu[len++] = 0x00000020; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1 */
else
ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 2,3 */
@@ -1256,7 +1359,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
/* pps */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
- if(einfo.hw_ip_version_major == 1)
+ if(vcn_ip_version_major == 1)
ib_cpu[len++] = 0x00000020; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1*/
else
ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 2,3*/
@@ -1270,7 +1373,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
/* slice header */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
- if(einfo.hw_ip_version_major == 1)
+ if(vcn_ip_version_major == 1)
ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_SLICE_HEADER vcn 1 */
else
ib_cpu[len++] = 0x0000000b; /* RENCODE_IB_PARAM_SLICE_HEADER vcn 2,3 */
@@ -1303,7 +1406,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
/* encode params */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
- if(einfo.hw_ip_version_major == 1)
+ if(vcn_ip_version_major == 1)
ib_cpu[len++] = 0x0000000b; /* RENCODE_IB_PARAM_ENCODE_PARAMS vcn 1*/
else
ib_cpu[len++] = 0x0000000f; /* RENCODE_IB_PARAM_ENCODE_PARAMS vcn 2,3*/
@@ -1324,7 +1427,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
ib_cpu[len++] = 0x00200003; /* RENCODE_H264_IB_PARAM_ENCODE_PARAMS */
- if (einfo.hw_ip_version_major != 3) {
+ if (vcn_ip_version_major != 3) {
ib_cpu[len++] = 0x00000000;
ib_cpu[len++] = 0x00000000;
ib_cpu[len++] = 0x00000000;
@@ -1353,7 +1456,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
/* encode context */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
- if(einfo.hw_ip_version_major == 1)
+ if(vcn_ip_version_major == 1)
ib_cpu[len++] = 0x0000000d; /* ENCODE_CONTEXT_BUFFER vcn 1 */
else
ib_cpu[len++] = 0x00000011; /* ENCODE_CONTEXT_BUFFER vcn 2,3 */
@@ -1375,7 +1478,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
/* bitstream buffer */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
- if(einfo.hw_ip_version_major == 1)
+ if(vcn_ip_version_major == 1)
ib_cpu[len++] = 0x0000000e; /* VIDEO_BITSTREAM_BUFFER vcn 1 */
else
ib_cpu[len++] = 0x00000012; /* VIDEO_BITSTREAM_BUFFER vcn 2,3 */
@@ -1389,7 +1492,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
/* feedback */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
- if(einfo.hw_ip_version_major == 1)
+ if(vcn_ip_version_major == 1)
ib_cpu[len++] = 0x00000010; /* FEEDBACK_BUFFER vcn 1 */
else
ib_cpu[len++] = 0x00000015; /* FEEDBACK_BUFFER vcn 2,3 */
@@ -1403,7 +1506,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
/* intra refresh */
st_offset = len;
st_size = &ib_cpu[len++];
- if(einfo.hw_ip_version_major == 1)
+ if(vcn_ip_version_major == 1)
ib_cpu[len++] = 0x0000000c; /* INTRA_REFRESH vcn 1 */
else
ib_cpu[len++] = 0x00000010; /* INTRA_REFRESH vcn 2,3 */
@@ -1412,7 +1515,7 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
ib_cpu[len++] = 0x00000000;
*st_size = (len - st_offset) * 4;
- if(einfo.hw_ip_version_major != 1) {
+ if(vcn_ip_version_major != 1) {
/* Input Format */
st_offset = len;
st_size = &ib_cpu[len++];
@@ -1449,6 +1552,10 @@ static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
*st_size = (len - st_offset) * 4;
*p_task_size = (len - task_offset) * 4;
+
+ if (vcn_unified_ring)
+ amdgpu_cs_sq_ib_tail(ib_cpu + len);
+
r = submit(len, AMDGPU_HW_IP_VCN_ENC);
CU_ASSERT_EQUAL(r, 0);
@@ -1473,10 +1580,10 @@ static void amdgpu_cs_vcn_enc_destroy(void)
uint32_t *st_size = NULL;
uint32_t fw_maj = 1, fw_min = 9;
- if (einfo.hw_ip_version_major == 2) {
+ if (vcn_ip_version_major == 2) {
fw_maj = 1;
fw_min = 1;
- } else if (einfo.hw_ip_version_major == 3) {
+ } else if (vcn_ip_version_major == 3) {
fw_maj = 1;
fw_min = 0;
}
@@ -1486,6 +1593,9 @@ static void amdgpu_cs_vcn_enc_destroy(void)
resources[num_resources++] = enc_buf.handle;
resources[num_resources++] = ib_handle;
+ if (vcn_unified_ring)
+ amdgpu_cs_sq_head(ib_cpu, &len, true);
+
/* session info */
st_offset = len;
st_size = &ib_cpu[len++]; /* size */
@@ -1514,6 +1624,9 @@ static void amdgpu_cs_vcn_enc_destroy(void)
*p_task_size = (len - task_offset) * 4;
+ if (vcn_unified_ring)
+ amdgpu_cs_sq_ib_tail(ib_cpu + len);
+
r = submit(len, AMDGPU_HW_IP_VCN_ENC);
CU_ASSERT_EQUAL(r, 0);
commit 8be30428641ea759bfbf660cc97eb138ced873f9
Author: Ruijing Dong <rui...@am...>
Date: Mon Jul 18 11:36:14 2022 -0400
tests/amdgpu/vcn: align comments for AMDGPU_HW_IP_VCN_ENC
From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support both encoding
and decoding jobs.
Reviewed-by: Boyuan Zhang <Boy...@am...>
Signed-off-by: Ruijing Dong <rui...@am...>
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 7f01f983..c0a0ad10 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -553,6 +553,10 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_HW_IP_VCE 4
#define AMDGPU_HW_IP_UVD_ENC 5
#define AMDGPU_HW_IP_VCN_DEC 6
+/*
+ * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support
+ * both encoding and decoding jobs.
+ */
#define AMDGPU_HW_IP_VCN_ENC 7
#define AMDGPU_HW_IP_VCN_JPEG 8
#define AMDGPU_HW_IP_NUM 9
commit e83aaae15eb201782cade233912c481e0807f82e
Author: James Zhu <Jam...@am...>
Date: Fri Mar 11 12:46:47 2022 -0500
tests/amdgpu: enable vcn swRing test for version 4 and later
Enable vcn decode software ring test for version 4 and later.
Signed-off-by: James Zhu <Jam...@am...>
Reviewed-by: Leo Liu <le...@am...>
Reviewed-by: Boyuan Zhang <Boy...@am...>
diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index add73ce5..e094b455 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -28,6 +28,7 @@
#include "CUnit/Basic.h"
+#include <unistd.h>
#include "util_math.h"
#include "amdgpu_test.h"
@@ -39,6 +40,30 @@
#define IB_SIZE 4096
#define MAX_RESOURCES 16
+#define DECODE_CMD_MSG_BUFFER 0x00000000
+#define DECODE_CMD_DPB_BUFFER 0x00000001
+#define DECODE_CMD_DECODING_TARGET_BUFFER 0x00000002
+#define DECODE_CMD_FEEDBACK_BUFFER 0x00000003
+#define DECODE_CMD_PROB_TBL_BUFFER 0x00000004
+#define DECODE_CMD_SESSION_CONTEXT_BUFFER 0x00000005
+#define DECODE_CMD_BITSTREAM_BUFFER 0x00000100
+#define DECODE_CMD_IT_SCALING_TABLE_BUFFER 0x00000204
+#define DECODE_CMD_CONTEXT_BUFFER 0x00000206
+
+#define DECODE_IB_PARAM_DECODE_BUFFER (0x00000001)
+
+#define DECODE_CMDBUF_FLAGS_MSG_BUFFER (0x00000001)
+#define DECODE_CMDBUF_FLAGS_DPB_BUFFER (0x00000002)
+#define DECODE_CMDBUF_FLAGS_BITSTREAM_BUFFER (0x00000004)
+#define DECODE_CMDBUF_FLAGS_DECODING_TARGET_BUFFER (0x00000008)
+#define DECODE_CMDBUF_FLAGS_FEEDBACK_BUFFER (0x00000010)
+#define DECODE_CMDBUF_FLAGS_IT_SCALING_BUFFER (0x00000200)
+#define DECODE_CMDBUF_FLAGS_CONTEXT_BUFFER (0x00000800)
+#define DECODE_CMDBUF_FLAGS_PROB_TBL_BUFFER (0x00001000)
+#define DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER (0x00100000)
+
+static bool vcn_dec_sw_ring = false;
+
#define H264_NAL_TYPE_NON_IDR_SLICE 1
#define H264_NAL_TYPE_DP_A_SLICE 2
#define H264_NAL_TYPE_DP_B_SLICE 3
@@ -63,6 +88,48 @@ struct amdgpu_vcn_bo {
uint8_t *ptr;
};
+typedef struct rvcn_decode_buffer_s {
+ unsigned int valid_buf_flag;
+ unsigned int msg_buffer_address_hi;
+ unsigned int msg_buffer_address_lo;
+ unsigned int dpb_buffer_address_hi;
+ unsigned int dpb_buffer_address_lo;
+ unsigned int target_buffer_address_hi;
+ unsigned int target_buffer_address_lo;
+ unsigned int session_contex_buffer_address_hi;
+ unsigned int session_contex_buffer_address_lo;
+ unsigned int bitstream_buffer_address_hi;
+ unsigned int bitstream_buffer_address_lo;
+ unsigned int context_buffer_address_hi;
+ unsigned int context_buffer_address_lo;
+ unsigned int feedback_buffer_address_hi;
+ unsigned int feedback_buffer_address_lo;
+ unsigned int luma_hist_buffer_address_hi;
+ unsigned int luma_hist_buffer_address_lo;
+ unsigned int prob_tbl_buffer_address_hi;
+ unsigned int prob_tbl_buffer_address_lo;
+ unsigned int sclr_coeff_buffer_address_hi;
+ unsigned int sclr_coeff_buffer_address_lo;
+ unsigned int it_sclr_table_buffer_address_hi;
+ unsigned int it_sclr_table_buffer_address_lo;
+ unsigned int sclr_target_buffer_address_hi;
+ unsigned int sclr_target_buffer_address_lo;
+ unsigned int cenc_size_info_buffer_address_hi;
+ unsigned int cenc_size_info_buffer_address_lo;
+ unsigned int mpeg2_pic_param_buffer_address_hi;
+ unsigned int mpeg2_pic_param_buffer_address_lo;
+ unsigned int mpeg2_mb_control_buffer_address_hi;
+ unsigned int mpeg2_mb_control_buffer_address_lo;
+ unsigned int mpeg2_idct_coeff_buffer_address_hi;
+ unsigned int mpeg2_idct_coeff_buffer_address_lo;
+} rvcn_decode_buffer_t;
+
+typedef struct rvcn_decode_ib_package_s {
+ unsigned int package_size;
+ unsigned int package_type;
+} rvcn_decode_ib_package_t;
+
+
struct amdgpu_vcn_reg {
uint32_t data0;
uint32_t data1;
@@ -105,6 +172,7 @@ static amdgpu_bo_handle ib_handle;
static amdgpu_va_handle ib_va_handle;
static uint64_t ib_mc_address;
static uint32_t *ib_cpu;
+static rvcn_decode_buffer_t *decode_buffer;
static amdgpu_bo_handle resources[MAX_RESOURCES];
static unsigned num_resources;
@@ -196,7 +264,7 @@ CU_BOOL suite_vcn_tests_enable(void)
info.hw_ip_version_major == 3)
vcn_reg_index = 2;
else
- return CU_FALSE;
+ vcn_dec_sw_ring = true;
return CU_TRUE;
}
@@ -339,12 +407,80 @@ static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
{
- ib_cpu[(*idx)++] = reg[vcn_reg_index].data0;
- ib_cpu[(*idx)++] = addr;
- ib_cpu[(*idx)++] = reg[vcn_reg_index].data1;
- ib_cpu[(*idx)++] = addr >> 32;
- ib_cpu[(*idx)++] = reg[vcn_reg_index].cmd;
- ib_cpu[(*idx)++] = cmd << 1;
+ if (vcn_dec_sw_ring == false) {
+ ib_cpu[(*idx)++] = reg[vcn_reg_index].data0;
+ ib_cpu[(*idx)++] = addr;
+ ib_cpu[(*idx)++] = reg[vcn_reg_index].data1;
+ ib_cpu[(*idx)++] = addr >> 32;
+ ib_cpu[(*idx)++] = reg[vcn_reg_index].cmd;
+ ib_cpu[(*idx)++] = cmd << 1;
+ return;
+ }
+
+ /* Support decode software ring message */
+ if (!(*idx)) {
+ rvcn_decode_ib_package_t *ib_header = (rvcn_decode_ib_package_t *)ib_cpu;
+
+ ib_header->package_size = sizeof(struct rvcn_decode_buffer_s) +
+ sizeof(struct rvcn_decode_ib_package_s);
+ (*idx)++;
+ ib_header->package_type = (DECODE_IB_PARAM_DECODE_BUFFER);
+ (*idx)++;
+
+ decode_buffer = (rvcn_decode_buffer_t *)&(ib_cpu[*idx]);
+ *idx += sizeof(struct rvcn_decode_buffer_s) / 4;
+ memset(decode_buffer, 0, sizeof(struct rvcn_decode_buffer_s));
+ }
+
+ switch(cmd) {
+ case DECODE_CMD_MSG_BUFFER:
+ decode_buffer->valid_buf_flag |= DECODE_CMDBUF_FLAGS_MSG_BUFFER;
+ decode_buffer->msg_buffer_address_hi = (addr >> 32);
+ decode_buffer->msg_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_DPB_BUFFER:
+ decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_DPB_BUFFER);
+ decode_buffer->dpb_buffer_address_hi = (addr >> 32);
+ decode_buffer->dpb_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_DECODING_TARGET_BUFFER:
+ decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_DECODING_TARGET_BUFFER);
+ decode_buffer->target_buffer_address_hi = (addr >> 32);
+ decode_buffer->target_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_FEEDBACK_BUFFER:
+ decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_FEEDBACK_BUFFER);
+ decode_buffer->feedback_buffer_address_hi = (addr >> 32);
+ decode_buffer->feedback_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_PROB_TBL_BUFFER:
+ decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_PROB_TBL_BUFFER);
+ decode_buffer->prob_tbl_buffer_address_hi = (addr >> 32);
+ decode_buffer->prob_tbl_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_SESSION_CONTEXT_BUFFER:
+ decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER);
+ decode_buffer->session_contex_buffer_address_hi = (addr >> 32);
+ decode_buffer->session_contex_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_BITSTREAM_BUFFER:
+ decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_BITSTREAM_BUFFER);
+ decode_buffer->bitstream_buffer_address_hi = (addr >> 32);
+ decode_buffer->bitstream_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_IT_SCALING_TABLE_BUFFER:
+ decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_IT_SCALING_BUFFER);
+ decode_buffer->it_sclr_table_buffer_address_hi = (addr >> 32);
+ decode_buffer->it_sclr_table_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_CONTEXT_BUFFER:
+ decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_CONTEXT_BUFFER);
+ decode_buffer->context_buffer_address_hi = (addr >> 32);
+ decode_buffer->context_buffer_address_lo = (addr);
+ break;
+ default:
+ printf("Not Support!\n");
+ }
}
static void amdgpu_cs_vcn_dec_create(void)
@@ -364,15 +500,19 @@ static void amdgpu_cs_vcn_dec_create(void)
memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
len = 0;
- ib_cpu[len++] = reg[vcn_reg_index].data0;
- ib_cpu[len++] = msg_buf.addr;
- ib_cpu[len++] = reg[vcn_reg_index].data1;
- ib_cpu[len++] = msg_buf.addr >> 32;
- ib_cpu[len++] = reg[vcn_reg_index].cmd;
- ib_cpu[len++] = 0;
- for (; len % 16; ) {
- ib_cpu[len++] = reg[vcn_reg_index].nop;
+ if (vcn_dec_sw_ring == true) {
+ vcn_dec_cmd(msg_buf.addr, 0, &len);
+ } else {
+ ib_cpu[len++] = reg[vcn_reg_index].data0;
+ ib_cpu[len++] = msg_buf.addr;
+ ib_cpu[len++] = reg[vcn_reg_index].data1;
+ ib_cpu[len++] = msg_buf.addr >> 32;
+ ib_cpu[len++] = reg[vcn_reg_index].cmd;
ib_cpu[len++] = 0;
+ for (; len % 16; ) {
+ ib_cpu[len++] = reg[vcn_reg_index].nop;
+ ib_cpu[len++] = 0;
+ }
}
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
@@ -439,11 +579,13 @@ static void amdgpu_cs_vcn_dec_decode(void)
vcn_dec_cmd(it_addr, 0x204, &len);
vcn_dec_cmd(ctx_addr, 0x206, &len);
- ib_cpu[len++] = reg[vcn_reg_index].cntl;
- ib_cpu[len++] = 0x1;
- for (; len % 16; ) {
- ib_cpu[len++] = reg[vcn_reg_index].nop;
- ib_cpu[len++] = 0;
+ if (vcn_dec_sw_ring == false) {
+ ib_cpu[len++] = reg[vcn_reg_index].cntl;
+ ib_cpu[len++] = 0x1;
+ for (; len % 16; ) {
+ ib_cpu[len++] = reg[vcn_reg_index].nop;
+ ib_cpu[len++] = 0;
+ }
}
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
@@ -474,15 +616,19 @@ static void amdgpu_cs_vcn_dec_destroy(void)
memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
len = 0;
- ib_cpu[len++] = reg[vcn_reg_index].data0;
- ib_cpu[len++] = msg_buf.addr;
- ib_cpu[len++] = reg[vcn_reg_index].data1;
- ib_cpu[len++] = msg_buf.addr >> 32;
- ib_cpu[len++] = reg[vcn_reg_index].cmd;
- ib_cpu[len++] = 0;
- for (; len % 16; ) {
- ib_cpu[len++] = reg[vcn_reg_index].nop;
+ if (vcn_dec_sw_ring == true) {
+ vcn_dec_cmd(msg_buf.addr, 0, &len);
+ } else {
+ ib_cpu[len++] = reg[vcn_reg_index].data0;
+ ib_cpu[len++] = msg_buf.addr;
+ ib_cpu[len++] = reg[vcn_reg_index].data1;
+ ib_cpu[len++] = msg_buf.addr >> 32;
+ ib_cpu[len++] = reg[vcn_reg_index].cmd;
ib_cpu[len++] = 0;
+ for (; len % 16; ) {
+ ib_cpu[len++] = reg[vcn_reg_index].nop;
+ ib_cpu[len++] = 0;
+ }
}
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
|
|
From: GitLab M. <git...@ke...> - 2023-03-24 13:49:26
|
tests/amdgpu/amdgpu_test.c | 207 +++++++++++++++++++++++++++++++++++----------
1 file changed, 163 insertions(+), 44 deletions(-)
New commits:
commit 28d9a3c4fb4c99aafc31b288b3f735e19e728d64
Author: Luben Tuikov <lub...@am...>
Date: Tue Mar 21 08:51:50 2023 -0400
tests/amdgpu: Allow to exclude a test or a suite of tests
Add the command line argument -e s[.t] to exclude (disable) suite s, or to
exclude suite s test t.
This is useful for instance to run the Basic Suite, but disable the GPU reset
test, on the command line, like this:
amdgpu_tests -s 1 -e 1.13
This option can be specified more than once on the command line, in order to
exclude more than one suite and/or suite and test combination from being run.
Cc: Alex Deucher <Ale...@am...>
Signed-off-by: Luben Tuikov <lub...@am...>
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 59ca49bd..ec787889 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -296,11 +296,14 @@ static void display_test_suites(void)
/** Help string for command line parameters */
static const char usage[] =
- "Usage: %s [-hlpr] [-s <suite id>] [-t <test id>] [-f] "
+ "Usage: %s [-hlpr] [-s <suite id>] [-e <s>[.<t>] [-e ...]] [-t <test id>] [-f] "
"[-b <pci_bus_id>] [-d <pci_device_id>]\n"
"Where,\n"
" -b Specify device's PCI bus id to run tests\n"
" -d Specify device's PCI device id to run tests (optional)\n"
+ " -e <s>[.<t>] Disable test <t> of suite <s>. If only <s> is given, then disable\n"
+ " the whole suite. Can be specified more than once on the command line\n"
+ " to disable multiple tests or suites.\n"
" -f Force executing inactive suite or test\n"
" -h Display this help\n"
" -l Display all test suites and their tests\n"
@@ -309,7 +312,7 @@ static const char usage[] =
" -s <s> Enable only test suite <s>\n"
" -t <t> Enable only test <t> of test suite <s>\n";
/** Specified options strings for getopt */
-static const char options[] = "hlrps:t:b:d:f";
+static const char options[] = "hlrps:t:e:b:d:f";
/* Open AMD devices.
* Return the number of AMD device opened.
@@ -664,6 +667,48 @@ char *amdgpu_get_device_from_fd(int fd)
#endif
}
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(_A) (sizeof(_A)/sizeof(_A[0]))
+#endif
+
+static void amdgpu_test_disable(long suite, long test)
+{
+ const char *suite_name;
+
+ if (suite < 1)
+ return;
+
+ /* The array is 0-based, so subract 1. */
+ suite--;
+ if (suite >= ARRAY_SIZE(suites) - 1)
+ return;
+
+ suite_name = suites[suite].pName;
+ if (test < 1) {
+ fprintf(stderr, "Deactivating suite %s\n", suite_name);
+ amdgpu_set_suite_active(suite_name, CU_FALSE);
+ } else {
+ int ii;
+
+ /* The array is 0-based so subtract 1. */
+ test--;
+ for (ii = 0; suites[suite].pTests[ii].pName; ii++) {
+ if (ii == test) {
+ fprintf(stderr, "Deactivating %s:%s\n",
+ suite_name,
+ suites[suite].pTests[ii].pName);
+ amdgpu_set_test_active(suite_name,
+ suites[suite].pTests[ii].pName,
+ CU_FALSE);
+ break;
+ }
+ }
+
+ if (suites[suite].pTests[ii].pName == NULL)
+ fprintf(stderr, "No such suite.test %ld.%ld\n", suite, test);
+ }
+}
+
/* The main() function for setting up and running the tests.
* Returns a CUE_SUCCESS on successful running, another
* CUnit error code on failure.
@@ -682,48 +727,21 @@ int main(int argc, char **argv)
int display_list = 0;
int force_run = 0;
- for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
- drm_amdgpu[i] = -1;
-
-
- /* Parse command line string */
+ /* Parse command line string.
+ * Process various command line options as early as possible.
+ */
opterr = 0; /* Do not print error messages from getopt */
while ((c = getopt(argc, argv, options)) != -1) {
switch (c) {
- case 'l':
- display_list = 1;
- break;
- case 's':
- suite_id = atoi(optarg);
- break;
- case 't':
- test_id = atoi(optarg);
- break;
- case 'b':
- pci_bus_id = atoi(optarg);
- break;
- case 'd':
- sscanf(optarg, "%x", &pci_device_id);
- break;
- case 'p':
- display_devices = 1;
- break;
- case 'r':
- open_render_node = 1;
- break;
- case 'f':
- force_run = 1;
- break;
- case '?':
case 'h':
fprintf(stderr, usage, argv[0]);
exit(EXIT_SUCCESS);
- default:
- fprintf(stderr, usage, argv[0]);
- exit(EXIT_FAILURE);
}
}
+ for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
+ drm_amdgpu[i] = -1;
+
if (amdgpu_open_devices(open_render_node) <= 0) {
perror("Cannot open AMDGPU device");
exit(EXIT_FAILURE);
@@ -734,12 +752,37 @@ int main(int argc, char **argv)
exit(EXIT_FAILURE);
}
+ /* Parse command line string */
+ opterr = 0; /* Do not print error messages from getopt */
+ optind = 1;
+ while ((c = getopt(argc, argv, options)) != -1) {
+ switch (c) {
+ case 'p':
+ display_devices = 1;
+ break;
+ }
+ }
+
if (display_devices) {
amdgpu_print_devices();
amdgpu_close_devices();
exit(EXIT_SUCCESS);
}
+ /* Parse command line string */
+ opterr = 0; /* Do not print error messages from getopt */
+ optind = 1;
+ while ((c = getopt(argc, argv, options)) != -1) {
+ switch (c) {
+ case 'b':
+ pci_bus_id = atoi(optarg);
+ break;
+ case 'd':
+ sscanf(optarg, "%x", &pci_device_id);
+ break;
+ }
+ }
+
if (pci_bus_id > 0 || pci_device_id) {
/* A device was specified to run the test */
test_device_index = amdgpu_find_device(pci_bus_id,
@@ -782,11 +825,85 @@ int main(int argc, char **argv)
/* Disable suites and individual tests based on misc. conditions */
amdgpu_disable_suites();
+ /* Parse command line string */
+ opterr = 0; /* Do not print error messages from getopt */
+ optind = 1;
+ while ((c = getopt(argc, argv, options)) != -1) {
+ switch (c) {
+ case 'l':
+ display_list = 1;
+ break;
+ }
+ }
+
if (display_list) {
display_test_suites();
goto end;
}
+ /* Parse command line string */
+ opterr = 0; /* Do not print error messages from getopt */
+ optind = 1;
+ while ((c = getopt(argc, argv, options)) != -1) {
+ long esuite = -1;
+ long etest = -1;
+ char *endp;
+ switch (c) {
+ case 's':
+ suite_id = atoi(optarg);
+ break;
+ case 't':
+ test_id = atoi(optarg);
+ break;
+ case 'r':
+ open_render_node = 1;
+ break;
+ case 'f':
+ force_run = 1;
+ break;
+ case 'e':
+ esuite = strtol(optarg, &endp, 0);
+ if (endp == optarg) {
+ fprintf(stderr, "No digits given for -e argument\n");
+ goto end;
+ } else if (endp && *endp == '.' && esuite > 0) {
+ char *tt = endp + 1;
+ etest = strtol(tt, &endp, 0);
+ if (endp == tt) {
+ fprintf(stderr, "No digits given for test in -e s.t argument\n");
+ goto end;
+ } else if (endp && *endp != '\0') {
+ fprintf(stderr, "Bad input given for test in -e s.t argument\n");
+ goto end;
+ } else if (etest < 1) {
+ fprintf(stderr, "Test in -e s.t argument cannot be smaller than 1\n");
+ goto end;
+ }
+ } else if (endp && *endp != '\0') {
+ fprintf(stderr, "Bad input given for suite for -e s argument\n");
+ goto end;
+ } else if (esuite < 1) {
+ fprintf(stderr, "Suite in -e s argument cannot be smaller than 1\n");
+ goto end;
+ }
+ amdgpu_test_disable(esuite, etest);
+ break;
+ case 'h':
+ case 'p':
+ case 'b':
+ case 'd':
+ case 'l':
+ /* Those have been processed earlier.
+ */
+ break;
+ case '?':
+ default:
+ fprintf(stderr, "Unknown command line option '%c'. Try -h.\n",
+ c == '?' ? optopt : c);
+ goto end;
+ }
+ }
+
if (suite_id != -1) { /* If user specify particular suite? */
pSuite = CU_get_suite_by_index((unsigned int) suite_id,
CU_get_registry());
commit 41121251de435e621a10627d4bbe08c436b32b4b
Author: Luben Tuikov <lub...@am...>
Date: Thu Mar 16 18:17:18 2023 -0400
tests/amdgpu: Add all 9 options to the help output
Add -s and -t to the help output, as well as sort
the options output alphabetically.
v1: Fix a spelling in the subject of this commit.
Cc: Alex Deucher <Ale...@am...>
Signed-off-by: Luben Tuikov <lub...@am...>
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index b8fd638c..59ca49bd 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -298,14 +298,16 @@ static void display_test_suites(void)
static const char usage[] =
"Usage: %s [-hlpr] [-s <suite id>] [-t <test id>] [-f] "
"[-b <pci_bus_id>] [-d <pci_device_id>]\n"
- "where:\n"
- " l - Display all suites and their tests\n"
- " r - Run the tests on render node\n"
- " b - Specify device's PCI bus id to run tests\n"
- " d - Specify device's PCI device id to run tests (optional)\n"
- " p - Display information of AMDGPU devices in system\n"
- " f - Force executing inactive suite or test\n"
- " h - Display this help\n";
+ "Where,\n"
+ " -b Specify device's PCI bus id to run tests\n"
+ " -d Specify device's PCI device id to run tests (optional)\n"
+ " -f Force executing inactive suite or test\n"
+ " -h Display this help\n"
+ " -l Display all test suites and their tests\n"
+ " -p Display information of AMDGPU devices in system\n"
+ " -r Run the tests on render node\n"
+ " -s <s> Enable only test suite <s>\n"
+ " -t <t> Enable only test <t> of test suite <s>\n";
/** Specified options strings for getopt */
static const char options[] = "hlrps:t:b:d:f";
commit 25e08fd9ae83d8362573e95fa7eead28846e501f
Author: Luben Tuikov <lub...@am...>
Date: Thu Mar 16 15:09:14 2023 -0400
tests/amdgpu: Fix Usage string
Fix the Usage: string on -h (help) in amdgpu_tests.c,
so brackets match, and remove mismatched angle brackets.
Cc: Alex Deucher <Ale...@am...>
Signed-off-by: Luben Tuikov <lub...@am...>
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 9abe5730..b8fd638c 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -296,8 +296,8 @@ static void display_test_suites(void)
/** Help string for command line parameters */
static const char usage[] =
- "Usage: %s [-hlpr] [<-s <suite id>> [-t <test id>] [-f]] "
- "[-b <pci_bus_id> [-d <pci_device_id>]]\n"
+ "Usage: %s [-hlpr] [-s <suite id>] [-t <test id>] [-f] "
+ "[-b <pci_bus_id>] [-d <pci_device_id>]\n"
"where:\n"
" l - Display all suites and their tests\n"
" r - Run the tests on render node\n"
|
|
From: GitLab M. <git...@ke...> - 2023-09-08 17:45:34
|
tests/modetest/buffers.c | 20 ++++++++++++++++++++
tests/util/format.c | 2 ++
tests/util/pattern.c | 4 ++++
3 files changed, 26 insertions(+)
New commits:
commit be42051eadc53c55ca1920a7bfedb9ad867838dc
Author: Geert Uytterhoeven <gee...@gl...>
Date: Wed Jul 5 15:24:02 2023 +0200
modetest: add support for DRM_FORMAT_NV{24,42}
Add support for creating buffers using semi-planar YUV formats with
non-subsampled chroma planes.
Signed-off-by: Geert Uytterhoeven <gee...@gl...>
Reviewed-by: Laurent Pinchart <lau...@id...>
---
v2:
- Add Reviewed-by.
diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c
index 4119f048..c122fb3f 100644
--- a/tests/modetest/buffers.c
+++ b/tests/modetest/buffers.c
@@ -129,6 +129,8 @@ bo_create(int fd, unsigned int format,
case DRM_FORMAT_NV21:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV61:
+ case DRM_FORMAT_NV24:
+ case DRM_FORMAT_NV42:
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
bpp = 8;
@@ -208,6 +210,11 @@ bo_create(int fd, unsigned int format,
virtual_height = height * 2;
break;
+ case DRM_FORMAT_NV24:
+ case DRM_FORMAT_NV42:
+ virtual_height = height * 3;
+ break;
+
default:
virtual_height = height;
break;
@@ -255,6 +262,19 @@ bo_create(int fd, unsigned int format,
planes[1] = virtual + offsets[1];
break;
+ case DRM_FORMAT_NV24:
+ case DRM_FORMAT_NV42:
+ offsets[0] = 0;
+ handles[0] = bo->handle;
+ pitches[0] = bo->pitch;
+ pitches[1] = pitches[0] * 2;
+ offsets[1] = pitches[0] * height;
+ handles[1] = bo->handle;
+
+ planes[0] = virtual;
+ planes[1] = virtual + offsets[1];
+ break;
+
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
offsets[0] = 0;
commit 8e5286d4f982b7dd372a8747d5cf55438e74d02d
Author: Geert Uytterhoeven <gee...@gl...>
Date: Wed Jul 5 15:23:56 2023 +0200
util: add pattern support for DRM_FORMAT_NV{24,42}
Add support for drawing the SMPTE and tiles patterns in buffers using
semi-planar YUV formats with non-subsampled chroma planes.
Signed-off-by: Geert Uytterhoeven <gee...@gl...>
Reviewed-by: Laurent Pinchart <lau...@id...>
---
v2:
- Add Reviewed-by.
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index 158c0b16..f45a26cc 100644
--- a/tests/util/pattern.c
+++ b/tests/util/pattern.c
@@ -698,6 +698,8 @@ static void fill_smpte(const struct util_format_info *info, void *planes[3],
case DRM_FORMAT_NV21:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV61:
+ case DRM_FORMAT_NV24:
+ case DRM_FORMAT_NV42:
u = info->yuv.order & YUV_YCbCr ? planes[1] : planes[1] + 1;
v = info->yuv.order & YUV_YCrCb ? planes[1] : planes[1] + 1;
return fill_smpte_yuv_planar(&info->yuv, planes[0], u, v,
@@ -1023,6 +1025,8 @@ static void fill_tiles(const struct util_format_info *info, void *planes[3],
case DRM_FORMAT_NV21:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV61:
+ case DRM_FORMAT_NV24:
+ case DRM_FORMAT_NV42:
u = info->yuv.order & YUV_YCbCr ? planes[1] : planes[1] + 1;
v = info->yuv.order & YUV_YCrCb ? planes[1] : planes[1] + 1;
return fill_tiles_yuv_planar(info, planes[0], u, v,
commit cd3b248cdceacad1ad5cdf146ad8c95fbdd66240
Author: Geert Uytterhoeven <gee...@gl...>
Date: Wed Jul 5 15:23:52 2023 +0200
util: add NV24 and NV42 frame buffer formats
Add the missing entries for semi-planar YUV formats with
non-subsampled chroma planes.
Signed-off-by: Geert Uytterhoeven <gee...@gl...>
Reviewed-by: Laurent Pinchart <lau...@id...>
---
v2:
- Add Reviewed-by.
diff --git a/tests/util/format.c b/tests/util/format.c
index 1ca1b82c..f8250272 100644
--- a/tests/util/format.c
+++ b/tests/util/format.c
@@ -51,6 +51,8 @@ static const struct util_format_info format_info[] = {
{ DRM_FORMAT_NV21, "NV21", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 2) },
{ DRM_FORMAT_NV16, "NV16", MAKE_YUV_INFO(YUV_YCbCr, 2, 1, 2) },
{ DRM_FORMAT_NV61, "NV61", MAKE_YUV_INFO(YUV_YCrCb, 2, 1, 2) },
+ { DRM_FORMAT_NV24, "NV24", MAKE_YUV_INFO(YUV_YCbCr, 1, 1, 2) },
+ { DRM_FORMAT_NV42, "NV42", MAKE_YUV_INFO(YUV_YCrCb, 1, 1, 2) },
/* YUV planar */
{ DRM_FORMAT_YUV420, "YU12", MAKE_YUV_INFO(YUV_YCbCr, 2, 2, 1) },
{ DRM_FORMAT_YVU420, "YV12", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 1) },
|
|
From: GitLab M. <git...@ke...> - 2023-09-08 18:13:48
|
tests/modetest/modetest.c | 15 +++++++++++++--
tests/util/pattern.c | 9 ++-------
2 files changed, 15 insertions(+), 9 deletions(-)
New commits:
commit 4d3635fada9462a817f5d252b10349affde8e6f7
Author: Geert Uytterhoeven <ge...@li...>
Date: Thu Jun 30 16:35:31 2022 +0200
util: remove unused definitions of RED, GREEN, and BLUE
These are unused since commit edcef53685edf5fb ("modetest: Add test
pattern support for missing RGB formats").
Signed-off-by: Geert Uytterhoeven <ge...@li...>
Reviewed-by: Laurent Pinchart <lau...@id...>
---
v2:
- Add Reviewed-by.
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index cf5c8e21..bd0989e6 100644
--- a/tests/util/pattern.c
+++ b/tests/util/pattern.c
@@ -766,11 +766,6 @@ static void fill_smpte(const struct util_format_info *info, void *planes[3],
}
}
-/* swap these for big endian.. */
-#define RED 2
-#define GREEN 1
-#define BLUE 0
-
static void make_pwetty(void *data, unsigned int width, unsigned int height,
unsigned int stride, uint32_t format)
{
commit ea5237e549257c47b0edeb445bd63e089f278c0b
Author: Geert Uytterhoeven <ge...@li...>
Date: Thu Jun 30 14:41:48 2022 +0200
modetest: fix mode_vrefresh() for interlace/dblscan/vscan
mode_vrefresh() does not take into account interlaced, doublescan, and
multiscan modes, leading to incorrect refresh rates.
Fix this, based on drm_mode_vrefresh() in Linux.
Signed-off-by: Geert Uytterhoeven <ge...@li...>
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index e714818e..4e00bed9 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -138,8 +138,19 @@ static inline int64_t U642I64(uint64_t val)
static float mode_vrefresh(drmModeModeInfo *mode)
{
- return mode->clock * 1000.00
- / (mode->htotal * mode->vtotal);
+ unsigned int num, den;
+
+ num = mode->clock;
+ den = mode->htotal * mode->vtotal;
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ num *= 2;
+ if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ den *= 2;
+ if (mode->vscan > 1)
+ den *= mode->vscan;
+
+ return num * 1000.00 / den;
}
#define bit_name_fn(res) \
commit 022a4d8a82f8d621cfa0eccec92446b289a23e28
Author: Geert Uytterhoeven <ge...@li...>
Date: Sun Jul 3 14:05:31 2022 +0200
util: fix grey in YUV SMPTE patterns
The YUV SMPTE patterns use RGB 191/192/192 instead of 192/192/192 for
the grey color in the top color bar.
Change it to 192/192/192, to match the RGB SMPTE patterns.
Fixes: a94ee624292bff96 ("modetest: Add SMPTE test pattern")
Signed-off-by: Geert Uytterhoeven <ge...@li...>
Reviewed-by: Laurent Pinchart <lau...@id...>
---
v2:
- Add Reviewed-by.
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index f45a26cc..cf5c8e21 100644
--- a/tests/util/pattern.c
+++ b/tests/util/pattern.c
@@ -162,7 +162,7 @@ static void fill_smpte_yuv_planar(const struct util_yuv_info *yuv,
unsigned int height, unsigned int stride)
{
const struct color_yuv colors_top[] = {
- MAKE_YUV_601(191, 192, 192), /* grey */
+ MAKE_YUV_601(192, 192, 192), /* grey */
MAKE_YUV_601(192, 192, 0), /* yellow */
MAKE_YUV_601(0, 192, 192), /* cyan */
MAKE_YUV_601(0, 192, 0), /* green */
@@ -265,7 +265,7 @@ static void fill_smpte_yuv_packed(const struct util_yuv_info *yuv, void *mem,
unsigned int stride)
{
const struct color_yuv colors_top[] = {
- MAKE_YUV_601(191, 192, 192), /* grey */
+ MAKE_YUV_601(192, 192, 192), /* grey */
MAKE_YUV_601(192, 192, 0), /* yellow */
MAKE_YUV_601(0, 192, 192), /* cyan */
MAKE_YUV_601(0, 192, 0), /* green */
|
|
From: GitLab M. <git...@ke...> - 2023-10-20 05:23:44
|
.gitlab-ci.yml | 4 -
amdgpu/meson.build | 2
meson.build | 118 +++++++++++++++-------------------------------------
nouveau/meson.build | 2
radeon/meson.build | 2
5 files changed, 40 insertions(+), 88 deletions(-)
New commits:
commit bd205d133e42069ac60013854e75a35f9fb54424
Author: Dylan Baker <dy...@pn...>
Date: Fri Sep 1 13:10:41 2023 -0700
meson: replace deprecated program.path -> program.full_path
To avoid Meson warnings
Signed-off-by: Dylan Baker <dyl...@in...>
Reviewed-by: Simon Ser <co...@em...>
diff --git a/amdgpu/meson.build b/amdgpu/meson.build
index 20bf6244..679de94d 100644
--- a/amdgpu/meson.build
+++ b/amdgpu/meson.build
@@ -65,6 +65,6 @@ test(
args : [
'--lib', libdrm_amdgpu,
'--symbols-file', files('amdgpu-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
diff --git a/meson.build b/meson.build
index f883760e..9f6946ae 100644
--- a/meson.build
+++ b/meson.build
@@ -266,7 +266,7 @@ test(
args : [
'--lib', libdrm,
'--symbols-file', files('core-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
diff --git a/nouveau/meson.build b/nouveau/meson.build
index 350f34c4..71c8f552 100644
--- a/nouveau/meson.build
+++ b/nouveau/meson.build
@@ -60,6 +60,6 @@ test(
args : [
'--lib', libdrm_nouveau,
'--symbols-file', files('nouveau-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
diff --git a/radeon/meson.build b/radeon/meson.build
index dda3877a..7aa9b705 100644
--- a/radeon/meson.build
+++ b/radeon/meson.build
@@ -65,6 +65,6 @@ test(
args : [
'--lib', libdrm_radeon,
'--symbols-file', files('radeon-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
commit 16e6a965051fae4d5142e9f16c47bb6bd3dd6f59
Author: Dylan Baker <dy...@pn...>
Date: Fri Sep 1 12:23:35 2023 -0700
meson: Use feature.require() and feature.allowed()
To reduce the size and complexity of checks. require() allows combining
auto and enabled checks(), so that something like
```meson
x = get_option('feature')
y = false
if x.enabled()
if not condition
error(...)
endif
y = condition
endif
```
can be rewritten as:
```meson
y = get_option('feature').require(condition, error_message : ...).allowed()
```
require checks the condition, then if the feature is required it emits
an error with the given message otherwise it returns a disabled feature.
allowed then returns whether the feature is not disabled, and returns
that (ie, .allowed() == not .disabled()). This is especially helpful for
longer more complex conditions
Signed-off-by: Dylan Baker <dyl...@in...>
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index b59d68ea..6e8655fa 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -41,10 +41,10 @@ stages:
BUILD_OS: debian
FDO_DISTRIBUTION_VERSION: buster
FDO_DISTRIBUTION_PACKAGES: 'build-essential docbook-xsl libatomic-ops-dev libcairo2-dev libcunit1-dev libpciaccess-dev meson ninja-build pkg-config python3 python3-pip python3-wheel python3-setuptools python3-docutils valgrind'
- FDO_DISTRIBUTION_EXEC: 'pip3 install meson==0.53.0'
+ FDO_DISTRIBUTION_EXEC: 'pip3 install meson==0.59.0'
# bump this tag every time you change something which requires rebuilding the
# base image
- FDO_DISTRIBUTION_TAG: "2022-08-22.0"
+ FDO_DISTRIBUTION_TAG: "2023-09-01.0"
.debian-x86_64:
extends:
diff --git a/meson.build b/meson.build
index ba62da6e..f883760e 100644
--- a/meson.build
+++ b/meson.build
@@ -23,7 +23,7 @@ project(
['c'],
version : '2.4.116',
license : 'MIT',
- meson_version : '>= 0.53',
+ meson_version : '>= 0.59',
default_options : ['buildtype=debugoptimized', 'c_std=c11'],
)
@@ -84,113 +84,61 @@ config.set10('HAVE_LIB_ATOMIC_OPS', lib_atomics)
dep_pciaccess = dependency('pciaccess', version : '>= 0.10', required : get_option('intel'))
-with_intel = false
-_intel = get_option('intel')
-if not _intel.disabled()
- if _intel.enabled()
- if not with_atomics
- error('libdrm_intel requires atomics.')
- elif not dep_pciaccess.found()
- error('libdrm_intel requires libpciaccess')
- endif
- else
- with_intel = (_intel.enabled() or host_machine.cpu_family().startswith('x86')) and with_atomics and dep_pciaccess.found()
- endif
-endif
+with_intel = get_option('intel') \
+ .require(with_atomics, error_message : 'libdrm_intel requires atomics') \
+ .require(dep_pciaccess.found(), error_message : 'libdrm_intel requires libpciaccess') \
+ .disable_auto_if(not host_machine.system().startswith('x86')) \
+ .allowed()
summary('Intel', with_intel)
-with_radeon = false
-_radeon = get_option('radeon')
-if not _radeon.disabled()
- if _radeon.enabled() and not with_atomics
- error('libdrm_radeon requires atomics.')
- endif
- with_radeon = with_atomics
-endif
+with_radeon = get_option('radeon') \
+ .require(with_atomics, error_message : 'libdrm_radeon requires atomics') \
+ .allowed()
summary('Radeon', with_radeon)
-with_amdgpu = false
-_amdgpu = get_option('amdgpu')
-if not _amdgpu.disabled()
- if _amdgpu.enabled() and not with_atomics
- error('libdrm_amdgpu requires atomics.')
- endif
- with_amdgpu = with_atomics
-endif
+with_amdgpu = get_option('amdgpu') \
+ .require(with_atomics, error_message : 'libdrm_amdgpu requires atomics') \
+ .allowed()
summary('AMDGPU', with_amdgpu)
-with_nouveau = false
-_nouveau = get_option('nouveau')
-if not _nouveau.disabled()
- if _nouveau.enabled() and not with_atomics
- error('libdrm_nouveau requires atomics.')
- endif
- with_nouveau = with_atomics
-endif
+with_nouveau = get_option('nouveau') \
+ .require(with_atomics, error_message : 'libdrm_nouveau requires atomics') \
+ .allowed()
summary('Nouveau', with_nouveau)
-with_vmwgfx = false
-_vmwgfx = get_option('vmwgfx')
-if not _vmwgfx.disabled()
- with_vmwgfx = true
-endif
+with_vmwgfx = get_option('vmwgfx').allowed()
summary('vmwgfx', with_vmwgfx)
-with_omap = false
-_omap = get_option('omap')
-if _omap.enabled()
- if not with_atomics
- error('libdrm_omap requires atomics.')
- endif
- with_omap = true
-endif
+with_omap = get_option('omap') \
+ .require(with_atomics, error_message : 'libdrm_omap requires atomics') \
+ .enabled()
summary('OMAP', with_omap)
-with_freedreno = false
-_freedreno = get_option('freedreno')
-if not _freedreno.disabled()
- if _freedreno.enabled() and not with_atomics
- error('libdrm_freedreno requires atomics.')
- else
- with_freedreno = (_freedreno.enabled() or ['arm', 'aarch64'].contains(host_machine.cpu_family())) and with_atomics
- endif
-endif
+with_freedreno = get_option('freedreno') \
+ .require(with_atomics, error_message : 'libdrm_freedreno requires atomics') \
+ .disable_auto_if(not ['arm', 'aarch64'].contains(host_machine.cpu_family())) \
+ .allowed()
summary('Freedreno', with_freedreno)
summary('Freedreon-kgsl', with_freedreno_kgsl)
-with_tegra = false
-_tegra = get_option('tegra')
-if _tegra.enabled()
- if not with_atomics
- error('libdrm_tegra requires atomics.')
- endif
- with_tegra = true
-endif
+with_tegra = get_option('tegra') \
+ .require(with_atomics, error_message : 'libdrm_tegra requires atomics') \
+ .disable_auto_if(not ['arm', 'aarch64'].contains(host_machine.cpu_family())) \
+ .enabled()
summary('Tegra', with_tegra)
-with_etnaviv = false
-_etnaviv = get_option('etnaviv')
-if not _etnaviv.disabled()
- if _etnaviv.enabled() and not with_atomics
- error('libdrm_etnaviv requires atomics.')
- endif
- with_etnaviv = _etnaviv.enabled() or (
- with_atomics and [
- 'loongarch64', 'mips', 'mips64',
- 'arm', 'aarch64', 'arc',
- ].contains(host_machine.cpu_family())
- )
-endif
+with_etnaviv = get_option('etnaviv') \
+ .require(with_atomics, error_message : 'libdrm_etnaviv requires atomics') \
+ .disable_auto_if(not ['arm', 'aarch64', 'arc', 'mips', 'mips64', 'loongarch64'].contains(host_machine.cpu_family())) \
+ .allowed()
summary('Etnaviv', with_etnaviv)
with_exynos = get_option('exynos').enabled()
summary('EXYNOS', with_exynos)
-with_vc4 = false
-_vc4 = get_option('vc4')
-if not _vc4.disabled()
- with_vc4 = _vc4.enabled() or ['arm', 'aarch64'].contains(host_machine.cpu_family())
-endif
+with_vc4 = get_option('vc4') \
+ .disable_auto_if(not ['arm', 'aarch64'].contains(host_machine.cpu_family())) \
+ .allowed()
summary('VC4', with_vc4)
# Among others FreeBSD does not have a separate dl library.
commit a6a2ccb4486306c3caa5ccd337d972b61b97f75a
Author: Dylan Baker <dy...@pn...>
Date: Fri Sep 1 12:09:24 2023 -0700
meson: fix intel requirements
Intel requires libpciaccess and an x86/x86_64 host, so if those
aren't found and it's enabled we need to error
Signed-off-by: Dylan Baker <dyl...@in...>
Reviewed-by: Simon Ser <co...@em...>
diff --git a/meson.build b/meson.build
index 05f05fd9..ba62da6e 100644
--- a/meson.build
+++ b/meson.build
@@ -87,8 +87,12 @@ dep_pciaccess = dependency('pciaccess', version : '>= 0.10', required : get_opti
with_intel = false
_intel = get_option('intel')
if not _intel.disabled()
- if _intel.enabled() and not with_atomics
- error('libdrm_intel requires atomics.')
+ if _intel.enabled()
+ if not with_atomics
+ error('libdrm_intel requires atomics.')
+ elif not dep_pciaccess.found()
+ error('libdrm_intel requires libpciaccess')
+ endif
else
with_intel = (_intel.enabled() or host_machine.cpu_family().startswith('x86')) and with_atomics and dep_pciaccess.found()
endif
|
|
From: GitLab M. <git...@ke...> - 2024-05-28 17:12:51
|
tests/amdgpu/shader_code.h | 8 ++++----
tests/amdgpu/shader_code_gfx10.h | 20 ++++++++++----------
tests/amdgpu/shader_code_gfx11.h | 22 +++++++++++-----------
tests/amdgpu/shader_code_gfx9.h | 21 +++++++++++----------
tests/amdgpu/shader_test_util.c | 28 ++++++++++++++++++++++++++++
5 files changed, 64 insertions(+), 35 deletions(-)
New commits:
commit 37265ab0ad36af456b664b8656e126a6c770e61a
Author: Flora Cui <flo...@am...>
Date: Thu May 23 15:15:56 2024 +0800
tests/amdgpu: fix compile error with gcc14
../../drm/tests/amdgpu/shader_code.h:114:9: error: initialization of
‘const uint32_t *’ {aka ‘const unsigned int *’} from incompatible
pointer type ‘const uint32_t (*)[10][6]’ {aka ‘const unsigned int
(*)[10][6]’} [-Wincompatible-pointer-types]
114 | ps_##_ps##_shader_patchinfo_code_gfx##_n, \
| ^~~
../../drm/tests/amdgpu/shader_code.h:119:10: note: in expansion of macro
‘SHADER_PS_INFO’
119 | {SHADER_PS_INFO(const, 9), SHADER_PS_INFO(tex, 9)},
| ^~~~~~~~~~~~~~
Signed-off-by: Flora Cui <flo...@am...>
Reviewed-by: Marek Olšák <mar...@am...>
diff --git a/tests/amdgpu/shader_code.h b/tests/amdgpu/shader_code.h
index 601d16a7..164c6193 100644
--- a/tests/amdgpu/shader_code.h
+++ b/tests/amdgpu/shader_code.h
@@ -111,7 +111,7 @@ static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2]
#define SHADER_PS_INFO(_ps, _n) \
{ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \
ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
- ps_##_ps##_shader_patchinfo_code_gfx##_n, \
+ &(ps_##_ps##_shader_patchinfo_code_gfx##_n)[0][0][0], \
ps_##_ps##_shader_patchinfo_offset_gfx##_n, \
ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \
ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n}
commit cee441f32d65f25bda510669cf46f87f3dce1f0e
Author: Flora Cui <flo...@am...>
Date: Wed Aug 24 11:28:23 2022 +0800
tests/amdgpu: fix compile error with gcc7.5
fix commit cc3c80c6("tests/amdgpu: refactor dispatch/draw test")
../../SOURCES/drm/tests/amdgpu/shader_code.h:113:2: error: initializer
element is not constant
ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
^
Signed-off-by: Flora Cui <flo...@am...>
Reviewed-by: Marek Olšák <mar...@am...>
diff --git a/tests/amdgpu/shader_code.h b/tests/amdgpu/shader_code.h
index 74d32bb5..601d16a7 100644
--- a/tests/amdgpu/shader_code.h
+++ b/tests/amdgpu/shader_code.h
@@ -75,13 +75,13 @@ struct shader_test_cs_shader {
struct shader_test_ps_shader {
const uint32_t *shader;
unsigned shader_size;
- const uint32_t patchinfo_code_size;
+ uint32_t patchinfo_code_size;
const uint32_t *patchinfo_code;
const uint32_t *patchinfo_code_offset;
const struct reg_info *sh_reg;
- const uint32_t num_sh_reg;
+ uint32_t num_sh_reg;
const struct reg_info *context_reg;
- const uint32_t num_context_reg;
+ uint32_t num_context_reg;
};
struct shader_test_vs_shader {
diff --git a/tests/amdgpu/shader_code_gfx10.h b/tests/amdgpu/shader_code_gfx10.h
index 4849bbc9..1e7c8f96 100644
--- a/tests/amdgpu/shader_code_gfx10.h
+++ b/tests/amdgpu/shader_code_gfx10.h
@@ -41,7 +41,7 @@ static const uint32_t ps_const_shader_gfx10[] = {
0xF8001C0F, 0x00000100, 0xBF810000
};
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6;
+#define ps_const_shader_patchinfo_code_size_gfx10 6
static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
@@ -61,7 +61,7 @@ static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = {
0x00000004
};
-static const uint32_t ps_const_num_sh_registers_gfx10 = 2;
+#define ps_const_num_sh_registers_gfx10 2
static const struct reg_info ps_const_sh_registers_gfx10[] = {
{0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 },
@@ -79,7 +79,7 @@ static const struct reg_info ps_const_context_registers_gfx10[] =
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
};
-static const uint32_t ps_const_num_context_registers_gfx10 = 7;
+#define ps_const_num_context_registers_gfx10 7
static const uint32_t ps_tex_shader_gfx10[] = {
0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000,
@@ -93,7 +93,7 @@ static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = {
0x0000000C
};
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6;
+#define ps_tex_shader_patchinfo_code_size_gfx10 6
static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
@@ -115,7 +115,7 @@ static const struct reg_info ps_tex_sh_registers_gfx10[] =
{0x2C0B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
};
-static const uint32_t ps_tex_num_sh_registers_gfx10 = 2;
+#define ps_tex_num_sh_registers_gfx10 2
// Holds Context Register Information
static const struct reg_info ps_tex_context_registers_gfx10[] =
@@ -129,7 +129,7 @@ static const struct reg_info ps_tex_context_registers_gfx10[] =
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
};
-static const uint32_t ps_tex_num_context_registers_gfx10 = 7;
+#define ps_tex_num_context_registers_gfx10 7
static const uint32_t vs_RectPosTexFast_shader_gfx10[] = {
0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206,
@@ -148,7 +148,7 @@ static const struct reg_info vs_RectPosTexFast_sh_registers_gfx10[] =
{0x2C4B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
};
-static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx10 = 2;
+#define vs_RectPosTexFast_num_sh_registers_gfx10 2
// Holds Context Register Information
static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
@@ -157,7 +157,7 @@ static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
};
-static const uint32_t vs_RectPosTexFast_num_context_registers_gfx10 = 2;
+#define vs_RectPosTexFast_num_context_registers_gfx10 2
static const uint32_t preamblecache_gfx10[] = {
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
@@ -196,7 +196,7 @@ static const uint32_t cached_cmd_gfx10[] = {
0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
};
-static const uint32_t sh_reg_base_gfx10 = 0x2C00;
-static const uint32_t context_reg_base_gfx10 = 0xA000;
+#define sh_reg_base_gfx10 0x2C00
+#define context_reg_base_gfx10 0xA000
#endif
diff --git a/tests/amdgpu/shader_code_gfx11.h b/tests/amdgpu/shader_code_gfx11.h
index d9ee0a7c..8a998ae8 100644
--- a/tests/amdgpu/shader_code_gfx11.h
+++ b/tests/amdgpu/shader_code_gfx11.h
@@ -101,7 +101,7 @@ static const uint32_t ps_const_shader_gfx11[] = {
0xBF9F0000
};
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx11 = 6;
+#define ps_const_shader_patchinfo_code_size_gfx11 6
static const uint32_t ps_const_shader_patchinfo_code_gfx11[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 }, // SI_EXPORT_FMT_ZERO
@@ -121,7 +121,7 @@ static const uint32_t ps_const_shader_patchinfo_offset_gfx11[] = {
0x00000006
};
-static const uint32_t ps_const_num_sh_registers_gfx11 = 2;
+#define ps_const_num_sh_registers_gfx11 2
static const struct reg_info ps_const_sh_registers_gfx11[] = {
{0x2C0A, 0x020C0000}, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0000 },
@@ -138,7 +138,7 @@ static const struct reg_info ps_const_context_registers_gfx11[] = {
{0xA1C5, 0x00000004 }, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
};
-static const uint32_t ps_const_num_context_registers_gfx11 = 7;
+#define ps_const_num_context_registers_gfx11 7
static const uint32_t ps_tex_shader_gfx11[] =
{
@@ -174,7 +174,7 @@ static const uint32_t ps_tex_shader_patchinfo_offset_gfx11[] =
};
// Denotes the Patch Info Code Length
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx11 = 6;
+#define ps_tex_shader_patchinfo_code_size_gfx11 6
static const uint32_t ps_tex_shader_patchinfo_code_gfx11[][10][6] =
{
@@ -197,7 +197,7 @@ static const struct reg_info ps_tex_sh_registers_gfx11[] =
{0x2C0B, 0x00000018 } //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
};
-static const uint32_t ps_tex_num_sh_registers_gfx11 = 2;
+#define ps_tex_num_sh_registers_gfx11 2
// Holds Context Register Information
static const struct reg_info ps_tex_context_registers_gfx11[] =
@@ -211,8 +211,7 @@ static const struct reg_info ps_tex_context_registers_gfx11[] =
{0xA1C5, 0x00000004 } //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
};
-static const uint32_t ps_tex_num_context_registers_gfx11 = 7;
-
+#define ps_tex_num_context_registers_gfx11 7
static const uint32_t vs_RectPosTexFast_shader_gfx11[] =
{
@@ -261,7 +260,7 @@ static const struct reg_info vs_RectPosTexFast_sh_registers_gfx11[] =
{0x2C8B, 0x0008001C}, //{ mmSPI_SHADER_PGM_RSRC2_GS, 0x0008001C }
};
-static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx11 = 2;
+#define vs_RectPosTexFast_num_sh_registers_gfx11 2
// Holds Context Register Information
static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] =
@@ -274,7 +273,7 @@ static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] =
{0xA2CE, 0x00000001}, //{ mmVGT_GS_MAX_VERT_OUT, 0x00000001 }
};
-static const uint32_t vs_RectPosTexFast_num_context_registers_gfx11 = 6;
+#define vs_RectPosTexFast_num_context_registers_gfx11 6
static const uint32_t preamblecache_gfx11[] = {
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
@@ -314,7 +313,8 @@ static const uint32_t cached_cmd_gfx11[] = {
0xc0046900, 0x1d5, 0x0, 0x0, 0x0, 0x0, 0xc0016900, 0x104, 0x4a00005,
0xc0016900, 0x1f, 0xf2a0055, 0xc0017900, 0x266, 0x4
};
-static const uint32_t sh_reg_base_gfx11 = 0x2C00;
-static const uint32_t context_reg_base_gfx11 = 0xA000;
+
+#define sh_reg_base_gfx11 0x2C00
+#define context_reg_base_gfx11 0xA000
#endif
diff --git a/tests/amdgpu/shader_code_gfx9.h b/tests/amdgpu/shader_code_gfx9.h
index 3ad1ca8f..1cb6582f 100644
--- a/tests/amdgpu/shader_code_gfx9.h
+++ b/tests/amdgpu/shader_code_gfx9.h
@@ -51,7 +51,7 @@ static const uint32_t ps_const_shader_gfx9[] = {
0xC4001C0F, 0x00000100, 0xBF810000
};
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6;
+#define ps_const_shader_patchinfo_code_size_gfx9 6
static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
@@ -71,14 +71,14 @@ static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
0x00000004
};
-static const uint32_t ps_const_num_sh_registers_gfx9 = 2;
+#define ps_const_num_sh_registers_gfx9 2
static const struct reg_info ps_const_sh_registers_gfx9[] = {
{0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
};
-static const uint32_t ps_const_num_context_registers_gfx9 = 7;
+#define ps_const_num_context_registers_gfx9 7
static const struct reg_info ps_const_context_registers_gfx9[] = {
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
@@ -102,7 +102,7 @@ static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = {
0x0000000B
};
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6;
+#define ps_tex_shader_patchinfo_code_size_gfx9 6
static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
@@ -118,13 +118,14 @@ static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
}
};
-static const uint32_t ps_tex_num_sh_registers_gfx9 = 2;
+#define ps_tex_num_sh_registers_gfx9 2
+
static const struct reg_info ps_tex_sh_registers_gfx9[] = {
{0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
{0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
};
-static const uint32_t ps_tex_num_context_registers_gfx9 = 7;
+#define ps_tex_num_context_registers_gfx9 7
static const struct reg_info ps_tex_context_registers_gfx9[] = {
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
@@ -153,7 +154,7 @@ static const struct reg_info vs_RectPosTexFast_sh_registers_gfx9[] =
{0x2C4B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
};
-static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx9 = 2;
+#define vs_RectPosTexFast_num_sh_registers_gfx9 2
// Holds Context Register Information
static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
@@ -162,7 +163,7 @@ static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
};
-static const uint32_t vs_RectPosTexFast_num_context_registers_gfx9 = 2;
+#define vs_RectPosTexFast_num_context_registers_gfx9 2
static const uint32_t preamblecache_gfx9[] = {
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
@@ -198,7 +199,7 @@ static const uint32_t cached_cmd_gfx9[] = {
0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
};
-static const uint32_t sh_reg_base_gfx9 = 0x2C00;
-static const uint32_t context_reg_base_gfx9 = 0xA000;
+#define sh_reg_base_gfx9 0x2C00
+#define context_reg_base_gfx9 0xA000
#endif
commit 058a04de62f9a4f71511ff9172f4f219a63d29f2
Author: Flora Cui <flo...@am...>
Date: Thu May 23 15:02:13 2024 +0800
tests/amdgpu: fix compile warning with the guard enum value
../../drm/tests/amdgpu/shader_test_util.c: In function
‘amdgpu_dispatch_init’:
../../drm/tests/amdgpu/shader_test_util.c:296:9: warning: enumeration
value ‘AMDGPU_TEST_GFX_MAX’ not handled in switch [-Wswitch]
296 | switch (test_priv->info->version) {
| ^~~~~~
Signed-off-by: Flora Cui <flo...@am...>
Reviewed-by: Marek Olšák <mar...@am...>
diff --git a/tests/amdgpu/shader_test_util.c b/tests/amdgpu/shader_test_util.c
index 60148fb8..8a19f59f 100644
--- a/tests/amdgpu/shader_test_util.c
+++ b/tests/amdgpu/shader_test_util.c
@@ -4,6 +4,7 @@
#include <sys/types.h>
#include <sys/stat.h>
#include <string.h>
+#include <assert.h>
#include "CUnit/Basic.h"
#include "amdgpu_test.h"
@@ -303,6 +304,9 @@ static void amdgpu_dispatch_init(struct shader_test_priv *test_priv)
case AMDGPU_TEST_GFX_V11:
amdgpu_dispatch_init_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -338,6 +342,9 @@ static void amdgpu_dispatch_write_cumask(struct shader_test_priv *test_priv)
ptr[i++] = 0xffffffff;
ptr[i++] = 0xffffffff;
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
test_priv->cmd_curr = i;
@@ -541,6 +548,9 @@ static void amdgpu_dispatch_write2hw(struct shader_test_priv *test_priv)
case AMDGPU_TEST_GFX_V11:
amdgpu_dispatch_write2hw_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1168,6 +1178,9 @@ static void amdgpu_draw_setup_and_write_drawblt_surf_info(struct shader_test_pri
case AMDGPU_TEST_GFX_V11:
amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1298,6 +1311,9 @@ static void amdgpu_draw_setup_and_write_drawblt_state(struct shader_test_priv *t
case AMDGPU_TEST_GFX_V11:
amdgpu_draw_setup_and_write_drawblt_state_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1546,6 +1562,9 @@ static void amdgpu_draw_vs_RectPosTexFast_write2hw(struct shader_test_priv *test
case AMDGPU_TEST_GFX_V11:
amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1679,6 +1698,9 @@ static void amdgpu_draw_ps_write2hw(struct shader_test_priv *test_priv)
case AMDGPU_TEST_GFX_V11:
amdgpu_draw_ps_write2hw_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1718,6 +1740,9 @@ static void amdgpu_draw_draw(struct shader_test_priv *test_priv)
ptr[i++] = 0x242;
ptr[i++] = 0x11;
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1);
@@ -2010,6 +2035,9 @@ static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info)
ptr_cmd[i++] = 0x400;
i++;
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
|
|
From: GitLab M. <git...@ke...> - 2025-06-08 12:16:35
|
.gitlab-ci.yml | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
New commits:
commit dccb4b18e24d2e8a52d9d1bcb95d01d534b83c06
Author: Simon Ser <co...@em...>
Date: Thu May 22 15:37:44 2025 +0200
ci: fix arm32v7 Debian container preparation
buildah tried to pull the arm64 variant of the arm32v7/debian:bookworm
container:
* choosing an image from manifest list docker://arm32v7/debian:bookworm: no image found in image index for architecture "arm64", variant "v8", OS "linux"
Signed-off-by: Simon Ser <co...@em...>
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index df555c7c..1993e976 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -62,6 +62,7 @@ stages:
- .os-debian
variables:
BUILD_ARCH: "armv7"
+ FDO_DISTRIBUTION_PLATFORM: linux/arm/v7
.os-freebsd:
variables:
commit c3a4c985d5e2d723c7a15a1c358e28be4befd769
Author: Simon Ser <co...@em...>
Date: Thu May 22 15:25:35 2025 +0200
ci: upgrade FreeBSD to version 14.2
py39-docutils doesn't exist in the package repositories, likely
because the Python version has been upgraded. Let's not hardcode
the Python version in the package name.
Signed-off-by: Simon Ser <co...@em...>
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 1842ca07..df555c7c 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -66,11 +66,11 @@ stages:
.os-freebsd:
variables:
BUILD_OS: freebsd
- FDO_DISTRIBUTION_VERSION: "14.1"
- FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess py39-docutils cairo'
+ FDO_DISTRIBUTION_VERSION: "14.2"
+ FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess textproc/py-docutils cairo'
# bump this tag every time you change something which requires rebuilding the
# base image
- FDO_DISTRIBUTION_TAG: "2026-26-25.0"
+ FDO_DISTRIBUTION_TAG: "2025-05-22.0"
.freebsd-x86_64:
extends:
commit e9a886f8592fbcb3c82c3c9949fa09424c51d032
Author: Simon Ser <co...@em...>
Date: Thu May 22 15:23:00 2025 +0200
ci: upgrade ci-templates to latest commit
Signed-off-by: Simon Ser <co...@em...>
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index ca8972cb..1842ca07 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -12,7 +12,7 @@
# main repository, it's recommended to remove the image from the source
# repository's container registry, so that the image from the main
# repository's registry will be used there as well.
-.templates_sha: &template_sha b61a03cabbf308e81289f7aaaf0b5a80a34ffb99 # see https://docs.gitlab.com/ee/ci/yaml/#includefile
+.templates_sha: &template_sha c6aeb16f86e32525fa630fb99c66c4f3e62fc3cb # see https://docs.gitlab.com/ee/ci/yaml/#includefile
include:
- project: 'freedesktop/ci-templates'
|
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