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dri-patches
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From: <aus...@ke...> - 2017-04-14 23:05:46
|
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit f02719c5246d301a50d7e0356bf3fe61b1e945a1
Author: Christian Gmeiner <chr...@gm...>
Date: Sat Apr 15 00:45:57 2017 +0200
configure.ac: bump version for release
Signed-off-by: Christian Gmeiner <chr...@gm...>
diff --git a/configure.ac b/configure.ac
index a67480c1..e5158b7d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.79],
+ [2.4.80],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
|
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From: <rob...@ke...> - 2017-04-15 18:46:40
|
freedreno/freedreno_device.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
New commits:
commit f45853802e910fd472f368a2d461708491fedfa3
Author: Rob Clark <rob...@fr...>
Date: Sat Apr 15 14:43:17 2017 -0400
freedreno: fix double-free on exit
Fixes: a07ae97 ("freedreno: fix device close issues")
Signed-off-by: Rob Clark <rob...@fr...>
diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c
index dba7ec47..12b95fd0 100644
--- a/freedreno/freedreno_device.c
+++ b/freedreno/freedreno_device.c
@@ -112,13 +112,13 @@ struct fd_device * fd_device_ref(struct fd_device *dev)
static void fd_device_del_impl(struct fd_device *dev)
{
+ int close_fd = dev->closefd ? dev->fd : -1;
fd_bo_cache_cleanup(&dev->bo_cache, 0);
drmHashDestroy(dev->handle_table);
drmHashDestroy(dev->name_table);
dev->funcs->destroy(dev);
- if (dev->closefd)
- close(dev->fd);
- free(dev);
+ if (close_fd >= 0)
+ close(close_fd);
}
drm_private void fd_device_del_locked(struct fd_device *dev)
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From: <fun...@ke...> - 2017-04-19 08:09:01
|
amdgpu/amdgpu_bo.c | 2 +-
amdgpu/amdgpu_cs.c | 43 +++++++++++++------------------------------
amdgpu/amdgpu_gpu_info.c | 5 +++--
3 files changed, 17 insertions(+), 33 deletions(-)
New commits:
commit 7cfcd5ef4b394f66c4a6fde705cf7c583a0b0c7b
Author: Edward O'Callaghan <fun...@fo...>
Date: Wed Apr 19 02:13:19 2017 +1000
amdgpu/: concisely && consistently check null ptrs in canonical form
Be consistent and use the canonical form while sanity checking
null pointers, also combine a few branches for brevity.
v2: rebase on top of 'add amdgpu_cs_wait_fences' series.
Signed-off-by: Edward O'Callaghan <fun...@fo...>
Reviewed-by: Nicolai Hähnle <nic...@am...>
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 9adfffa2..5ac456be 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -652,7 +652,7 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
return -EINVAL;
list = malloc(number_of_resources * sizeof(struct drm_amdgpu_bo_list_entry));
- if (list == NULL)
+ if (!list)
return -ENOMEM;
args.in.operation = AMDGPU_BO_LIST_OP_UPDATE;
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 779c7dbc..0993a6d8 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -59,13 +59,11 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
int i, j, k;
int r;
- if (NULL == dev)
- return -EINVAL;
- if (NULL == context)
+ if (!dev || !context)
return -EINVAL;
gpu_context = calloc(1, sizeof(struct amdgpu_context));
- if (NULL == gpu_context)
+ if (!gpu_context)
return -ENOMEM;
gpu_context->dev = dev;
@@ -110,7 +108,7 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context)
int i, j, k;
int r;
- if (NULL == context)
+ if (!context)
return -EINVAL;
pthread_mutex_destroy(&context->sequence_mutex);
@@ -330,9 +328,7 @@ int amdgpu_cs_submit(amdgpu_context_handle context,
uint32_t i;
int r;
- if (NULL == context)
- return -EINVAL;
- if (NULL == ibs_request)
+ if (!context || !ibs_request)
return -EINVAL;
r = 0;
@@ -416,11 +412,7 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
bool busy = true;
int r;
- if (NULL == fence)
- return -EINVAL;
- if (NULL == expired)
- return -EINVAL;
- if (NULL == fence->context)
+ if (!fence || !expired || !fence->context)
return -EINVAL;
if (fence->ip_type >= AMDGPU_HW_IP_NUM)
return -EINVAL;
@@ -493,12 +485,9 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
uint32_t i;
/* Sanity check */
- if (NULL == fences)
- return -EINVAL;
- if (NULL == status)
- return -EINVAL;
- if (fence_count <= 0)
+ if (!fences || !status || !fence_count)
return -EINVAL;
+
for (i = 0; i < fence_count; i++) {
if (NULL == fences[i].context)
return -EINVAL;
@@ -518,11 +507,11 @@ int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
{
struct amdgpu_semaphore *gpu_semaphore;
- if (NULL == sem)
+ if (!sem)
return -EINVAL;
gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore));
- if (NULL == gpu_semaphore)
+ if (!gpu_semaphore)
return -ENOMEM;
atomic_set(&gpu_semaphore->refcount, 1);
@@ -537,14 +526,12 @@ int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
uint32_t ring,
amdgpu_semaphore_handle sem)
{
- if (NULL == ctx)
+ if (!ctx || !sem)
return -EINVAL;
if (ip_type >= AMDGPU_HW_IP_NUM)
return -EINVAL;
if (ring >= AMDGPU_CS_MAX_RINGS)
return -EINVAL;
- if (NULL == sem)
- return -EINVAL;
/* sem has been signaled */
if (sem->signal_fence.context)
return -EINVAL;
@@ -565,14 +552,12 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
uint32_t ring,
amdgpu_semaphore_handle sem)
{
- if (NULL == ctx)
+ if (!ctx || !sem)
return -EINVAL;
if (ip_type >= AMDGPU_HW_IP_NUM)
return -EINVAL;
if (ring >= AMDGPU_CS_MAX_RINGS)
return -EINVAL;
- if (NULL == sem)
- return -EINVAL;
/* must signal first */
if (NULL == sem->signal_fence.context)
return -EINVAL;
@@ -585,9 +570,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
{
- if (NULL == sem)
- return -EINVAL;
- if (NULL == sem->signal_fence.context)
+ if (!sem || !sem->signal_fence.context)
return -EINVAL;
sem->signal_fence.context = NULL;;
@@ -601,7 +584,7 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem)
{
- if (NULL == sem)
+ if (!sem)
return -EINVAL;
if (update_references(&sem->refcount, NULL))
diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index f4b94c9e..1efffc6f 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -234,8 +234,9 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
int amdgpu_query_gpu_info(amdgpu_device_handle dev,
struct amdgpu_gpu_info *info)
{
- if ((dev == NULL) || (info == NULL))
+ if (!dev || !info)
return -EINVAL;
+
/* Get ASIC info*/
*info = dev->info;
@@ -300,7 +301,7 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev,
struct drm_amdgpu_info_gds gds_config = {};
int r;
- if (gds_info == NULL)
+ if (!gds_info)
return -EINVAL;
r = amdgpu_query_info(dev, AMDGPU_INFO_GDS_CONFIG,
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From: <im...@ke...> - 2017-04-20 03:26:55
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tests/modetest/modetest.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
New commits:
commit 691a21579962d2db2d5cb1de5286fa86ef22214f
Author: Ilia Mirkin <im...@al...>
Date: Tue Apr 18 08:54:11 2017 -0400
modetest: fix printing of fourcc on BE machines
fourcc is not a string, it's a packed integer. This happens to work out
on LE, but gets reversed on BE.
Signed-off-by: Ilia Mirkin <im...@al...>
Reviewed-by: Michel Dänzer <mic...@am...>
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index c390d875..b8891ff5 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -174,6 +174,15 @@ static const char *mode_flag_names[] = {
static bit_name_fn(mode_flag)
+static void dump_fourcc(uint32_t fourcc)
+{
+ printf(" %c%c%c%c",
+ fourcc,
+ fourcc >> 8,
+ fourcc >> 16,
+ fourcc >> 24);
+}
+
static void dump_encoders(struct device *dev)
{
drmModeEncoder *encoder;
@@ -443,7 +452,7 @@ static void dump_planes(struct device *dev)
printf(" formats:");
for (j = 0; j < ovr->count_formats; j++)
- printf(" %4.4s", (char *)&ovr->formats[j]);
+ dump_fourcc(ovr->formats[j]);
printf("\n");
if (plane->props) {
|
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From: <fun...@ke...> - 2017-05-03 11:36:27
|
amdgpu/amdgpu_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit 00aa2c18810efb896afd9ff0acbadd4aa9540fe6
Author: Edward O'Callaghan <fun...@fo...>
Date: Sat Apr 22 16:47:40 2017 +1000
amdgpu: Use the canonical form in branch predicate
Suggested-by: Emil Velikov <emi...@gm...>
Signed-off-by: Edward O'Callaghan <fun...@fo...>
Reviewed-by: Emil Velikov <emi...@gm...>
Reviewed-by: Nicolai Hähnle <nic...@am...>
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 0993a6d8..868eb7b0 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -559,7 +559,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
if (ring >= AMDGPU_CS_MAX_RINGS)
return -EINVAL;
/* must signal first */
- if (NULL == sem->signal_fence.context)
+ if (!sem->signal_fence.context)
return -EINVAL;
pthread_mutex_lock(&ctx->sequence_mutex);
|
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From: <aj...@ke...> - 2017-05-04 19:57:50
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xf86drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit a2fa2e08692483cf9f4d06caa6e0f0add59e3343
Author: Adam Jackson <aj...@re...>
Date: Thu May 4 15:57:14 2017 -0400
Fix stray caller of drmCompareDevices
Signed-off-by: Adam Jackson <aj...@re...>
diff --git a/xf86drm.c b/xf86drm.c
index 29fea331..728ac78c 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -3669,7 +3669,7 @@ static void drmFoldDuplicatedDevices(drmDevicePtr local_devices[], int count)
for (i = 0; i < count; i++) {
for (j = i + 1; j < count; j++) {
- if (drmCompareDevices(local_devices[i], local_devices[j])) {
+ if (drmDevicesEqual(local_devices[i], local_devices[j])) {
local_devices[i]->available_nodes |= local_devices[j]->available_nodes;
node_type = log2(local_devices[j]->available_nodes);
memcpy(local_devices[i]->nodes[node_type],
|
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From: <nh...@ke...> - 2017-05-16 13:57:29
|
amdgpu/amdgpu.h | 8 ++++++++
1 file changed, 8 insertions(+)
New commits:
commit 41be41f99eb53bd4998b1cd930fa63f0e552d971
Author: Nicolai Hähnle <nic...@am...>
Date: Sat May 13 23:03:55 2017 +0200
amdgpu: add missing extern "C" headers
Signed-off-by: Nicolai Hähnle <nic...@am...>
Reviewed-by: Michel Dänzer <mic...@am...>
Reviewed-by: Alex Xie <Ale...@am...>
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index fdea9050..1901fa8c 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -37,6 +37,10 @@
#include <stdint.h>
#include <stdbool.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
struct drm_amdgpu_info_hw_ip;
/*--------------------------------------------------------------------------*/
@@ -1324,4 +1328,8 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
*/
const char *amdgpu_get_marketing_name(amdgpu_device_handle dev);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* #ifdef _AMDGPU_H_ */
|
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From: <ma...@ke...> - 2017-05-24 15:03:49
|
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit 81312f3730c14a2930a7784493701809c7f04a26
Author: Marek Olšák <mar...@am...>
Date: Wed May 24 17:01:36 2017 +0200
Bump version to 2.4.81
diff --git a/configure.ac b/configure.ac
index 43fcf68f..1cfb8c27 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.80],
+ [2.4.81],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
|
|
From: <ro...@ke...> - 2017-05-28 14:31:42
|
Android.common.mk | 1 +
1 file changed, 1 insertion(+)
New commits:
commit bbe998791d6cd0d5c048beba6ae8a6dbbf8185be
Author: Elliott Hughes <en...@go...>
Date: Sat May 20 11:24:29 2017 -0700
Android's major/minor/makedev live in <sys/sysmacros.h>
Bug: https://github.com/android-ndk/ndk/issues/398
Signed-off-by: Rob Herring <ro...@ke...>
diff --git a/Android.common.mk b/Android.common.mk
index 35c0f02c..4b5462f6 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -1,5 +1,6 @@
# XXX: Consider moving these to config.h analogous to autoconf.
LOCAL_CFLAGS += \
+ -DMAJOR_IN_SYSMACROS=1
-DHAVE_VISIBILITY=1 \
-DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1
|
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From: <ro...@ke...> - 2017-05-28 14:37:32
|
Android.common.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit ce9e3ba6e2cc65e1e9e6e05a5f326c4dd25ab2c4
Author: Rob Herring <ro...@ke...>
Date: Sun May 28 09:34:13 2017 -0500
Android: fix missing trailing \
In commit bbe998791d6c ("Android's major/minor/makedev live in
<sys/sysmacros.h>"), it didn't apply cleanly and I missed the trailing
\, so add it here.
Signed-off-by: Rob Herring <ro...@ke...>
diff --git a/Android.common.mk b/Android.common.mk
index 4b5462f6..b45ca10f 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -1,6 +1,6 @@
# XXX: Consider moving these to config.h analogous to autoconf.
LOCAL_CFLAGS += \
- -DMAJOR_IN_SYSMACROS=1
+ -DMAJOR_IN_SYSMACROS=1 \
-DHAVE_VISIBILITY=1 \
-DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1
|
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From: <ag...@ke...> - 2017-06-06 16:16:08
|
tests/amdgpu/amdgpu_test.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
New commits:
commit b6f450e065a538d566c71872ce890ff07956e3eb
Author: Tom St Denis <tom...@am...>
Date: Mon Jun 5 14:04:11 2017 -0400
tests/amdgpu: Fix device_id option
The device_id option [-d] was badly broken. This commit fixes
the width (was 8 is now 16 bits) as well as enables searches
without specifying a bus id. It was also comparing "dev" from
the bus field which is not the PCI device id.
Reviewed-by: Alex Deucher <ale...@am...>
Signed-off-by: Tom St Denis <tom...@am...>
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index bc901a9e..1d44b09e 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -270,25 +270,25 @@ static void amdgpu_print_devices()
/* Find a match AMD device in PCI bus
* Return the index of the device or -1 if not found
*/
-static int amdgpu_find_device(uint8_t bus, uint8_t dev)
+static int amdgpu_find_device(uint8_t bus, uint16_t dev)
{
int i;
drmDevicePtr device;
- for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++)
+ for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
if (drmGetDevice2(drm_amdgpu[i],
DRM_DEVICE_GET_PCI_REVISION,
&device) == 0) {
if (device->bustype == DRM_BUS_PCI)
- if (device->businfo.pci->bus == bus &&
- device->businfo.pci->dev == dev) {
-
+ if ((bus == 0xFF || device->businfo.pci->bus == bus) &&
+ device->deviceinfo.pci->device_id == dev) {
drmFreeDevice(&device);
return i;
}
drmFreeDevice(&device);
}
+ }
return -1;
}
@@ -331,7 +331,7 @@ int main(int argc, char **argv)
pci_bus_id = atoi(optarg);
break;
case 'd':
- pci_device_id = atoi(optarg);
+ sscanf(optarg, "%x", &pci_device_id);
break;
case 'p':
display_devices = 1;
@@ -365,10 +365,10 @@ int main(int argc, char **argv)
exit(EXIT_SUCCESS);
}
- if (pci_bus_id > 0) {
+ if (pci_bus_id > 0 || pci_device_id) {
/* A device was specified to run the test */
- test_device_index = amdgpu_find_device((uint8_t)pci_bus_id,
- (uint8_t)pci_device_id);
+ test_device_index = amdgpu_find_device(pci_bus_id,
+ pci_device_id);
if (test_device_index >= 0) {
/* Most tests run on device of drm_amdgpu[0].
|
|
From: <da...@ke...> - 2017-06-12 08:20:13
|
tests/amdgpu/Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit 57d67d55d32e9196fceef41a693c89d0eb163a72
Author: Michel Dänzer <mic...@am...>
Date: Mon Jun 12 17:15:21 2017 +0900
tests/amdgpu: s/uvd_messages.h/decode_messages.h/ in Makefile.am
Fixes make distcheck with amdgpu enabled.
Fixes: ec65d1980912 ("tests/amdgpu: rename uvd messages to decode
messages")
Trivial.
diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index d4572bec..9e085784 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -23,7 +23,7 @@ amdgpu_test_SOURCES = \
basic_tests.c \
bo_tests.c \
cs_tests.c \
- uvd_messages.h \
+ decode_messages.h \
vce_tests.c \
vce_ib.h \
frame.h \
|
|
From: <da...@ke...> - 2017-06-13 01:21:43
|
amdgpu/.editorconfig | 9 +++++++++
1 file changed, 9 insertions(+)
New commits:
commit 87dac00db38fa962c2fd6aa66c8482a9d7464903
Author: Michel Dänzer <mic...@am...>
Date: Mon Jun 12 19:00:13 2017 +0900
amdgpu: Add .editorconfig file for amdgpu coding style
The .editorconfig file in the toplevel directory doesn't match.
Acked-by: Christian König <chr...@am...>
Reviewed-by: Alex Deucher <ale...@am...>
diff --git a/amdgpu/.editorconfig b/amdgpu/.editorconfig
new file mode 100644
index 00000000..2528d675
--- /dev/null
+++ b/amdgpu/.editorconfig
@@ -0,0 +1,9 @@
+# To use this config with your editor, follow the instructions at:
+# http://editorconfig.org
+
+[*]
+charset = utf-8
+indent_style = tab
+indent_size = 8
+tab_width = 8
+insert_final_newline = true
|
|
From: <da...@ke...> - 2017-06-15 03:03:03
|
Makefile.am | 1
amdgpu/Makefile.am | 7 +
amdgpu/Makefile.sources | 2
amdgpu/amdgpu_asic_id.c | 219 +++++++++++++++++++++++++++++++++++++++++++++++
amdgpu/amdgpu_asic_id.h | 165 -----------------------------------
amdgpu/amdgpu_device.c | 28 ++++--
amdgpu/amdgpu_internal.h | 10 ++
configure.ac | 4
data/Makefile.am | 23 ++++
data/amdgpu.ids | 159 ++++++++++++++++++++++++++++++++++
10 files changed, 445 insertions(+), 173 deletions(-)
New commits:
commit 7e6bf88cac315a9fa41818cf72a7b5d18a2cb1fc
Author: Xiaojie Yuan <Xia...@am...>
Date: Wed May 31 16:22:50 2017 -0400
amdgpu: move asic id table to a separate file
v2: fix an off by one error and leading white spaces
v3: use thread safe strtok_r(); initialize len before calling getline();
change printf() to drmMsg(); add initial amdgpu.ids
v4: integrate some recent internal changes, including format changes
v5: fix line number for empty/commented lines; realloc to save memory;
indentation changes
v6: remove a line error
v7: [Michel Dänzer]
* Move amdgpu.ids to new data directory
* Remove placeholder entries from amdgpu.ids
* Set libdrmdatadir variable in configure.ac instead of Makefile.am
[Emil Velikov]
* Use isblank() instead of open-coding it [Emil Velikov]
* Don't leak asic_id_table memory if realloc fails [Emil Velikov]
* Check and bump table_max_size at the beginning of the while loop [Emil
Velikov]
* Initialize table_max_size to the number of entries in data/amdgpu.ids
v8: [Michel Dänzer]
* Make sure amdgpu_asic_id.c gets rebuilt when amdgpu.ids changes
Reviewed-by: Alex Deucher <ale...@am...>
Reviewed-by: Emil Velikov <emi...@gm...>
Signed-off-by: Samuel Li <Sam...@am...>
diff --git a/Makefile.am b/Makefile.am
index dfb8fcdb..7b86214e 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -109,6 +109,7 @@ SUBDIRS = \
$(TEGRA_SUBDIR) \
$(VC4_SUBDIR) \
$(ETNAVIV_SUBDIR) \
+ data \
tests \
$(MAN_SUBDIR)
diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am
index cf7bc1ba..66f6f676 100644
--- a/amdgpu/Makefile.am
+++ b/amdgpu/Makefile.am
@@ -30,12 +30,19 @@ AM_CFLAGS = \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
+libdrmdatadir = @libdrmdatadir@
+ASIC_ID_TABLE_NUM_ENTRIES := $(shell egrep -ci '^[0-9a-f]{4},.*[0-9a-f]+,' \
+ $(top_srcdir)/data/amdgpu.ids)
+AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\" \
+ -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(ASIC_ID_TABLE_NUM_ENTRIES)
+
libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
libdrm_amdgpu_ladir = $(libdir)
libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 -no-undefined
libdrm_amdgpu_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@
libdrm_amdgpu_la_SOURCES = $(LIBDRM_AMDGPU_FILES)
+amdgpu_asic_id.lo: $(top_srcdir)/data/amdgpu.ids
libdrm_amdgpuincludedir = ${includedir}/libdrm
libdrm_amdgpuinclude_HEADERS = $(LIBDRM_AMDGPU_H_FILES)
diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources
index 487b9e0a..bc3abaa6 100644
--- a/amdgpu/Makefile.sources
+++ b/amdgpu/Makefile.sources
@@ -1,5 +1,5 @@
LIBDRM_AMDGPU_FILES := \
- amdgpu_asic_id.h \
+ amdgpu_asic_id.c \
amdgpu_bo.c \
amdgpu_cs.c \
amdgpu_device.c \
diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c
new file mode 100644
index 00000000..3a88896b
--- /dev/null
+++ b/amdgpu/amdgpu_asic_id.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright © 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <ctype.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+
+#include "xf86drm.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+
+static int parse_one_line(const char *line, struct amdgpu_asic_id *id)
+{
+ char *buf, *saveptr;
+ char *s_did;
+ char *s_rid;
+ char *s_name;
+ char *endptr;
+ int r = 0;
+
+ buf = strdup(line);
+ if (!buf)
+ return -ENOMEM;
+
+ /* ignore empty line and commented line */
+ if (strlen(line) == 0 || line[0] == '#') {
+ r = -EAGAIN;
+ goto out;
+ }
+
+ /* device id */
+ s_did = strtok_r(buf, ",", &saveptr);
+ if (!s_did) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ id->did = strtol(s_did, &endptr, 16);
+ if (*endptr) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ /* revision id */
+ s_rid = strtok_r(NULL, ",", &saveptr);
+ if (!s_rid) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ id->rid = strtol(s_rid, &endptr, 16);
+ if (*endptr) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ /* marketing name */
+ s_name = strtok_r(NULL, ",", &saveptr);
+ if (!s_name) {
+ r = -EINVAL;
+ goto out;
+ }
+ /* trim leading whitespaces or tabs */
+ while (isblank(*s_name))
+ s_name++;
+ if (strlen(s_name) == 0) {
+ r = -EINVAL;
+ goto out;
+ }
+
+ id->marketing_name = strdup(s_name);
+ if (id->marketing_name == NULL) {
+ r = -EINVAL;
+ goto out;
+ }
+
+out:
+ free(buf);
+
+ return r;
+}
+
+int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table)
+{
+ struct amdgpu_asic_id *asic_id_table;
+ struct amdgpu_asic_id *id;
+ FILE *fp;
+ char *line = NULL;
+ size_t len = 0;
+ ssize_t n;
+ int line_num = 1;
+ size_t table_size = 0;
+ size_t table_max_size = AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES;
+ int r = 0;
+
+ fp = fopen(AMDGPU_ASIC_ID_TABLE, "r");
+ if (!fp) {
+ fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE,
+ strerror(errno));
+ return -EINVAL;
+ }
+
+ asic_id_table = calloc(table_max_size + 1,
+ sizeof(struct amdgpu_asic_id));
+ if (!asic_id_table) {
+ r = -ENOMEM;
+ goto close;
+ }
+
+ /* 1st valid line is file version */
+ while ((n = getline(&line, &len, fp)) != -1) {
+ /* trim trailing newline */
+ if (line[n - 1] == '\n')
+ line[n - 1] = '\0';
+
+ /* ignore empty line and commented line */
+ if (strlen(line) == 0 || line[0] == '#') {
+ line_num++;
+ continue;
+ }
+
+ drmMsg("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line);
+ break;
+ }
+
+ while ((n = getline(&line, &len, fp)) != -1) {
+ if (table_size > table_max_size) {
+ /* double table size */
+ table_max_size *= 2;
+ id = realloc(asic_id_table, (table_max_size + 1) *
+ sizeof(struct amdgpu_asic_id));
+ if (!id) {
+ r = -ENOMEM;
+ goto free;
+ }
+ asic_id_table = id;
+ }
+
+ id = asic_id_table + table_size;
+
+ /* trim trailing newline */
+ if (line[n - 1] == '\n')
+ line[n - 1] = '\0';
+
+ r = parse_one_line(line, id);
+ if (r) {
+ if (r == -EAGAIN) {
+ line_num++;
+ continue;
+ }
+ fprintf(stderr, "Invalid format: %s: line %d: %s\n",
+ AMDGPU_ASIC_ID_TABLE, line_num, line);
+ goto free;
+ }
+
+ line_num++;
+ table_size++;
+ }
+
+ /* end of table */
+ id = asic_id_table + table_size;
+ memset(id, 0, sizeof(struct amdgpu_asic_id));
+
+ if (table_size != table_max_size) {
+ id = realloc(asic_id_table, (table_size + 1) *
+ sizeof(struct amdgpu_asic_id));
+ if (!id)
+ r = -ENOMEM;
+ else
+ asic_id_table = id;
+ }
+
+free:
+ free(line);
+
+ if (r && asic_id_table) {
+ while (table_size--) {
+ id = asic_id_table + table_size;
+ free(id->marketing_name);
+ }
+ free(asic_id_table);
+ asic_id_table = NULL;
+ }
+close:
+ fclose(fp);
+
+ *p_asic_id_table = asic_id_table;
+
+ return r;
+}
diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h
deleted file mode 100644
index 3e7d736b..00000000
--- a/amdgpu/amdgpu_asic_id.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright © 2016 Advanced Micro Devices, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef __AMDGPU_ASIC_ID_H__
-#define __AMDGPU_ASIC_ID_H__
-
-static struct amdgpu_asic_id_table_t {
- uint32_t did;
- uint32_t rid;
- const char *marketing_name;
-} const amdgpu_asic_id_table [] = {
- {0x6600, 0x0, "AMD Radeon HD 8600/8700M"},
- {0x6600, 0x81, "AMD Radeon R7 M370"},
- {0x6601, 0x0, "AMD Radeon HD 8500M/8700M"},
- {0x6604, 0x0, "AMD Radeon R7 M265 Series"},
- {0x6604, 0x81, "AMD Radeon R7 M350"},
- {0x6605, 0x0, "AMD Radeon R7 M260 Series"},
- {0x6605, 0x81, "AMD Radeon R7 M340"},
- {0x6606, 0x0, "AMD Radeon HD 8790M"},
- {0x6607, 0x0, "AMD Radeon HD8530M"},
- {0x6608, 0x0, "AMD FirePro W2100"},
- {0x6610, 0x0, "AMD Radeon HD 8600 Series"},
- {0x6610, 0x81, "AMD Radeon R7 350"},
- {0x6610, 0x83, "AMD Radeon R5 340"},
- {0x6611, 0x0, "AMD Radeon HD 8500 Series"},
- {0x6613, 0x0, "AMD Radeon HD 8500 series"},
- {0x6617, 0xC7, "AMD Radeon R7 240 Series"},
- {0x6640, 0x0, "AMD Radeon HD 8950"},
- {0x6640, 0x80, "AMD Radeon R9 M380"},
- {0x6646, 0x0, "AMD Radeon R9 M280X"},
- {0x6646, 0x80, "AMD Radeon R9 M470X"},
- {0x6647, 0x0, "AMD Radeon R9 M270X"},
- {0x6647, 0x80, "AMD Radeon R9 M380"},
- {0x6649, 0x0, "AMD FirePro W5100"},
- {0x6658, 0x0, "AMD Radeon R7 200 Series"},
- {0x665C, 0x0, "AMD Radeon HD 7700 Series"},
- {0x665D, 0x0, "AMD Radeon R7 200 Series"},
- {0x665F, 0x81, "AMD Radeon R7 300 Series"},
- {0x6660, 0x0, "AMD Radeon HD 8600M Series"},
- {0x6660, 0x81, "AMD Radeon R5 M335"},
- {0x6660, 0x83, "AMD Radeon R5 M330"},
- {0x6663, 0x0, "AMD Radeon HD 8500M Series"},
- {0x6663, 0x83, "AMD Radeon R5 M320"},
- {0x6664, 0x0, "AMD Radeon R5 M200 Series"},
- {0x6665, 0x0, "AMD Radeon R5 M200 Series"},
- {0x6665, 0x83, "AMD Radeon R5 M320"},
- {0x6667, 0x0, "AMD Radeon R5 M200 Series"},
- {0x666F, 0x0, "AMD Radeon HD 8500M"},
- {0x6780, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"},
- {0x678A, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"},
- {0x6798, 0x0, "AMD Radeon HD 7900 Series"},
- {0x679A, 0x0, "AMD Radeon HD 7900 Series"},
- {0x679B, 0x0, "AMD Radeon HD 7900 Series"},
- {0x679E, 0x0, "AMD Radeon HD 7800 Series"},
- {0x67A0, 0x0, "HAWAII XTGL (67A0)"},
- {0x67A1, 0x0, "HAWAII GL40 (67A1)"},
- {0x67B0, 0x0, "AMD Radeon R9 200 Series"},
- {0x67B0, 0x80, "AMD Radeon R9 390 Series"},
- {0x67B1, 0x0, "AMD Radeon R9 200 Series"},
- {0x67B1, 0x80, "AMD Radeon R9 390 Series"},
- {0x67B9, 0x0, "AMD Radeon R9 200 Series"},
- {0x67DF, 0xC4, "AMD Radeon RX 480 Graphics"},
- {0x67DF, 0xC5, "AMD Radeon RX 470 Graphics"},
- {0x67DF, 0xC7, "AMD Radeon RX 480 Graphics"},
- {0x67DF, 0xCF, "AMD Radeon RX 470 Graphics"},
- {0x67C4, 0x00, "AMD Radeon Pro WX 7100 Graphics"},
- {0x67C7, 0x00, "AMD Radeon Pro WX 5100 Graphics"},
- {0x67C0, 0x00, "AMD Radeon Pro WX 7100 Graphics"},
- {0x67E0, 0x00, "AMD Radeon Pro WX Series Graphics"},
- {0x67E3, 0x00, "AMD Radeon Pro WX 4100 Graphics"},
- {0x67E8, 0x00, "AMD Radeon Pro WX Series Graphics"},
- {0x67E8, 0x01, "AMD Radeon Pro WX Series Graphics"},
- {0x67E8, 0x80, "AMD Radeon E9260 Graphics"},
- {0x67EB, 0x00, "AMD Radeon Pro WX Series Graphics"},
- {0x67EF, 0xC0, "AMD Radeon RX Graphics"},
- {0x67EF, 0xC1, "AMD Radeon RX 460 Graphics"},
- {0x67EF, 0xC5, "AMD Radeon RX 460 Graphics"},
- {0x67EF, 0xC7, "AMD Radeon RX Graphics"},
- {0x67EF, 0xCF, "AMD Radeon RX 460 Graphics"},
- {0x67EF, 0xEF, "AMD Radeon RX Graphics"},
- {0x67FF, 0xC0, "AMD Radeon RX Graphics"},
- {0x67FF, 0xC1, "AMD Radeon RX Graphics"},
- {0x6800, 0x0, "AMD Radeon HD 7970M"},
- {0x6801, 0x0, "AMD Radeon(TM) HD8970M"},
- {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"},
- {0x6809, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"},
- {0x6810, 0x0, "AMD Radeon(TM) HD 8800 Series"},
- {0x6810, 0x81, "AMD Radeon R7 370 Series"},
- {0x6811, 0x0, "AMD Radeon(TM) HD8800 Series"},
- {0x6811, 0x81, "AMD Radeon R7 300 Series"},
- {0x6818, 0x0, "AMD Radeon HD 7800 Series"},
- {0x6819, 0x0, "AMD Radeon HD 7800 Series"},
- {0x6820, 0x0, "AMD Radeon HD 8800M Series"},
- {0x6820, 0x81, "AMD Radeon R9 M375"},
- {0x6820, 0x83, "AMD Radeon R9 M375X"},
- {0x6821, 0x0, "AMD Radeon HD 8800M Series"},
- {0x6821, 0x87, "AMD Radeon R7 M380"},
- {0x6821, 0x83, "AMD Radeon R9 M370X"},
- {0x6822, 0x0, "AMD Radeon E8860"},
- {0x6823, 0x0, "AMD Radeon HD 8800M Series"},
- {0x6825, 0x0, "AMD Radeon HD 7800M Series"},
- {0x6827, 0x0, "AMD Radeon HD 7800M Series"},
- {0x6828, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"},
- {0x682B, 0x0, "AMD Radeon HD 8800M Series"},
- {0x682B, 0x87, "AMD Radeon R9 M360"},
- {0x682C, 0x0, "AMD FirePro W4100"},
- {0x682D, 0x0, "AMD Radeon HD 7700M Series"},
- {0x682F, 0x0, "AMD Radeon HD 7700M Series"},
- {0x6835, 0x0, "AMD Radeon R7 Series / HD 9000 Series"},
- {0x6837, 0x0, "AMD Radeon HD7700 Series"},
- {0x683D, 0x0, "AMD Radeon HD 7700 Series"},
- {0x683F, 0x0, "AMD Radeon HD 7700 Series"},
- {0x6900, 0x0, "AMD Radeon R7 M260"},
- {0x6900, 0x81, "AMD Radeon R7 M360"},
- {0x6900, 0x83, "AMD Radeon R7 M340"},
- {0x6901, 0x0, "AMD Radeon R5 M255"},
- {0x6907, 0x0, "AMD Radeon R5 M255"},
- {0x6907, 0x87, "AMD Radeon R5 M315"},
- {0x6920, 0x0, "AMD Radeon R9 M395X"},
- {0x6920, 0x1, "AMD Radeon R9 M390X"},
- {0x6921, 0x0, "AMD Radeon R9 M295X"},
- {0x6929, 0x0, "AMD FirePro S7150"},
- {0x692B, 0x0, "AMD FirePro W7100"},
- {0x6938, 0x0, "AMD Radeon R9 200 Series"},
- {0x6938, 0xF0, "AMD Radeon R9 200 Series"},
- {0x6938, 0xF1, "AMD Radeon R9 380 Series"},
- {0x6939, 0xF0, "AMD Radeon R9 200 Series"},
- {0x6939, 0x0, "AMD Radeon R9 200 Series"},
- {0x6939, 0xF1, "AMD Radeon R9 380 Series"},
- {0x7300, 0xC8, "AMD Radeon R9 Fury Series"},
- {0x7300, 0xCB, "AMD Radeon R9 Fury Series"},
- {0x7300, 0xCA, "AMD Radeon R9 Fury Series"},
- {0x9874, 0xC4, "AMD Radeon R7 Graphics"},
- {0x9874, 0xC5, "AMD Radeon R6 Graphics"},
- {0x9874, 0xC6, "AMD Radeon R6 Graphics"},
- {0x9874, 0xC7, "AMD Radeon R5 Graphics"},
- {0x9874, 0x81, "AMD Radeon R6 Graphics"},
- {0x9874, 0x87, "AMD Radeon R5 Graphics"},
- {0x9874, 0x85, "AMD Radeon R6 Graphics"},
- {0x9874, 0x84, "AMD Radeon R7 Graphics"},
-
- {0x0000, 0x0, "\0"},
-};
-#endif
diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index f473d2da..9a238d97 100644
--- a/amdgpu/amdgpu_device.c
+++ b/amdgpu/amdgpu_device.c
@@ -44,7 +44,6 @@
#include "amdgpu_internal.h"
#include "util_hash_table.h"
#include "util_math.h"
-#include "amdgpu_asic_id.h"
#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
#define UINT_TO_PTR(x) ((void *)((intptr_t)(x)))
@@ -131,6 +130,7 @@ static int amdgpu_get_auth(int fd, int *auth)
static void amdgpu_device_free_internal(amdgpu_device_handle dev)
{
+ const struct amdgpu_asic_id *id;
amdgpu_vamgr_deinit(&dev->vamgr_32);
amdgpu_vamgr_deinit(&dev->vamgr);
util_hash_table_destroy(dev->bo_flink_names);
@@ -140,6 +140,12 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev)
close(dev->fd);
if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
close(dev->flink_fd);
+ if (dev->asic_ids) {
+ for (id = dev->asic_ids; id->did; id++)
+ free(id->marketing_name);
+
+ free(dev->asic_ids);
+ }
free(dev);
}
@@ -267,6 +273,12 @@ int amdgpu_device_initialize(int fd,
amdgpu_vamgr_init(&dev->vamgr_32, start, max,
dev->dev_info.virtual_address_alignment);
+ r = amdgpu_parse_asic_ids(&dev->asic_ids);
+ if (r) {
+ fprintf(stderr, "%s: Cannot parse ASIC IDs, 0x%x.",
+ __func__, r);
+ }
+
*major_version = dev->major_version;
*minor_version = dev->minor_version;
*device_handle = dev;
@@ -297,13 +309,15 @@ int amdgpu_device_deinitialize(amdgpu_device_handle dev)
const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
{
- const struct amdgpu_asic_id_table_t *t = amdgpu_asic_id_table;
+ const struct amdgpu_asic_id *id;
+
+ if (!dev->asic_ids)
+ return NULL;
- while (t->did) {
- if ((t->did == dev->info.asic_id) &&
- (t->rid == dev->info.pci_rev_id))
- return t->marketing_name;
- t++;
+ for (id = dev->asic_ids; id->did; id++) {
+ if ((id->did == dev->info.asic_id) &&
+ (id->rid == dev->info.pci_rev_id))
+ return id->marketing_name;
}
return NULL;
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index cf119a53..e68246bf 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -69,6 +69,12 @@ struct amdgpu_va {
struct amdgpu_bo_va_mgr *vamgr;
};
+struct amdgpu_asic_id {
+ uint32_t did;
+ uint32_t rid;
+ char *marketing_name;
+};
+
struct amdgpu_device {
atomic_t refcount;
int fd;
@@ -76,6 +82,8 @@ struct amdgpu_device {
unsigned major_version;
unsigned minor_version;
+ /** Lookup table of asic device id, revision id and marketing name */
+ struct amdgpu_asic_id *asic_ids;
/** List of buffer handles. Protected by bo_table_mutex. */
struct util_hash_table *bo_handles;
/** List of buffer GEM flink names. Protected by bo_table_mutex. */
@@ -149,6 +157,8 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
drm_private void
amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size);
+drm_private int amdgpu_parse_asic_ids(struct amdgpu_asic_id **asic_ids);
+
drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);
diff --git a/configure.ac b/configure.ac
index 1cfb8c27..aa9529cd 100644
--- a/configure.ac
+++ b/configure.ac
@@ -84,6 +84,9 @@ fi
pkgconfigdir=${libdir}/pkgconfig
AC_SUBST(pkgconfigdir)
+libdrmdatadir=${datadir}/libdrm
+AC_SUBST(libdrmdatadir)
+
AC_ARG_ENABLE([udev],
[AS_HELP_STRING([--enable-udev],
[Enable support for using udev instead of mknod (default: disabled)])],
@@ -527,6 +530,7 @@ fi
AC_SUBST(WARN_CFLAGS)
AC_CONFIG_FILES([
Makefile
+ data/Makefile
libkms/Makefile
libkms/libkms.pc
intel/Makefile
diff --git a/data/Makefile.am b/data/Makefile.am
new file mode 100644
index 00000000..eba915dd
--- /dev/null
+++ b/data/Makefile.am
@@ -0,0 +1,23 @@
+# Copyright © 2017 Advanced Micro Devices, Inc.
+# All Rights Reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# on the rights to use, copy, modify, merge, publish, distribute, sub
+# license, and/or sell copies of the Software, and to permit persons to whom
+# the Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+libdrmdatadir = @libdrmdatadir@
+dist_libdrmdata_DATA = amdgpu.ids
diff --git a/data/amdgpu.ids b/data/amdgpu.ids
new file mode 100644
index 00000000..0b98c3c3
--- /dev/null
+++ b/data/amdgpu.ids
@@ -0,0 +1,159 @@
+# List of AMDGPU IDs
+#
+# Syntax:
+# device_id, revision_id, product_name <-- single tab after comma
+
+1.0.0
+6600, 0, AMD Radeon HD 8600/8700M
+6600, 81, AMD Radeon (TM) R7 M370
+6601, 0, AMD Radeon (TM) HD 8500M/8700M
+6604, 0, AMD Radeon R7 M265 Series
+6604, 81, AMD Radeon (TM) R7 M350
+6605, 0, AMD Radeon R7 M260 Series
+6605, 81, AMD Radeon (TM) R7 M340
+6606, 0, AMD Radeon HD 8790M
+6607, 0, AMD Radeon (TM) HD8530M
+6608, 0, AMD FirePro W2100
+6610, 0, AMD Radeon HD 8600 Series
+6610, 81, AMD Radeon (TM) R7 350
+6610, 83, AMD Radeon (TM) R5 340
+6611, 0, AMD Radeon HD 8500 Series
+6613, 0, AMD Radeon HD 8500 series
+6617, C7, AMD Radeon R7 240 Series
+6640, 0, AMD Radeon HD 8950
+6640, 80, AMD Radeon (TM) R9 M380
+6646, 0, AMD Radeon R9 M280X
+6646, 80, AMD Radeon (TM) R9 M470X
+6647, 0, AMD Radeon R9 M270X
+6647, 80, AMD Radeon (TM) R9 M380
+6649, 0, AMD FirePro W5100
+6658, 0, AMD Radeon R7 200 Series
+665C, 0, AMD Radeon HD 7700 Series
+665D, 0, AMD Radeon R7 200 Series
+665F, 81, AMD Radeon (TM) R7 300 Series
+6660, 0, AMD Radeon HD 8600M Series
+6660, 81, AMD Radeon (TM) R5 M335
+6660, 83, AMD Radeon (TM) R5 M330
+6663, 0, AMD Radeon HD 8500M Series
+6663, 83, AMD Radeon (TM) R5 M320
+6664, 0, AMD Radeon R5 M200 Series
+6665, 0, AMD Radeon R5 M200 Series
+6665, 83, AMD Radeon (TM) R5 M320
+6667, 0, AMD Radeon R5 M200 Series
+666F, 0, AMD Radeon HD 8500M
+6780, 0, ATI FirePro V (FireGL V) Graphics Adapter
+678A, 0, ATI FirePro V (FireGL V) Graphics Adapter
+6798, 0, AMD Radeon HD 7900 Series
+679A, 0, AMD Radeon HD 7900 Series
+679B, 0, AMD Radeon HD 7900 Series
+679E, 0, AMD Radeon HD 7800 Series
+67A0, 0, AMD Radeon FirePro W9100
+67A1, 0, AMD Radeon FirePro W8100
+67B0, 0, AMD Radeon R9 200 Series
+67B0, 80, AMD Radeon (TM) R9 390 Series
+67B1, 0, AMD Radeon R9 200 Series
+67B1, 80, AMD Radeon (TM) R9 390 Series
+67B9, 0, AMD Radeon R9 200 Series
+67DF, C1, Radeon RX 580 Series
+67DF, C2, Radeon RX 570 Series
+67DF, C3, Radeon RX 580 Series
+67DF, C4, AMD Radeon (TM) RX 480 Graphics
+67DF, C5, AMD Radeon (TM) RX 470 Graphics
+67DF, C6, Radeon RX 570 Series
+67DF, C7, AMD Radeon (TM) RX 480 Graphics
+67DF, CF, AMD Radeon (TM) RX 470 Graphics
+67DF, E3, Radeon RX Series
+67DF, E7, Radeon RX 580 Series
+67DF, EF, Radeon RX 570 Series
+67C2, 01, AMD Radeon (TM) Pro V7350x2
+67C2, 02, AMD Radeon (TM) Pro V7300X
+67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics
+67C7, 00, AMD Radeon (TM) Pro WX 5100 Graphics
+67C0, 00, AMD Radeon (TM) Pro WX 7100 Graphics
+67D0, 01, AMD Radeon (TM) Pro V7350x2
+67D0, 02, AMD Radeon (TM) Pro V7300X
+67E0, 00, AMD Radeon (TM) Pro WX Series
+67E3, 00, AMD Radeon (TM) Pro WX 4100
+67E8, 00, AMD Radeon (TM) Pro WX Series
+67E8, 01, AMD Radeon (TM) Pro WX Series
+67E8, 80, AMD Radeon (TM) E9260 Graphics
+67EB, 00, AMD Radeon (TM) Pro V5300X
+67EF, C0, AMD Radeon (TM) RX Graphics
+67EF, C1, AMD Radeon (TM) RX 460 Graphics
+67EF, C3, Radeon RX Series
+67EF, C5, AMD Radeon (TM) RX 460 Graphics
+67EF, C7, AMD Radeon (TM) RX Graphics
+67EF, CF, AMD Radeon (TM) RX 460 Graphics
+67EF, E1, Radeon RX Series
+67EF, E3, Radeon RX Series
+67EF, E7, Radeon RX Series
+67EF, EF, AMD Radeon (TM) RX Graphics
+67EF, FF, Radeon RX Series
+67FF, C0, AMD Radeon (TM) RX Graphics
+67FF, C1, AMD Radeon (TM) RX Graphics
+67FF, FF, Radeon RX 550 Series
+6800, 0, AMD Radeon HD 7970M
+6801, 0, AMD Radeon(TM) HD8970M
+6808, 0, ATI FirePro V(FireGL V) Graphics Adapter
+6809, 0, ATI FirePro V(FireGL V) Graphics Adapter
+6810, 0, AMD Radeon(TM) HD 8800 Series
+6810, 81, AMD Radeon (TM) R7 370 Series
+6811, 0, AMD Radeon(TM) HD8800 Series
+6811, 81, AMD Radeon (TM) R7 300 Series
+6818, 0, AMD Radeon HD 7800 Series
+6819, 0, AMD Radeon HD 7800 Series
+6820, 0, AMD Radeon HD 8800M Series
+6820, 81, AMD Radeon (TM) R9 M375
+6820, 83, AMD Radeon (TM) R9 M375X
+6821, 0, AMD Radeon HD 8800M Series
+6821, 87, AMD Radeon (TM) R7 M380
+6821, 83, AMD Radeon R9 (TM) M370X
+6822, 0, AMD Radeon E8860
+6823, 0, AMD Radeon HD 8800M Series
+6825, 0, AMD Radeon HD 7800M Series
+6827, 0, AMD Radeon HD 7800M Series
+6828, 0, ATI FirePro V(FireGL V) Graphics Adapter
+682B, 0, AMD Radeon HD 8800M Series
+682B, 87, AMD Radeon (TM) R9 M360
+682C, 0, AMD FirePro W4100
+682D, 0, AMD Radeon HD 7700M Series
+682F, 0, AMD Radeon HD 7700M Series
+6835, 0, AMD Radeon R7 Series / HD 9000 Series
+6837, 0, AMD Radeon HD7700 Series
+683D, 0, AMD Radeon HD 7700 Series
+683F, 0, AMD Radeon HD 7700 Series
+6900, 0, AMD Radeon R7 M260
+6900, 81, AMD Radeon (TM) R7 M360
+6900, 83, AMD Radeon (TM) R7 M340
+6901, 0, AMD Radeon R5 M255
+6907, 0, AMD Radeon R5 M255
+6907, 87, AMD Radeon (TM) R5 M315
+6920, 0, AMD RADEON R9 M395X
+6920, 1, AMD RADEON R9 M390X
+6921, 0, AMD Radeon R9 M295X
+6929, 0, AMD FirePro S7150
+692B, 0, AMD FirePro W7100
+6938, 0, AMD Radeon R9 200 Series
+6938, F0, AMD Radeon R9 200 Series
+6938, F1, AMD Radeon (TM) R9 380 Series
+6939, F0, AMD Radeon R9 200 Series
+6939, 0, AMD Radeon R9 200 Series
+6939, F1, AMD Radeon (TM) R9 380 Series
+6985, 00, AMD Radeon Pro WX3100
+6995, 00, AMD Radeon Pro WX2100
+699F, C0, Radeon 500 Series
+699F, C3, Radeon 500 Series
+699F, C7, Radeon RX 550 Series
+7300, C1, AMD FirePro (TM) S9300 x2
+7300, C8, AMD Radeon (TM) R9 Fury Series
+7300, C9, Radeon (TM) Pro Duo
+7300, CB, AMD Radeon (TM) R9 Fury Series
+7300, CA, AMD Radeon (TM) R9 Fury Series
+9874, C4, AMD Radeon R7 Graphics
+9874, C5, AMD Radeon R6 Graphics
+9874, C6, AMD Radeon R6 Graphics
+9874, C7, AMD Radeon R5 Graphics
+9874, 81, AMD Radeon R6 Graphics
+9874, 87, AMD Radeon R5 Graphics
+9874, 85, AMD Radeon R6 Graphics
+9874, 84, AMD Radeon R7 Graphics
|
|
From: <da...@ke...> - 2017-06-22 09:49:28
|
include/drm/drm_fourcc.h | 23 ++++++++++++++++++++++-
include/drm/vc4_drm.h | 22 +++++++++++++++++++---
2 files changed, 41 insertions(+), 4 deletions(-)
New commits:
commit b9549c954e190010a79e6691983b6ae16eac83d5
Author: Eric Anholt <er...@an...>
Date: Wed Jun 21 10:23:23 2017 -0700
headers: Update drm_fourcc and vc4_drm.h with new VC4 tiling UAPI.
Taken from make headers_install of drm-misc-next
(34c8ea400ff6383b028f63df2453914163afc07c)
Reviewed-by: Daniel Stone <da...@co...>
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 55e30104..7586c46f 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -182,6 +182,7 @@ extern "C" {
#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
+#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
/* add more to the end as needed */
#define fourcc_mod_code(vendor, val) \
@@ -306,7 +307,6 @@ extern "C" {
*/
#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
-
/* NVIDIA Tegra frame buffer modifiers */
/*
@@ -351,6 +351,27 @@ extern "C" {
*/
#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
+/*
+ * Broadcom VC4 "T" format
+ *
+ * This is the primary layout that the V3D GPU can texture from (it
+ * can't do linear). The T format has:
+ *
+ * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
+ * pixels at 32 bit depth.
+ *
+ * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
+ * 16x16 pixels).
+ *
+ * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
+ * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
+ * they're (TR, BR, BL, TL), where bottom left is start of memory.
+ *
+ * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
+ * tiles) or right-to-left (odd rows of 4k tiles).
+ */
+#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
+
#if defined(__cplusplus)
}
#endif
diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h
index 319881d8..6ac4c5c0 100644
--- a/include/drm/vc4_drm.h
+++ b/include/drm/vc4_drm.h
@@ -21,8 +21,8 @@
* IN THE SOFTWARE.
*/
-#ifndef _VC4_DRM_H_
-#define _VC4_DRM_H_
+#ifndef _UAPI_VC4_DRM_H_
+#define _UAPI_VC4_DRM_H_
#include "drm.h"
@@ -38,6 +38,8 @@ extern "C" {
#define DRM_VC4_CREATE_SHADER_BO 0x05
#define DRM_VC4_GET_HANG_STATE 0x06
#define DRM_VC4_GET_PARAM 0x07
+#define DRM_VC4_SET_TILING 0x08
+#define DRM_VC4_GET_TILING 0x09
#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
@@ -47,6 +49,8 @@ extern "C" {
#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
+#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
+#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
struct drm_vc4_submit_rcl_surface {
__u32 hindex; /* Handle index, or ~0 if not present. */
@@ -295,8 +299,20 @@ struct drm_vc4_get_param {
__u64 value;
};
+struct drm_vc4_get_tiling {
+ __u32 handle;
+ __u32 flags;
+ __u64 modifier;
+};
+
+struct drm_vc4_set_tiling {
+ __u32 handle;
+ __u32 flags;
+ __u64 modifier;
+};
+
#if defined(__cplusplus)
}
#endif
-#endif /* _VC4_DRM_H_ */
+#endif /* _UAPI_VC4_DRM_H_ */
|
|
From: <ai...@ke...> - 2017-06-27 03:09:08
|
include/drm/amdgpu_drm.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 53 insertions(+), 1 deletion(-)
New commits:
commit 92b5b308ca2fec356dd29bb2f27d88a5aff61798
Author: Dave Airlie <ai...@re...>
Date: Tue Jun 27 12:56:25 2017 +1000
amdgpu: sync amdgpu_drm with kernel.
This syncs the amdgpu_drm header with my drm-next branch as of
6d61e70ccc21606ffb8a0a03bd3aba24f659502b.
It brings over the VM and semaphore API changes.
Generated using make headers_install.
Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2.
Reviewed-by: Michel Dänzer <mic...@am...>
Signed-off-by: Dave Airlie <ai...@re...>
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 8cfe68c5..d9aa4a33 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -51,6 +51,7 @@ extern "C" {
#define DRM_AMDGPU_GEM_OP 0x10
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
+#define DRM_AMDGPU_VM 0x13
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -65,6 +66,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
+#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -190,6 +192,26 @@ union drm_amdgpu_ctx {
union drm_amdgpu_ctx_out out;
};
+/* vm ioctl */
+#define AMDGPU_VM_OP_RESERVE_VMID 1
+#define AMDGPU_VM_OP_UNRESERVE_VMID 2
+
+struct drm_amdgpu_vm_in {
+ /** AMDGPU_VM_OP_* */
+ __u32 op;
+ __u32 flags;
+};
+
+struct drm_amdgpu_vm_out {
+ /** For future use, no flags defined so far */
+ __u64 flags;
+};
+
+union drm_amdgpu_vm {
+ struct drm_amdgpu_vm_in in;
+ struct drm_amdgpu_vm_out out;
+};
+
/*
* This is not a reliable API and you should expect it to fail for any
* number of reasons and have fallback path that do not use userptr to
@@ -295,7 +317,10 @@ union drm_amdgpu_gem_wait_idle {
};
struct drm_amdgpu_wait_cs_in {
- /** Command submission handle */
+ /* Command submission handle
+ * handle equals 0 means none to wait for
+ * handle equals ~0ull means wait for the latest sequence number
+ */
__u64 handle;
/** Absolute timeout to wait */
__u64 timeout;
@@ -415,6 +440,8 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_IB 0x01
#define AMDGPU_CHUNK_ID_FENCE 0x02
#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
+#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
+#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
@@ -482,6 +509,10 @@ struct drm_amdgpu_cs_chunk_fence {
__u32 offset;
};
+struct drm_amdgpu_cs_chunk_sem {
+ __u32 handle;
+};
+
struct drm_amdgpu_cs_chunk_data {
union {
struct drm_amdgpu_cs_chunk_ib ib_data;
@@ -578,6 +609,8 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_SENSOR_VDDNB 0x6
/* Subquery id: Query graphics voltage */
#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
+/* Number of VRAM page faults on CPU access. */
+#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -766,6 +799,25 @@ struct drm_amdgpu_info_device {
__u64 cntl_sb_buf_gpu_addr;
/* NGG Parameter Cache */
__u64 param_buf_gpu_addr;
+ __u32 prim_buf_size;
+ __u32 pos_buf_size;
+ __u32 cntl_sb_buf_size;
+ __u32 param_buf_size;
+ /* wavefront size*/
+ __u32 wave_front_size;
+ /* shader visible vgprs*/
+ __u32 num_shader_visible_vgprs;
+ /* CU per shader array*/
+ __u32 num_cu_per_sh;
+ /* number of tcc blocks*/
+ __u32 num_tcc_blocks;
+ /* gs vgt table depth*/
+ __u32 gs_vgt_table_depth;
+ /* gs primitive buffer depth*/
+ __u32 gs_prim_buffer_depth;
+ /* max gs wavefront per vgt*/
+ __u32 max_gs_waves_per_vgt;
+ __u32 _pad1;
};
struct drm_amdgpu_info_hw_ip {
|
|
From: <vi...@ke...> - 2017-07-05 22:32:27
|
intel/intel_chipset.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
New commits:
commit 68da7812fc8f859afa7f202f832c72a35c8d4a1d
Author: Rodrigo Vivi <rod...@in...>
Date: Fri Jun 30 14:24:55 2017 -0700
intel/intel_chipset: Move IS_9XX below IS_GEN10.
No functional change. Just organizing the code
so it gets clear for future platforms.
Paulo deserves credits becuase he was the one
that just noticed this IS_9XX was in the wrong position
after CNL patches got introduced.
Cc: Paulo Zanoni <pau...@in...>
Signed-off-by: Rodrigo Vivi <rod...@in...>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 770d21f0..3ff59ada 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -499,15 +499,6 @@
IS_GEMINILAKE(devid) || \
IS_COFFEELAKE(devid))
-#define IS_9XX(dev) (IS_GEN3(dev) || \
- IS_GEN4(dev) || \
- IS_GEN5(dev) || \
- IS_GEN6(dev) || \
- IS_GEN7(dev) || \
- IS_GEN8(dev) || \
- IS_GEN9(dev) || \
- IS_GEN10(dev))
-
#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
@@ -525,4 +516,13 @@
#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
+#define IS_9XX(dev) (IS_GEN3(dev) || \
+ IS_GEN4(dev) || \
+ IS_GEN5(dev) || \
+ IS_GEN6(dev) || \
+ IS_GEN7(dev) || \
+ IS_GEN8(dev) || \
+ IS_GEN9(dev) || \
+ IS_GEN10(dev))
+
#endif /* _INTEL_CHIPSET_H */
|
|
From: <aus...@ke...> - 2017-07-06 18:48:27
|
etnaviv/etnaviv_cmd_stream.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
New commits:
commit 2393acd14487db0b7bedcf5af7b3710066809cbc
Author: Christian Gmeiner <chr...@gm...>
Date: Fri Jun 9 12:27:34 2017 +0200
etnaviv: submit full struct drm_etnaviv_gem_submit
It is safe to submit the full struct even on older kernels as such
kernels do not process the full struct. Without this change it
becomes quite challenging to extned the submit struct.
Freedreno has no special treatment too. See git commits
- freedreno: sync uapi header
- freedreno: add fence fd support
Signed-off-by: Christian Gmeiner <chr...@gm...>
Reviewed-by: Philipp Zabel <p....@pe...>
Tested-by: Philipp Zabel <p....@pe...>
diff --git a/etnaviv/etnaviv_cmd_stream.c b/etnaviv/etnaviv_cmd_stream.c
index 3c7b0ed6..8d0e8135 100644
--- a/etnaviv/etnaviv_cmd_stream.c
+++ b/etnaviv/etnaviv_cmd_stream.c
@@ -203,14 +203,8 @@ static void flush(struct etna_cmd_stream *stream, int in_fence_fd,
if (out_fence_fd)
req.flags |= ETNA_SUBMIT_FENCE_FD_OUT;
- /*
- * Pass the complete submit structure only if flags are set. Otherwise,
- * only pass the fields up to, but not including the flags field for
- * backwards compatiblity with older kernels.
- */
ret = drmCommandWriteRead(gpu->dev->fd, DRM_ETNAVIV_GEM_SUBMIT,
- &req, req.flags ? sizeof(req) :
- offsetof(struct drm_etnaviv_gem_submit, flags));
+ &req, sizeof(req));
if (ret)
ERROR_MSG("submit failed: %d (%s)", ret, strerror(errno));
|
|
From: <eri...@ke...> - 2017-07-07 12:34:40
|
xf86drm.c | 2 --
1 file changed, 2 deletions(-)
New commits:
commit ac214017904b31bc5f80f802d748d5f4f3149d22
Author: coypu <co...@sd...>
Date: Fri Jun 30 03:56:55 2017 +0000
Remove redundant memclear
drmMalloc will zero out the memory for us
Reviewed-by: Eric Engestrom <eri...@im...>
diff --git a/xf86drm.c b/xf86drm.c
index 2ac3f265..879f85b6 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -866,8 +866,6 @@ drmVersionPtr drmGetVersion(int fd)
drmVersionPtr retval;
drm_version_t *version = drmMalloc(sizeof(*version));
- memclear(*version);
-
if (drmIoctl(fd, DRM_IOCTL_VERSION, version)) {
drmFreeKernelVersion(version);
return NULL;
|
|
From: <ai...@ke...> - 2017-07-18 23:41:16
|
amdgpu/amdgpu-symbol-check | 7 +++++++
1 file changed, 7 insertions(+)
New commits:
commit e12af382b5c59f531fddd6e5541f59474ba29ef1
Author: Dave Airlie <ai...@re...>
Date: Wed Jul 19 00:40:38 2017 +0100
amdgpu: add new symbols to tests.
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 81ef9b4e..c5b85b52 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -25,14 +25,21 @@ amdgpu_bo_va_op
amdgpu_bo_va_op_raw
amdgpu_bo_wait_for_idle
amdgpu_create_bo_from_user_mem
+amdgpu_cs_chunk_fence_info_to_data
+amdgpu_cs_chunk_fence_to_dep
amdgpu_cs_create_semaphore
+amdgpu_cs_create_syncobj
amdgpu_cs_ctx_create
amdgpu_cs_ctx_free
amdgpu_cs_destroy_semaphore
+amdgpu_cs_destroy_syncobj
+amdgpu_cs_export_syncobj
+amdgpu_cs_import_syncobj
amdgpu_cs_query_fence_status
amdgpu_cs_query_reset_state
amdgpu_cs_signal_semaphore
amdgpu_cs_submit
+amdgpu_cs_submit_raw
amdgpu_cs_wait_fences
amdgpu_cs_wait_semaphore
amdgpu_device_deinitialize
|
|
From: <ly...@ke...> - 2017-07-19 08:50:22
|
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit 23e234a3503f51b9d9c585123d33b936f522808d
Author: Lucas Stach <l....@pe...>
Date: Wed Jul 19 10:49:34 2017 +0200
configure.ac: bump version for release
Signed-off-by: Lucas Stach <l....@pe...>
diff --git a/configure.ac b/configure.ac
index aa9529cd..5a7b1f8a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.81],
+ [2.4.82],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
|
|
From: <eri...@ke...> - 2017-08-01 17:29:58
|
radeon/radeon_surface.c | 1 +
1 file changed, 1 insertion(+)
New commits:
commit 053ad3848786bf40a8131a2069d0fae259222c4f
Author: Eric Engestrom <er...@en...>
Date: Sun Jul 30 21:34:16 2017 +0100
radeon: add fallthrough annotation
GCC 7 started warning when a switch case has neither a `break` nor
a "fallthrough" comment.
Let's be explicit that we meant to fall through here.
Signed-off-by: Eric Engestrom <er...@en...>
Reviewed-by: Michel Dänzer <mic...@am...>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 965be24c..04df77d6 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -2503,6 +2503,7 @@ static int radeon_surface_sanity(struct radeon_surface_manager *surf_man,
if (surf->npix_y > 1) {
return -EINVAL;
}
+ /* fallthrough */
case RADEON_SURF_TYPE_2D:
if (surf->npix_z > 1) {
return -EINVAL;
|
|
From: <jv...@ke...> - 2017-08-02 15:24:37
|
data/amdgpu.ids | 1 +
1 file changed, 1 insertion(+)
New commits:
commit 0167e6836e91947418fec36c3b4b396760d0f345
Author: Jan Vesely <jan...@ru...>
Date: Fri Jul 28 01:46:45 2017 -0400
amdgpu: Add FX-9800P Bristol Ridge iGPU id
Signed-off-by: Jan Vesely <jan...@ru...>
Reviewed-by: Michel Dänzer <mic...@am...>
diff --git a/data/amdgpu.ids b/data/amdgpu.ids
index 0b98c3c3..f6c65dd9 100644
--- a/data/amdgpu.ids
+++ b/data/amdgpu.ids
@@ -153,6 +153,7 @@
9874, C5, AMD Radeon R6 Graphics
9874, C6, AMD Radeon R6 Graphics
9874, C7, AMD Radeon R5 Graphics
+9874, C8, AMD Radeon R7 Graphics
9874, 81, AMD Radeon R6 Graphics
9874, 87, AMD Radeon R5 Graphics
9874, 85, AMD Radeon R6 Graphics
|
|
From: <ag...@ke...> - 2017-08-07 19:46:40
|
amdgpu/amdgpu_bo.c | 1 +
1 file changed, 1 insertion(+)
New commits:
commit 4d244155945f5531b4d9735bbe73c887aac81070
Author: Monk Liu <mon...@am...>
Date: Mon Aug 7 22:35:11 2017 +0800
amdgpu: fix missing mutex unlock before return
Reviewed-by: Christian König <chr...@am...>
Signed-off-by: Monk Liu <mon...@am...>
Signed-off-by: Alex Deucher <ale...@am...>
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 5ac456be..d2725da8 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -302,6 +302,7 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle);
if (r) {
+ pthread_mutex_unlock(&dev->bo_table_mutex);
return r;
}
|
|
From: <jek...@ke...> - 2017-08-15 14:52:10
|
include/drm/drm_fourcc.h | 31 +++++++++++++++++++++++++++++
include/drm/drm_mode.h | 50 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 81 insertions(+)
New commits:
commit 7ec689a5406a4c5f468e126007c5aa9d72dd7f59
Author: Jason Ekstrand <jas...@in...>
Date: Mon Aug 14 16:12:19 2017 -0700
drm: Pull new modifier uapi into drm_fourcc and drm_mode
Reviewed-by: Daniel Stone <da...@co...>
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 7586c46f..3ad838d3 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -185,6 +185,8 @@ extern "C" {
#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
/* add more to the end as needed */
+#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
+
#define fourcc_mod_code(vendor, val) \
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
@@ -197,6 +199,15 @@ extern "C" {
*/
/*
+ * Invalid Modifier
+ *
+ * This modifier can be used as a sentinel to terminate the format modifiers
+ * list, or to initialize a variable with an invalid modifier. It might also be
+ * used to report an error back to userspace for certain APIs.
+ */
+#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
+
+/*
* Linear Layout
*
* Just plain linear layout. Note that this is different from no specifying any
@@ -253,6 +264,26 @@ extern "C" {
#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
/*
+ * Intel color control surface (CCS) for render compression
+ *
+ * The framebuffer format must be one of the 8:8:8:8 RGB formats.
+ * The main surface will be plane index 0 and must be Y/Yf-tiled,
+ * the CCS will be plane index 1.
+ *
+ * Each CCS tile matches a 1024x512 pixel area of the main surface.
+ * To match certain aspects of the 3D hardware the CCS is
+ * considered to be made up of normal 128Bx32 Y tiles, Thus
+ * the CCS pitch must be specified in multiples of 128 bytes.
+ *
+ * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
+ * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
+ * But that fact is not relevant unless the memory is accessed
+ * directly.
+ */
+#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
+#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+
+/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
* Macroblocks are laid in a Z-shape, and each pixel data is following the
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index 70571af6..08077978 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -657,6 +657,56 @@ struct drm_mode_atomic {
__u64 user_data;
};
+struct drm_format_modifier_blob {
+#define FORMAT_BLOB_CURRENT 1
+ /* Version of this blob format */
+ __u32 version;
+
+ /* Flags */
+ __u32 flags;
+
+ /* Number of fourcc formats supported */
+ __u32 count_formats;
+
+ /* Where in this blob the formats exist (in bytes) */
+ __u32 formats_offset;
+
+ /* Number of drm_format_modifiers */
+ __u32 count_modifiers;
+
+ /* Where in this blob the modifiers exist (in bytes) */
+ __u32 modifiers_offset;
+
+ /* u32 formats[] */
+ /* struct drm_format_modifier modifiers[] */
+};
+
+struct drm_format_modifier {
+ /* Bitmask of formats in get_plane format list this info applies to. The
+ * offset allows a sliding window of which 64 formats (bits).
+ *
+ * Some examples:
+ * In today's world with < 65 formats, and formats 0, and 2 are
+ * supported
+ * 0x0000000000000005
+ * ^-offset = 0, formats = 5
+ *
+ * If the number formats grew to 128, and formats 98-102 are
+ * supported with the modifier:
+ *
+ * 0x0000003c00000000 0000000000000000
+ * ^
+ * |__offset = 64, formats = 0x3c00000000
+ *
+ */
+ __u64 formats;
+ __u32 offset;
+ __u32 pad;
+
+ /* The modifier that applies to the >get_plane format list bitmask. */
+ __u64 modifier;
+};
+
/**
* Create a new 'blob' data property, copying length bytes from data pointer,
* and returning new blob ID.
|
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