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From: <ag...@ke...> - 2017-11-30 03:15:55
|
amdgpu/amdgpu.h | 15 +++++++++++++++
amdgpu/amdgpu_cs.c | 10 ++++++++++
2 files changed, 25 insertions(+)
New commits:
commit 1749d56ea00f350a74f662bdad82bcafa19889da
Author: David Mao <dav...@am...>
Date: Tue Nov 28 11:22:26 2017 +0800
amdgpu: Adding amdgpu_cs_create_syncobj2 to create syncobj as signaled initially
Signed-off-by: David Mao <dav...@am...>
Reviewed-by: Christian König <chr...@am...>
Signed-off-by: Alex Deucher <ale...@am...>
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index df85a24c..c95cb03c 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1344,6 +1344,21 @@ const char *amdgpu_get_marketing_name(amdgpu_device_handle dev);
/**
* Create kernel sync object
*
+ * \param dev - \c [in] device handle
+ * \param flags - \c [in] flags that affect creation
+ * \param syncobj - \c [out] sync object handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
+ uint32_t flags,
+ uint32_t *syncobj);
+
+/**
+ * Create kernel sync object
+ *
* \param dev - \c [in] device handle
* \param syncobj - \c [out] sync object handle
*
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index b9fc01e7..9e157a84 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -606,6 +606,16 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
return amdgpu_cs_unreference_sem(sem);
}
+int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
+ uint32_t flags,
+ uint32_t *handle)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjCreate(dev->fd, flags, handle);
+}
+
int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
uint32_t *handle)
{
|
|
From: <da...@ke...> - 2017-11-30 14:53:33
|
amdgpu/amdgpu-symbol-check | 1 +
1 file changed, 1 insertion(+)
New commits:
commit f71e95108de9a414226b0421ae2af99902ea28a5
Author: Michel Dänzer <mic...@am...>
Date: Thu Nov 30 15:52:50 2017 +0100
amdgpu: Add amdgpu_cs_create_syncobj2 to amdgpu-symbol-check
Fixes make check. Trivial.
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index d476038b..59db3cfe 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -29,6 +29,7 @@ amdgpu_cs_chunk_fence_info_to_data
amdgpu_cs_chunk_fence_to_dep
amdgpu_cs_create_semaphore
amdgpu_cs_create_syncobj
+amdgpu_cs_create_syncobj2
amdgpu_cs_ctx_create
amdgpu_cs_ctx_create2
amdgpu_cs_ctx_free
|
|
From: <agr...@ke...> - 2017-11-30 19:56:42
|
tests/amdgpu/amdgpu_test.c | 18 +++
tests/amdgpu/basic_tests.c | 264 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 282 insertions(+)
New commits:
commit bc21168fa924d3fc4a000492e861f50a1a135b25
Author: Andrey Grodzovsky <and...@am...>
Date: Fri Nov 24 15:19:09 2017 -0500
amdgpu: Add explicit dependency test.
The test is as following:
1) Create context A & B
2) Send a command submission using context A which fires up a compute shader.
3) The shader wait a bit and then write a value to a memory location.
4) Send a command submission using context B which writes another value to the same memory location, but having an explicit dependency on the first command submission.
5) Wait with the CPU for both submissions to finish and inspect the written value.
Test passes if the value seen in the memory location after both submissions is from command B.
Signed-off-by: Andrey Grodzovsky <and...@am...>
Acked-by: Christian König <chr...@am...>
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 50da17ca..8fa3399a 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -49,6 +49,7 @@
#include "CUnit/Basic.h"
#include "amdgpu_test.h"
+#include "amdgpu_internal.h"
/* Test suit names */
#define BASIC_TESTS_STR "Basic Tests"
@@ -401,9 +402,20 @@ static int amdgpu_find_device(uint8_t bus, uint16_t dev)
static void amdgpu_disable_suits()
{
+ amdgpu_device_handle device_handle;
+ uint32_t major_version, minor_version, family_id;
int i;
int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]);
+ if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+ &minor_version, &device_handle))
+ return;
+
+ family_id = device_handle->info.family_id;
+
+ if (amdgpu_device_deinitialize(device_handle))
+ return;
+
/* Set active status for suits based on their policies */
for (i = 0; i < size; ++i)
if (amdgpu_set_suite_active(suites_active_stat[i].pName,
@@ -420,6 +432,12 @@ static void amdgpu_disable_suits()
if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
+
+
+ /* This test was ran on GFX8 and GFX9 only */
+ if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV)
+ if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
}
/* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index e7f48e39..a78cf521 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -50,6 +50,7 @@ static void amdgpu_command_submission_multi_fence(void);
static void amdgpu_command_submission_sdma(void);
static void amdgpu_userptr_test(void);
static void amdgpu_semaphore_test(void);
+static void amdgpu_sync_dependency_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -63,6 +64,7 @@ CU_TestInfo basic_tests[] = {
{ "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence },
{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
{ "SW semaphore Test", amdgpu_semaphore_test },
+ { "Sync dependency Test", amdgpu_sync_dependency_test },
CU_TEST_INFO_NULL,
};
#define BUFFER_SIZE (8 * 1024)
@@ -226,6 +228,60 @@ CU_TestInfo basic_tests[] = {
*/
# define PACKET3_DMA_DATA_SI_CP_SYNC (1 << 31)
+
+#define PKT3_CONTEXT_CONTROL 0x28
+#define CONTEXT_CONTROL_LOAD_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
+#define CONTEXT_CONTROL_LOAD_CE_RAM(x) (((unsigned)(x) & 0x1) << 28)
+#define CONTEXT_CONTROL_SHADOW_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
+
+#define PKT3_CLEAR_STATE 0x12
+
+#define PKT3_SET_SH_REG 0x76
+#define PACKET3_SET_SH_REG_START 0x00002c00
+
+#define PACKET3_DISPATCH_DIRECT 0x15
+
+
+/* gfx 8 */
+#define mmCOMPUTE_PGM_LO 0x2e0c
+#define mmCOMPUTE_PGM_RSRC1 0x2e12
+#define mmCOMPUTE_TMPRING_SIZE 0x2e18
+#define mmCOMPUTE_USER_DATA_0 0x2e40
+#define mmCOMPUTE_USER_DATA_1 0x2e41
+#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15
+#define mmCOMPUTE_NUM_THREAD_X 0x2e07
+
+
+
+#define SWAP_32(num) ((num>>24)&0xff) | \
+ ((num<<8)&0xff0000) | \
+ ((num>>8)&0xff00) | \
+ ((num<<24)&0xff000000)
+
+
+/* Shader code
+ * void main()
+{
+
+ float x = some_input;
+ for (unsigned i = 0; i < 1000000; i++)
+ x = sin(x);
+
+ u[0] = 42u;
+}
+*/
+
+static uint32_t shader_bin[] = {
+ SWAP_32(0x800082be), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0x040085bf),
+ SWAP_32(0x02810281), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0xfcff84bf),
+ SWAP_32(0xff0083be), SWAP_32(0x00f00000), SWAP_32(0xc10082be), SWAP_32(0xaa02007e),
+ SWAP_32(0x000070e0), SWAP_32(0x00000080), SWAP_32(0x000081bf)
+};
+
+#define CODE_OFFSET 512
+#define DATA_OFFSET 1024
+
+
int suite_basic_tests_init(void)
{
struct amdgpu_gpu_info gpu_info = {0};
@@ -1386,3 +1442,211 @@ static void amdgpu_userptr_test(void)
wait(NULL);
}
+
+static void amdgpu_sync_dependency_test(void)
+{
+ amdgpu_context_handle context_handle[2];
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct amdgpu_cs_request ibs_request;
+ struct amdgpu_cs_ib_info ib_info;
+ struct amdgpu_cs_fence fence_status;
+ uint32_t expired;
+ int i, j, r, instance;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ static uint32_t *ptr;
+ uint64_t seq_no;
+
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle[0]);
+ CU_ASSERT_EQUAL(r, 0);
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle[1]);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 8192, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+ &bo_list);
+ CU_ASSERT_EQUAL(r, 0);
+
+ ptr = ib_result_cpu;
+ i = 0;
+
+ memcpy(ptr + CODE_OFFSET , shader_bin, sizeof(shader_bin));
+
+ /* Dispatch minimal init config and verify it's executed */
+ ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
+ ptr[i++] = 0x80000000;
+ ptr[i++] = 0x80000000;
+
+ ptr[i++] = PACKET3(PKT3_CLEAR_STATE, 0);
+ ptr[i++] = 0x80000000;
+
+
+ /* Program compute regs */
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
+ ptr[i++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
+ ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 8;
+ ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 40;
+
+
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
+ ptr[i++] = mmCOMPUTE_PGM_RSRC1 - PACKET3_SET_SH_REG_START;
+ /*
+ * 002c0040 COMPUTE_PGM_RSRC1 <- VGPRS = 0
+ SGPRS = 1
+ PRIORITY = 0
+ FLOAT_MODE = 192 (0xc0)
+ PRIV = 0
+ DX10_CLAMP = 1
+ DEBUG_MODE = 0
+ IEEE_MODE = 0
+ BULKY = 0
+ CDBG_USER = 0
+ *
+ */
+ ptr[i++] = 0x002c0040;
+
+
+ /*
+ * 00000010 COMPUTE_PGM_RSRC2 <- SCRATCH_EN = 0
+ USER_SGPR = 8
+ TRAP_PRESENT = 0
+ TGID_X_EN = 0
+ TGID_Y_EN = 0
+ TGID_Z_EN = 0
+ TG_SIZE_EN = 0
+ TIDIG_COMP_CNT = 0
+ EXCP_EN_MSB = 0
+ LDS_SIZE = 0
+ EXCP_EN = 0
+ *
+ */
+ ptr[i++] = 0x00000010;
+
+
+/*
+ * 00000100 COMPUTE_TMPRING_SIZE <- WAVES = 256 (0x100)
+ WAVESIZE = 0
+ *
+ */
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
+ ptr[i++] = mmCOMPUTE_TMPRING_SIZE - PACKET3_SET_SH_REG_START;
+ ptr[i++] = 0x00000100;
+
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
+ ptr[i++] = mmCOMPUTE_USER_DATA_0 - PACKET3_SET_SH_REG_START;
+ ptr[i++] = 0xffffffff & (ib_result_mc_address + DATA_OFFSET * 4);
+ ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32;
+
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
+ ptr[i++] = mmCOMPUTE_RESOURCE_LIMITS - PACKET3_SET_SH_REG_START;
+ ptr[i++] = 0;
+
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3);
+ ptr[i++] = mmCOMPUTE_NUM_THREAD_X - PACKET3_SET_SH_REG_START;
+ ptr[i++] = 1;
+ ptr[i++] = 1;
+ ptr[i++] = 1;
+
+
+ /* Dispatch */
+ ptr[i++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+ ptr[i++] = 1;
+ ptr[i++] = 1;
+ ptr[i++] = 1;
+ ptr[i++] = 0x00000045; /* DISPATCH DIRECT field */
+
+
+ while (i & 7)
+ ptr[i++] = 0xffff1000; /* type3 nop packet */
+
+ memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
+ ib_info.ib_mc_address = ib_result_mc_address;
+ ib_info.size = i;
+
+ memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
+ ibs_request.ip_type = AMDGPU_HW_IP_GFX;
+ ibs_request.ring = 0;
+ ibs_request.number_of_ibs = 1;
+ ibs_request.ibs = &ib_info;
+ ibs_request.resources = bo_list;
+ ibs_request.fence_info.handle = NULL;
+
+ r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request, 1);
+ CU_ASSERT_EQUAL(r, 0);
+ seq_no = ibs_request.seq_no;
+
+
+
+ /* Prepare second command with dependency on the first */
+ j = i;
+ ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3);
+ ptr[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+ ptr[i++] = 0xfffffffc & ib_result_mc_address + DATA_OFFSET * 4;
+ ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32;
+ ptr[i++] = 99;
+
+ while (i & 7)
+ ptr[i++] = 0xffff1000; /* type3 nop packet */
+
+ memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
+ ib_info.ib_mc_address = ib_result_mc_address + j * 4;
+ ib_info.size = i - j;
+
+ memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
+ ibs_request.ip_type = AMDGPU_HW_IP_GFX;
+ ibs_request.ring = 0;
+ ibs_request.number_of_ibs = 1;
+ ibs_request.ibs = &ib_info;
+ ibs_request.resources = bo_list;
+ ibs_request.fence_info.handle = NULL;
+
+ ibs_request.number_of_dependencies = 1;
+
+ ibs_request.dependencies = calloc(1, sizeof(*ibs_request.dependencies));
+ ibs_request.dependencies[0].context = context_handle[1];
+ ibs_request.dependencies[0].ip_instance = 0;
+ ibs_request.dependencies[0].ring = 0;
+ ibs_request.dependencies[0].fence = seq_no;
+
+
+ r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request, 1);
+ CU_ASSERT_EQUAL(r, 0);
+
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle[0];
+ fence_status.ip_type = AMDGPU_HW_IP_GFX;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = ibs_request.seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE,0, &expired);
+ CU_ASSERT_EQUAL(r, 0);
+
+ /* Expect the second command to wait for shader to complete */
+ CU_ASSERT_EQUAL(ptr[DATA_OFFSET], 99);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_ctx_free(context_handle[0]);
+ CU_ASSERT_EQUAL(r, 0);
+ r = amdgpu_cs_ctx_free(context_handle[1]);
+ CU_ASSERT_EQUAL(r, 0);
+
+ free(ibs_request.dependencies);
+}
|
|
From: <da...@ke...> - 2017-12-05 15:03:57
|
data/amdgpu.ids | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
New commits:
commit 47419a1497fa585ff74b41732b267356b9d5b949
Author: Michel Dänzer <mic...@am...>
Date: Tue Dec 5 12:59:35 2017 +0100
amdgpu.ids: Refresh from AMD 17.40 release
Reviewed-by: Alex Deucher <ale...@am...>
Acked-by: Christian König <chr...@am...>
Signed-off-by: Michel Dänzer <mic...@am...>
diff --git a/data/amdgpu.ids b/data/amdgpu.ids
index f6c65dd9..1828e410 100644
--- a/data/amdgpu.ids
+++ b/data/amdgpu.ids
@@ -62,6 +62,7 @@
67DF, C6, Radeon RX 570 Series
67DF, C7, AMD Radeon (TM) RX 480 Graphics
67DF, CF, AMD Radeon (TM) RX 470 Graphics
+67DF, D7, Radeon(TM) RX 470 Graphics
67DF, E3, Radeon RX Series
67DF, E7, Radeon RX 580 Series
67DF, EF, Radeon RX 570 Series
@@ -84,13 +85,16 @@
67EF, C5, AMD Radeon (TM) RX 460 Graphics
67EF, C7, AMD Radeon (TM) RX Graphics
67EF, CF, AMD Radeon (TM) RX 460 Graphics
+67EF, E0, Radeon RX 560 Series
67EF, E1, Radeon RX Series
67EF, E3, Radeon RX Series
-67EF, E7, Radeon RX Series
+67EF, E5, Radeon RX 560 Series
67EF, EF, AMD Radeon (TM) RX Graphics
-67EF, FF, Radeon RX Series
+67EF, FF, Radeon(TM) RX 460 Graphics
67FF, C0, AMD Radeon (TM) RX Graphics
67FF, C1, AMD Radeon (TM) RX Graphics
+67FF, CF, Radeon RX 560 Series
+67FF, EF, Radeon RX 560 Series
67FF, FF, Radeon RX 550 Series
6800, 0, AMD Radeon HD 7970M
6801, 0, AMD Radeon(TM) HD8970M
@@ -122,6 +126,25 @@
6837, 0, AMD Radeon HD7700 Series
683D, 0, AMD Radeon HD 7700 Series
683F, 0, AMD Radeon HD 7700 Series
+6860, 00, Radeon Instinct MI25
+6860, 01, Radeon Pro V320
+6860, 02, Radeon Instinct MI25
+6860, 03, Radeon Pro V340
+6860, 04, Radeon Instinct MI25x2
+6861, 00, Radeon(TM) Pro WX9100
+6862, 00, Radeon Pro SSG
+6863, 00, Radeon Vega Frontier Edition
+6864, 03, Radeon Pro V340
+6864, 04, Instinct MI25x2
+6868, 00, Radeon(TM) Pro WX8100
+686C, 00, GLXT (Radeon Instinct MI25) MxGPU VFID
+686C, 01, GLXT (Radeon Pro V320) MxGPU
+686C, 02, GLXT (Radeon Instinct MI25) MxGPU
+686C, 03, GLXT (Radeon Pro V340) MxGPU
+686C, 04, GLXT (Radeon Instinct MI25x2) MxGPU
+687F, C0, Radeon RX Vega
+687F, C1, Radeon RX Vega
+687F, C3, Radeon RX Vega
6900, 0, AMD Radeon R7 M260
6900, 81, AMD Radeon (TM) R7 M360
6900, 83, AMD Radeon (TM) R7 M340
@@ -139,8 +162,12 @@
6939, F0, AMD Radeon R9 200 Series
6939, 0, AMD Radeon R9 200 Series
6939, F1, AMD Radeon (TM) R9 380 Series
+6980, 00, Radeon Pro WX3100
6985, 00, AMD Radeon Pro WX3100
+6987, 80, AMD Embedded Radeon E9171
6995, 00, AMD Radeon Pro WX2100
+6997, 00, Radeon Pro WX2100
+699F, 81, AMD Embedded Radeon E9170 Series
699F, C0, Radeon 500 Series
699F, C3, Radeon 500 Series
699F, C7, Radeon RX 550 Series
|
|
From: <agr...@ke...> - 2017-12-12 14:26:33
|
tests/amdgpu/basic_tests.c | 2 --
1 file changed, 2 deletions(-)
New commits:
commit 7f2993948cc13b4f526cfe6b7fe272581a633928
Author: Andrey Grodzovsky <and...@am...>
Date: Tue Dec 12 08:33:09 2017 -0500
amdgpu: Remove dummy CU_ASSERT_EQUAL.
Fixes test failure on rhel.
Signed-off-by: Andrey Grodzovsky <and...@am...>
Reviewed-by: Qiang Yu <Qia...@am...>
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index a78cf521..474a679c 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -1459,8 +1459,6 @@ static void amdgpu_sync_dependency_test(void)
static uint32_t *ptr;
uint64_t seq_no;
- CU_ASSERT_EQUAL(r, 0);
-
r = amdgpu_cs_ctx_create(device_handle, &context_handle[0]);
CU_ASSERT_EQUAL(r, 0);
r = amdgpu_cs_ctx_create(device_handle, &context_handle[1]);
|
|
From: <agr...@ke...> - 2017-12-15 18:36:00
|
tests/amdgpu/vcn_tests.c | 2 ++
1 file changed, 2 insertions(+)
New commits:
commit 4f8e426884a51b6786459ea2505f1ce82a13a87c
Author: Andrey Grodzovsky <and...@am...>
Date: Fri Dec 15 13:21:02 2017 -0500
tests/amdgpu: Add return CUE_SUCCESS to suite_vcn_tests_clean.
fixes: 806d0803600000faecb4025d8e9c7490cb097c25 (amdgpu: Use new suite/test disabling functionality.)
bug: https://bugs.freedesktop.org/show_bug.cgi?id=104280
Signed-off-by: Andrey Grodzovsky <and...@am...>
Reviewed-by: Christian König <chr...@am...>
diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index 53a2d08e..9224bc37 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -144,6 +144,8 @@ int suite_vcn_tests_clean(void)
r = amdgpu_device_deinitialize(device_handle);
if (r)
return CUE_SCLEAN_FAILED;
+
+ return CUE_SUCCESS;
}
static int submit(unsigned ndw, unsigned ip)
|
|
From: <aus...@ke...> - 2017-12-15 18:42:45
|
etnaviv/etnaviv_bo_cache.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
New commits:
commit 7d984e609470aa38d4c3f7d48e26fa763a03af13
Author: Lucas Stach <l....@pe...>
Date: Fri Dec 15 11:30:26 2017 +0100
etnaviv: fix BO cache to properly work with different flags
Currently if the oldest BO in a bucket has different flags than what we
look for we'll miss the cache.Fix this by iterating over the cached BOs
until we find the oldest one with matching flags. This improves the hit
ratio for some of the buckets.
Signed-off-by: Lucas Stach <l....@pe...>
Reviewed-by: Philipp Zabel <p....@pe...>
Reviewed-by: Christian Gmeiner <chr...@gm...>
diff --git a/etnaviv/etnaviv_bo_cache.c b/etnaviv/etnaviv_bo_cache.c
index 8924651f..6208230d 100644
--- a/etnaviv/etnaviv_bo_cache.c
+++ b/etnaviv/etnaviv_bo_cache.c
@@ -124,20 +124,32 @@ static int is_idle(struct etna_bo *bo)
static struct etna_bo *find_in_bucket(struct etna_bo_bucket *bucket, uint32_t flags)
{
- struct etna_bo *bo = NULL;
+ struct etna_bo *bo = NULL, *tmp;
pthread_mutex_lock(&table_lock);
- while (!LIST_IS_EMPTY(&bucket->list)) {
- bo = LIST_ENTRY(struct etna_bo, bucket->list.next, list);
- if (bo->flags == flags && is_idle(bo)) {
- list_del(&bo->list);
- break;
+ if (LIST_IS_EMPTY(&bucket->list))
+ goto out_unlock;
+
+ LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &bucket->list, list) {
+ /* skip BOs with different flags */
+ if (bo->flags != flags)
+ continue;
+
+ /* check if the first BO with matching flags is idle */
+ if (is_idle(bo)) {
+ list_delinit(&bo->list);
+ goto out_unlock;
}
- bo = NULL;
+ /* If the oldest BO is still busy, don't try younger ones */
break;
}
+
+ /* There was no matching buffer found */
+ bo = NULL;
+
+out_unlock:
pthread_mutex_unlock(&table_lock);
return bo;
|
|
From: <ai...@ke...> - 2017-12-18 01:28:57
|
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit 831036a6f62005da9fb4a75fe043bd96ce672d27
Author: Dave Airlie <ai...@re...>
Date: Mon Dec 18 11:24:34 2017 +1000
configure.ac: bump version for release
diff --git a/configure.ac b/configure.ac
index b2d961b1..35378b33 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.88],
+ [2.4.89],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
|
|
From: <da...@ke...> - 2018-01-08 17:35:28
|
data/Makefile.am | 2 ++
1 file changed, 2 insertions(+)
New commits:
commit ad3152fa698b128c9bd266522b0b48594b131055
Author: Seung-Woo Kim <sw0...@sa...>
Date: Thu Jan 4 15:31:51 2018 +0900
amdgpu: fix not to add amdgpu.ids when building without amdgpu
The amdgpu.ids is only required when building with amdgpu support.
Fix not to add it without amdgpu.
Signed-off-by: Seung-Woo Kim <sw0...@sa...>
Reviewed-by: Michel Dänzer <mic...@am...>
diff --git a/data/Makefile.am b/data/Makefile.am
index eba915dd..897a7f35 100644
--- a/data/Makefile.am
+++ b/data/Makefile.am
@@ -20,4 +20,6 @@
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
libdrmdatadir = @libdrmdatadir@
+if HAVE_AMDGPU
dist_libdrmdata_DATA = amdgpu.ids
+endif
|
|
From: <vi...@ke...> - 2018-01-11 18:30:06
|
intel/intel_chipset.h | 30 +++++++++++++++++++++++-------
1 file changed, 23 insertions(+), 7 deletions(-)
New commits:
commit d3cb58831517d4d42869a7c1f518c861baafdc8e
Author: Anuj Phogat <anu...@gm...>
Date: Wed Jan 10 15:51:02 2018 -0800
intel: Add more Coffeelake PCI IDs
Cc: Rodrigo Vivi <rod...@in...>
Cc: Anusha Srivatsa <anu...@in...>
Signed-off-by: Anuj Phogat <anu...@gm...>
Reviewed-by: Rodrigo Vivi <rod...@in...>
Signed-off-by: Rodrigo Vivi <rod...@in...>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index d81b1646..3818e71e 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -223,15 +223,23 @@
#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90
#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
+#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99
#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
+#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A
#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
-#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
-#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
-#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
-#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
+#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1
+#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4
+#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0
+#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3
+#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9
+#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2
+#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5
+#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6
+#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7
+#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8
#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52
#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
@@ -477,17 +485,25 @@
#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
(devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \
(devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
(devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
- (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3)
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4)
#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
(devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
-#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
+#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
(devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
(devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4)
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5)
#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
IS_CFL_H(devid) || \
|
|
From: <da...@ke...> - 2018-01-15 16:08:39
|
amdgpu/amdgpu_asic_id.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit 57d3d4c96887cde016fe1d2766196accf77ca423
Author: Michel Dänzer <mic...@am...>
Date: Mon Jan 8 11:20:25 2018 +0100
amdgpu: Don't print error message if parse_one_line returned -EAGAIN
It means it just didn't find an entry for the GPU in the amdgpu.ids file.
Fixes spurious
amdgpu_parse_asic_ids: Cannot parse ASIC IDs: Resource temporarily unavailable
error messages in that case.
Reported-by: Marek Olšák <mar...@am...>
Reviewed-by: Marek Olšák <mar...@am...>
diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c
index 0c8925e5..62459c09 100644
--- a/amdgpu/amdgpu_asic_id.c
+++ b/amdgpu/amdgpu_asic_id.c
@@ -155,7 +155,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
if (r == -EINVAL) {
fprintf(stderr, "Invalid format: %s: line %d: %s\n",
AMDGPU_ASIC_ID_TABLE, line_num, line);
- } else if (r) {
+ } else if (r && r != -EAGAIN) {
fprintf(stderr, "%s: Cannot parse ASIC IDs: %s\n",
__func__, strerror(-r));
}
|
|
From: <db...@ke...> - 2018-01-18 18:15:15
|
amdgpu/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
New commits:
commit 3509e7cd2b9098193b9f8c97ecd68fae929eb131
Author: Christoph Haag <ha...@fr...ub>
Date: Thu Jan 18 19:01:55 2018 +0100
meson: fix the install path of amdgpu.ids
Signed-off-by: Dylan Baker <dyl...@in...>
diff --git a/amdgpu/meson.build b/amdgpu/meson.build
index 55ab9d1d..8b045205 100644
--- a/amdgpu/meson.build
+++ b/amdgpu/meson.build
@@ -19,7 +19,7 @@
# SOFTWARE.
-datadir_amdgpu = join_paths(get_option('datadir'), 'libdrm', 'amdgpu.ids')
+datadir_amdgpu = join_paths(get_option('prefix'), get_option('datadir'), 'libdrm')
libdrm_amdgpu = shared_library(
'drm_amdgpu',
@@ -33,7 +33,7 @@ libdrm_amdgpu = shared_library(
],
c_args : [
warn_c_args,
- '-DAMDGPU_ASIC_ID_TABLE="@0@"'.format(datadir_amdgpu),
+ '-DAMDGPU_ASIC_ID_TABLE="@0@"'.format(join_paths(datadir_amdgpu, 'amdgpu.ids')),
],
include_directories : [inc_root, inc_drm],
link_with : libdrm,
|
|
From: <dea...@ke...> - 2018-01-23 10:17:57
|
amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit 1cc17744b988106b4fe71ee9d3d17b651d6adb40
Author: Christian König <chr...@am...>
Date: Mon Jan 22 13:17:30 2018 +0100
amdgpu: fix high VA mask
That constant needs to be 64bits.
Fixes: amdgpu: use the high VA range if possible v2
Signed-off-by: Christian König <chr...@am...>
Reviewed-by: Alex Deucher <ale...@am...>
diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index a0d01727..f34e27a9 100644
--- a/amdgpu/amdgpu_device.c
+++ b/amdgpu/amdgpu_device.c
@@ -272,7 +272,7 @@ int amdgpu_device_initialize(int fd,
max = dev->dev_info.virtual_address_max;
}
- max = MIN2(max, (start & ~0xffffffff) + 0x100000000ULL);
+ max = MIN2(max, (start & ~0xffffffffULL) + 0x100000000ULL);
amdgpu_vamgr_init(&dev->vamgr_32, start, max,
dev->dev_info.virtual_address_alignment);
|
|
From: <eri...@ke...> - 2018-01-25 10:53:38
|
tests/modetest/modetest.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
New commits:
commit 6736ad45d88c4ce16c6f76fd128fae73b51ea2dc
Author: Seung-Woo Kim <sw0...@sa...>
Date: Wed Jan 10 11:16:41 2018 +0900
modetest: Fix to check return value of asprintf()
There is warning about ignoring return value of 'asprintf'. Fix to
check return value of asprintf().
Signed-off-by: Seung-Woo Kim <sw0...@sa...>
Reviewed-by: Eric Engestrom <eri...@im...>
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index 62d93327..0773bd02 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -656,10 +656,13 @@ static struct resources *get_resources(struct device *dev)
for (i = 0; i < res->res->count_connectors; i++) {
struct connector *connector = &res->connectors[i];
drmModeConnector *conn = connector->connector;
+ int num;
- asprintf(&connector->name, "%s-%u",
+ num = asprintf(&connector->name, "%s-%u",
util_lookup_connector_type_name(conn->connector_type),
conn->connector_type_id);
+ if (num < 0)
+ goto error;
}
#define get_properties(_res, __res, type, Type) \
|
|
From: <rob...@ke...> - 2018-01-26 20:29:36
|
freedreno/freedreno_priv.h | 2 +-
freedreno/msm/msm_pipe.c | 28 +++++++++++++++++-----------
2 files changed, 18 insertions(+), 12 deletions(-)
New commits:
commit 6f0f6cee5e9be1dcf816c144e05d26352c85a9e8
Author: Rob Clark <rob...@fr...>
Date: Wed Jan 24 15:08:46 2018 -0500
freedreno: clamp priority based on # of rings
In case of a kernel that is new enough to support multiple submit-
queues, but with an adreno generation which doesn't support multiple
prioritized ringbuffers, we'd attempt to open a submit-queue with
prio=1 (medium), which is rejected by the kernel.
This could happen either w/ an older mesa (which uses fd_pipe_new())
or a newer mesa which defaults to prio=1 if no pipe context priority
flags are set.
The simple answer to fix both cases is to clamp the requested priority
according to the number of rings. This might not do exactly what you
want, if we hypothetically had 2 rings (it would result in requested
medium priority being high priority instead of low priority). But the
number of rings (for hw gen's that support this) is purely a software
construct, so the easy answer there is to have the kernel advertise at
least 3 rings if it supports more than one. There isn't really any
reason to do otherwise.
Signed-off-by: Rob Clark <rob...@fr...>
diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h
index 27307472..199ccb94 100644
--- a/freedreno/freedreno_priv.h
+++ b/freedreno/freedreno_priv.h
@@ -49,6 +49,7 @@
#include "xf86atomic.h"
#include "util_double_list.h"
+#include "util_math.h"
#include "freedreno_drmif.h"
#include "freedreno_ringbuffer.h"
@@ -173,7 +174,6 @@ struct fd_bo {
time_t free_time; /* time when added to bucket-list */
};
-#define ALIGN(v,a) (((v) + (a) - 1) & ~((a) - 1))
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#define enable_debug 0 /* TODO make dynamic */
diff --git a/freedreno/msm/msm_pipe.c b/freedreno/msm/msm_pipe.c
index 7395e573..12e4be59 100644
--- a/freedreno/msm/msm_pipe.c
+++ b/freedreno/msm/msm_pipe.c
@@ -100,42 +100,48 @@ static int msm_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp,
return 0;
}
-static int open_submitqueue(struct fd_device *dev, uint32_t prio,
- uint32_t *queue_id)
+static int open_submitqueue(struct fd_pipe *pipe, uint32_t prio)
{
struct drm_msm_submitqueue req = {
.flags = 0,
.prio = prio,
};
+ uint64_t nr_rings = 1;
int ret;
- if (fd_device_version(dev) < FD_VERSION_SUBMIT_QUEUES) {
- *queue_id = 0;
+ if (fd_device_version(pipe->dev) < FD_VERSION_SUBMIT_QUEUES) {
+ to_msm_pipe(pipe)->queue_id = 0;
return 0;
}
- ret = drmCommandWriteRead(dev->fd, DRM_MSM_SUBMITQUEUE_NEW, &req, sizeof(req));
+ msm_pipe_get_param(pipe, FD_NR_RINGS, &nr_rings);
+
+ req.prio = MIN2(req.prio, MAX2(nr_rings, 1) - 1);
+
+ ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_SUBMITQUEUE_NEW,
+ &req, sizeof(req));
if (ret) {
ERROR_MSG("could not create submitqueue! %d (%s)", ret, strerror(errno));
return ret;
}
- *queue_id = req.id;
+ to_msm_pipe(pipe)->queue_id = req.id;
return 0;
}
-static void close_submitqueue(struct fd_device *dev, uint32_t queue_id)
+static void close_submitqueue(struct fd_pipe *pipe, uint32_t queue_id)
{
- if (fd_device_version(dev) < FD_VERSION_SUBMIT_QUEUES)
+ if (fd_device_version(pipe->dev) < FD_VERSION_SUBMIT_QUEUES)
return;
- drmCommandWrite(dev->fd, DRM_MSM_SUBMITQUEUE_CLOSE, &queue_id, sizeof(queue_id));
+ drmCommandWrite(pipe->dev->fd, DRM_MSM_SUBMITQUEUE_CLOSE,
+ &queue_id, sizeof(queue_id));
}
static void msm_pipe_destroy(struct fd_pipe *pipe)
{
struct msm_pipe *msm_pipe = to_msm_pipe(pipe);
- close_submitqueue(pipe->dev, msm_pipe->queue_id);
+ close_submitqueue(pipe, msm_pipe->queue_id);
free(msm_pipe);
}
@@ -193,7 +199,7 @@ drm_private struct fd_pipe * msm_pipe_new(struct fd_device *dev,
INFO_MSG(" Chip-id: 0x%08x", msm_pipe->chip_id);
INFO_MSG(" GMEM size: 0x%08x", msm_pipe->gmem);
- if (open_submitqueue(dev, prio, &msm_pipe->queue_id))
+ if (open_submitqueue(pipe, prio))
goto fail;
return pipe;
|
|
From: <eve...@ke...> - 2018-01-31 16:02:27
|
tests/amdgpu/vm_tests.c | 4 ++++
1 file changed, 4 insertions(+)
New commits:
commit 10e85a8b7f28e80f5184919b2448ade18c19ca21
Author: Emil Velikov <emi...@co...>
Date: Mon Jan 29 14:51:31 2018 +0000
tests/amdgpu: add missing config.h include
Otherwise we'll end up without the macros set during configure stage.
And effectively error out in sanity tests such as the mmap static
assert.
To reproduce, do a multilib build - 32bit build on 64bit machine.
Cc: Fabio Pedretti <ped...@gm...>
Cc: Andrey Grodzovsky <And...@am...>
Fixes: 33dcc29f7cc ("amdgpu: Add VMID reservation per GPU context test.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104819
Signed-off-by: Emil Velikov <emi...@co...>
Reviewed-by: Eric Engestrom <eri...@im...>
diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c
index 7b6dc5d6..502a9405 100644
--- a/tests/amdgpu/vm_tests.c
+++ b/tests/amdgpu/vm_tests.c
@@ -21,6 +21,10 @@
*
*/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
#include "CUnit/Basic.h"
#include "amdgpu_test.h"
|
|
From: <db...@ke...> - 2018-01-31 17:17:15
|
nouveau/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit 9e34ad590e0e1003a597b8cc790a3f36830ba993
Author: Dylan Baker <dy...@pn...>
Date: Thu Jan 25 15:44:37 2018 -0800
meson: fix libdrm_nouveau pkgconfig include directories
Signed-off-by: Dylan Baker <dyl...@in...>
Reviewed-by: Eric Engestrom <eri...@im...>
diff --git a/nouveau/meson.build b/nouveau/meson.build
index bfecf84b..f031cd63 100644
--- a/nouveau/meson.build
+++ b/nouveau/meson.build
@@ -45,7 +45,7 @@ install_headers(
pkg.generate(
name : 'libdrm_nouveau',
libraries : libdrm_nouveau,
- subdirs : ['.', 'nouveau'],
+ subdirs : ['.', 'libdrm', 'libdrm/nouveau'],
version : meson.project_version(),
requires_private : 'libdrm',
description : 'Userspace interface to nouveau kernel DRM services',
|
|
From: <bni...@ke...> - 2018-02-06 17:18:44
|
xf86drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit b1e63d9ee622f3f08127bab43bf6817101b870a8
Author: Bas Nieuwenhuizen <ba...@ba...>
Date: Tue Feb 6 11:21:35 2018 +0100
drm: Fix 32-bit drmSyncobjWait.
Otherwise we get an EFAULT, at least on a 64-bit kernel.
Fixes: 2048a9e7 "drm: add drmSyncobjWait wrapper"
Reviewed-by: Christian König <chr...@am...>
Reviewed-by: Dave Airlie <ai...@re...>
diff --git a/xf86drm.c b/xf86drm.c
index 74b4e230..1e87610b 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4271,7 +4271,7 @@ int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
int ret;
memclear(args);
- args.handles = (intptr_t)handles;
+ args.handles = (uintptr_t)handles;
args.timeout_nsec = timeout_nsec;
args.count_handles = num_handles;
args.flags = flags;
|
|
From: <Chu...@ke...> - 2018-02-07 03:23:38
|
xf86drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit bde3b9b689407eadd1cb0d9348a0fd7906c880e2
Author: Chunming Zhou <dav...@am...>
Date: Wed Feb 7 11:22:32 2018 +0800
fix return value for syncobj wait
otherwise -ETIME is missed.
Signed-off-by: Chunming Zhou <dav...@am...>
Reviewed-by: Christian König <chr...@am...>
diff --git a/xf86drm.c b/xf86drm.c
index 1e87610b..344326db 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4278,7 +4278,7 @@ int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args);
if (ret < 0)
- return ret;
+ return -errno;
if (first_signaled)
*first_signaled = args.first_signaled;
|
|
From: <Chu...@ke...> - 2018-02-08 06:37:07
|
amdgpu/amdgpu_vamgr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
New commits:
commit d07be74a4afe9d22f987aca7e8e84cccaa210248
Author: Chunming Zhou <dav...@am...>
Date: Thu Feb 8 14:35:26 2018 +0800
amdgpu: fix inefficient vamgr algorithm
issue: UMD allocates top 4GB, but don't do anything, just reserve top 4GB space,
but the performance of VP13 drops from 162fps to 99fps.
root cause:
our va hole list of vamgr is too long by time going.
fix:
reusing old hole as much as possible can make the list shortest.
result:
performance recovers as non-list path, next patch will remove non-list code path.
Signed-off-by: Chunming Zhou <dav...@am...>
Reviewed-by: Christian König <chr...@am...>
diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
index ab425ef7..a2852b55 100644
--- a/amdgpu/amdgpu_vamgr.c
+++ b/amdgpu/amdgpu_vamgr.c
@@ -80,9 +80,7 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
return AMDGPU_INVALID_VA_ADDRESS;
pthread_mutex_lock(&mgr->bo_va_mutex);
- /* TODO: using more appropriate way to track the holes */
- /* first look for a hole */
- LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
+ LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) {
if (base_required) {
if (hole->offset > base_required ||
(hole->offset + hole->size) < (base_required + size))
|
|
From: <Chu...@ke...> - 2018-02-08 06:53:47
|
amdgpu/amdgpu_internal.h | 2
amdgpu/amdgpu_vamgr.c | 121 ++++++++++++++++-------------------------------
2 files changed, 43 insertions(+), 80 deletions(-)
New commits:
commit 41b94a3fb6e87d057fad78568d920d29489e5060
Author: Chunming Zhou <dav...@am...>
Date: Thu Feb 8 14:52:11 2018 +0800
amdgpu: clean up non list code path for vamgr
Signed-off-by: Chunming Zhou <dav...@am...>
Reviewed-by: Christian König <chr...@am...>
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index 3e044f11..75276a99 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -53,8 +53,6 @@ struct amdgpu_bo_va_hole {
};
struct amdgpu_bo_va_mgr {
- /* the start virtual address */
- uint64_t va_offset;
uint64_t va_max;
struct list_head va_holes;
pthread_mutex_t bo_va_mutex;
diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
index a2852b55..2311e5eb 100644
--- a/amdgpu/amdgpu_vamgr.c
+++ b/amdgpu/amdgpu_vamgr.c
@@ -48,12 +48,19 @@ int amdgpu_va_range_query(amdgpu_device_handle dev,
drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start,
uint64_t max, uint64_t alignment)
{
- mgr->va_offset = start;
+ struct amdgpu_bo_va_hole *n;
+
mgr->va_max = max;
mgr->va_alignment = alignment;
list_inithead(&mgr->va_holes);
pthread_mutex_init(&mgr->bo_va_mutex, NULL);
+ pthread_mutex_lock(&mgr->bo_va_mutex);
+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
+ n->size = mgr->va_max;
+ n->offset = start;
+ list_add(&n->list, &mgr->va_holes);
+ pthread_mutex_unlock(&mgr->bo_va_mutex);
}
drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr)
@@ -122,41 +129,14 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
}
}
- if (base_required) {
- if (base_required < mgr->va_offset) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
- offset = mgr->va_offset;
- waste = base_required - mgr->va_offset;
- } else {
- offset = mgr->va_offset;
- waste = offset % alignment;
- waste = waste ? alignment - waste : 0;
- }
-
- if (offset + waste + size > mgr->va_max) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
-
- if (waste) {
- n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- n->size = waste;
- n->offset = offset;
- list_add(&n->list, &mgr->va_holes);
- }
-
- offset += waste;
- mgr->va_offset += size + waste;
pthread_mutex_unlock(&mgr->bo_va_mutex);
- return offset;
+ return AMDGPU_INVALID_VA_ADDRESS;
}
static drm_private void
amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size)
{
- struct amdgpu_bo_va_hole *hole;
+ struct amdgpu_bo_va_hole *hole, *next;
if (va == AMDGPU_INVALID_VA_ADDRESS)
return;
@@ -164,61 +144,46 @@ amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size)
size = ALIGN(size, mgr->va_alignment);
pthread_mutex_lock(&mgr->bo_va_mutex);
- if ((va + size) == mgr->va_offset) {
- mgr->va_offset = va;
- /* Delete uppermost hole if it reaches the new top */
- if (!LIST_IS_EMPTY(&mgr->va_holes)) {
- hole = container_of(mgr->va_holes.next, hole, list);
- if ((hole->offset + hole->size) == va) {
- mgr->va_offset = hole->offset;
+ hole = container_of(&mgr->va_holes, hole, list);
+ LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
+ if (next->offset < va)
+ break;
+ hole = next;
+ }
+
+ if (&hole->list != &mgr->va_holes) {
+ /* Grow upper hole if it's adjacent */
+ if (hole->offset == (va + size)) {
+ hole->offset = va;
+ hole->size += size;
+ /* Merge lower hole if it's adjacent */
+ if (next != hole &&
+ &next->list != &mgr->va_holes &&
+ (next->offset + next->size) == va) {
+ next->size += hole->size;
list_del(&hole->list);
free(hole);
}
}
- } else {
- struct amdgpu_bo_va_hole *next;
-
- hole = container_of(&mgr->va_holes, hole, list);
- LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
- if (next->offset < va)
- break;
- hole = next;
- }
-
- if (&hole->list != &mgr->va_holes) {
- /* Grow upper hole if it's adjacent */
- if (hole->offset == (va + size)) {
- hole->offset = va;
- hole->size += size;
- /* Merge lower hole if it's adjacent */
- if (next != hole &&
- &next->list != &mgr->va_holes &&
- (next->offset + next->size) == va) {
- next->size += hole->size;
- list_del(&hole->list);
- free(hole);
- }
- goto out;
- }
- }
+ }
- /* Grow lower hole if it's adjacent */
- if (next != hole && &next->list != &mgr->va_holes &&
- (next->offset + next->size) == va) {
- next->size += size;
- goto out;
- }
+ /* Grow lower hole if it's adjacent */
+ if (next != hole && &next->list != &mgr->va_holes &&
+ (next->offset + next->size) == va) {
+ next->size += size;
+ goto out;
+ }
- /* FIXME on allocation failure we just lose virtual address space
- * maybe print a warning
- */
- next = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- if (next) {
- next->size = size;
- next->offset = va;
- list_add(&next->list, &hole->list);
- }
+ /* FIXME on allocation failure we just lose virtual address space
+ * maybe print a warning
+ */
+ next = calloc(1, sizeof(struct amdgpu_bo_va_hole));
+ if (next) {
+ next->size = size;
+ next->offset = va;
+ list_add(&next->list, &hole->list);
}
+
out:
pthread_mutex_unlock(&mgr->bo_va_mutex);
}
|
|
From: <Chu...@ke...> - 2018-02-08 07:04:20
|
tests/amdgpu/amdgpu_test.h | 23 ++++++
tests/amdgpu/basic_tests.c | 160 ++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 182 insertions(+), 1 deletion(-)
New commits:
commit 09642c073e8af71127cf98b48fe1b2a376c606cf
Author: Chunming Zhou <dav...@am...>
Date: Thu Feb 8 15:03:01 2018 +0800
tests/amdgpu: add bo eviction test
for(( i=1; i < 100; i++))
do
echo "Hello, Welcome $i times "
sudo ./amdgpu_test -s 1 -t 5
done
with above stricpt, run in two terminals, will reproduce Felix's swap leeking issue.
Signed-off-by: Chunming Zhou <dav...@am...>
Acked-by: Christian König <chr...@am...>
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index 1db803c6..7397dea0 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -252,6 +252,29 @@ static inline int gpu_mem_free(amdgpu_bo_handle bo,
}
static inline int
+amdgpu_bo_alloc_wrap(amdgpu_device_handle dev, unsigned size,
+ unsigned alignment, unsigned heap, uint64_t flags,
+ amdgpu_bo_handle *bo)
+{
+ struct amdgpu_bo_alloc_request request = {};
+ amdgpu_bo_handle buf_handle;
+ int r;
+
+ request.alloc_size = size;
+ request.phys_alignment = alignment;
+ request.preferred_heap = heap;
+ request.flags = flags;
+
+ r = amdgpu_bo_alloc(dev, &request, &buf_handle);
+ if (r)
+ return r;
+
+ *bo = buf_handle;
+
+ return 0;
+}
+
+static inline int
amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
unsigned alignment, unsigned heap, uint64_t flags,
amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 354b0157..0ea010a8 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -51,14 +51,22 @@ static void amdgpu_command_submission_sdma(void);
static void amdgpu_userptr_test(void);
static void amdgpu_semaphore_test(void);
static void amdgpu_sync_dependency_test(void);
+static void amdgpu_bo_eviction_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type);
-
+static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
+ unsigned ip_type,
+ int instance, int pm4_dw, uint32_t *pm4_src,
+ int res_cnt, amdgpu_bo_handle *resources,
+ struct amdgpu_cs_ib_info *ib_info,
+ struct amdgpu_cs_request *ibs_request);
+
CU_TestInfo basic_tests[] = {
{ "Query Info Test", amdgpu_query_info_test },
{ "Userptr Test", amdgpu_userptr_test },
+ { "bo eviction Test", amdgpu_bo_eviction_test },
{ "Command submission Test (GFX)", amdgpu_command_submission_gfx },
{ "Command submission Test (Compute)", amdgpu_command_submission_compute },
{ "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence },
@@ -516,6 +524,156 @@ static void amdgpu_command_submission_gfx_cp_copy_data(void)
amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_GFX);
}
+static void amdgpu_bo_eviction_test(void)
+{
+ const int sdma_write_length = 1024;
+ const int pm4_dw = 256;
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle bo1, bo2, vram_max[2], gtt_max[2];
+ amdgpu_bo_handle *resources;
+ uint32_t *pm4;
+ struct amdgpu_cs_ib_info *ib_info;
+ struct amdgpu_cs_request *ibs_request;
+ uint64_t bo1_mc, bo2_mc;
+ volatile unsigned char *bo1_cpu, *bo2_cpu;
+ int i, j, r, loop1, loop2;
+ uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
+ amdgpu_va_handle bo1_va_handle, bo2_va_handle;
+ struct amdgpu_heap_info vram_info, gtt_info;
+
+ pm4 = calloc(pm4_dw, sizeof(*pm4));
+ CU_ASSERT_NOT_EQUAL(pm4, NULL);
+
+ ib_info = calloc(1, sizeof(*ib_info));
+ CU_ASSERT_NOT_EQUAL(ib_info, NULL);
+
+ ibs_request = calloc(1, sizeof(*ibs_request));
+ CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ /* prepare resource */
+ resources = calloc(4, sizeof(amdgpu_bo_handle));
+ CU_ASSERT_NOT_EQUAL(resources, NULL);
+
+ r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM,
+ 0, &vram_info);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[0]);
+ CU_ASSERT_EQUAL(r, 0);
+ r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[1]);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT,
+ 0, >t_info);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[0]);
+ CU_ASSERT_EQUAL(r, 0);
+ r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[1]);
+ CU_ASSERT_EQUAL(r, 0);
+
+
+
+ loop1 = loop2 = 0;
+ /* run 9 circle to test all mapping combination */
+ while(loop1 < 2) {
+ while(loop2 < 2) {
+ /* allocate UC bo1for sDMA use */
+ r = amdgpu_bo_alloc_and_map(device_handle,
+ sdma_write_length, 4096,
+ AMDGPU_GEM_DOMAIN_GTT,
+ gtt_flags[loop1], &bo1,
+ (void**)&bo1_cpu, &bo1_mc,
+ &bo1_va_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ /* set bo1 */
+ memset((void*)bo1_cpu, 0xaa, sdma_write_length);
+
+ /* allocate UC bo2 for sDMA use */
+ r = amdgpu_bo_alloc_and_map(device_handle,
+ sdma_write_length, 4096,
+ AMDGPU_GEM_DOMAIN_GTT,
+ gtt_flags[loop2], &bo2,
+ (void**)&bo2_cpu, &bo2_mc,
+ &bo2_va_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ /* clear bo2 */
+ memset((void*)bo2_cpu, 0, sdma_write_length);
+
+ resources[0] = bo1;
+ resources[1] = bo2;
+ resources[2] = vram_max[loop2];
+ resources[3] = gtt_max[loop2];
+
+ /* fulfill PM4: test DMA copy linear */
+ i = j = 0;
+ if (family_id == AMDGPU_FAMILY_SI) {
+ pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0,
+ sdma_write_length);
+ pm4[i++] = 0xffffffff & bo2_mc;
+ pm4[i++] = 0xffffffff & bo1_mc;
+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
+ pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
+ } else {
+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
+ if (family_id >= AMDGPU_FAMILY_AI)
+ pm4[i++] = sdma_write_length - 1;
+ else
+ pm4[i++] = sdma_write_length;
+ pm4[i++] = 0;
+ pm4[i++] = 0xffffffff & bo1_mc;
+ pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
+ pm4[i++] = 0xffffffff & bo2_mc;
+ pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
+ }
+
+ amdgpu_test_exec_cs_helper(context_handle,
+ AMDGPU_HW_IP_DMA, 0,
+ i, pm4,
+ 4, resources,
+ ib_info, ibs_request);
+
+ /* verify if SDMA test result meets with expected */
+ i = 0;
+ while(i < sdma_write_length) {
+ CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa);
+ }
+ r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc,
+ sdma_write_length);
+ CU_ASSERT_EQUAL(r, 0);
+ r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc,
+ sdma_write_length);
+ CU_ASSERT_EQUAL(r, 0);
+ loop2++;
+ }
+ loop2 = 0;
+ loop1++;
+ }
+ amdgpu_bo_free(vram_max[0]);
+ amdgpu_bo_free(vram_max[1]);
+ amdgpu_bo_free(gtt_max[0]);
+ amdgpu_bo_free(gtt_max[1]);
+ /* clean resources */
+ free(resources);
+ free(ibs_request);
+ free(ib_info);
+ free(pm4);
+
+ /* end of test */
+ r = amdgpu_cs_ctx_free(context_handle);
+ CU_ASSERT_EQUAL(r, 0);
+}
+
+
static void amdgpu_command_submission_gfx(void)
{
/* write data using the CP */
|
|
From: <da...@ke...> - 2018-02-08 08:55:55
|
amdgpu/amdgpu_internal.h | 2
amdgpu/amdgpu_vamgr.c | 121 ++++++++++++++++++++++++++++++-----------------
2 files changed, 80 insertions(+), 43 deletions(-)
New commits:
commit fa35b51f6366bd44185177f0a66e02191905d774
Author: Michel Dänzer <mic...@am...>
Date: Thu Feb 8 09:50:53 2018 +0100
Revert "amdgpu: clean up non list code path for vamgr"
This reverts commit 41b94a3fb6e87d057fad78568d920d29489e5060.
It caused crashes with radeonsi in at least glxgears and Xorg.
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index 75276a99..3e044f11 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -53,6 +53,8 @@ struct amdgpu_bo_va_hole {
};
struct amdgpu_bo_va_mgr {
+ /* the start virtual address */
+ uint64_t va_offset;
uint64_t va_max;
struct list_head va_holes;
pthread_mutex_t bo_va_mutex;
diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
index 2311e5eb..a2852b55 100644
--- a/amdgpu/amdgpu_vamgr.c
+++ b/amdgpu/amdgpu_vamgr.c
@@ -48,19 +48,12 @@ int amdgpu_va_range_query(amdgpu_device_handle dev,
drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start,
uint64_t max, uint64_t alignment)
{
- struct amdgpu_bo_va_hole *n;
-
+ mgr->va_offset = start;
mgr->va_max = max;
mgr->va_alignment = alignment;
list_inithead(&mgr->va_holes);
pthread_mutex_init(&mgr->bo_va_mutex, NULL);
- pthread_mutex_lock(&mgr->bo_va_mutex);
- n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- n->size = mgr->va_max;
- n->offset = start;
- list_add(&n->list, &mgr->va_holes);
- pthread_mutex_unlock(&mgr->bo_va_mutex);
}
drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr)
@@ -129,14 +122,41 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
}
}
+ if (base_required) {
+ if (base_required < mgr->va_offset) {
+ pthread_mutex_unlock(&mgr->bo_va_mutex);
+ return AMDGPU_INVALID_VA_ADDRESS;
+ }
+ offset = mgr->va_offset;
+ waste = base_required - mgr->va_offset;
+ } else {
+ offset = mgr->va_offset;
+ waste = offset % alignment;
+ waste = waste ? alignment - waste : 0;
+ }
+
+ if (offset + waste + size > mgr->va_max) {
+ pthread_mutex_unlock(&mgr->bo_va_mutex);
+ return AMDGPU_INVALID_VA_ADDRESS;
+ }
+
+ if (waste) {
+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
+ n->size = waste;
+ n->offset = offset;
+ list_add(&n->list, &mgr->va_holes);
+ }
+
+ offset += waste;
+ mgr->va_offset += size + waste;
pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
+ return offset;
}
static drm_private void
amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size)
{
- struct amdgpu_bo_va_hole *hole, *next;
+ struct amdgpu_bo_va_hole *hole;
if (va == AMDGPU_INVALID_VA_ADDRESS)
return;
@@ -144,46 +164,61 @@ amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size)
size = ALIGN(size, mgr->va_alignment);
pthread_mutex_lock(&mgr->bo_va_mutex);
- hole = container_of(&mgr->va_holes, hole, list);
- LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
- if (next->offset < va)
- break;
- hole = next;
- }
-
- if (&hole->list != &mgr->va_holes) {
- /* Grow upper hole if it's adjacent */
- if (hole->offset == (va + size)) {
- hole->offset = va;
- hole->size += size;
- /* Merge lower hole if it's adjacent */
- if (next != hole &&
- &next->list != &mgr->va_holes &&
- (next->offset + next->size) == va) {
- next->size += hole->size;
+ if ((va + size) == mgr->va_offset) {
+ mgr->va_offset = va;
+ /* Delete uppermost hole if it reaches the new top */
+ if (!LIST_IS_EMPTY(&mgr->va_holes)) {
+ hole = container_of(mgr->va_holes.next, hole, list);
+ if ((hole->offset + hole->size) == va) {
+ mgr->va_offset = hole->offset;
list_del(&hole->list);
free(hole);
}
}
- }
+ } else {
+ struct amdgpu_bo_va_hole *next;
- /* Grow lower hole if it's adjacent */
- if (next != hole && &next->list != &mgr->va_holes &&
- (next->offset + next->size) == va) {
- next->size += size;
- goto out;
- }
+ hole = container_of(&mgr->va_holes, hole, list);
+ LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
+ if (next->offset < va)
+ break;
+ hole = next;
+ }
- /* FIXME on allocation failure we just lose virtual address space
- * maybe print a warning
- */
- next = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- if (next) {
- next->size = size;
- next->offset = va;
- list_add(&next->list, &hole->list);
- }
+ if (&hole->list != &mgr->va_holes) {
+ /* Grow upper hole if it's adjacent */
+ if (hole->offset == (va + size)) {
+ hole->offset = va;
+ hole->size += size;
+ /* Merge lower hole if it's adjacent */
+ if (next != hole &&
+ &next->list != &mgr->va_holes &&
+ (next->offset + next->size) == va) {
+ next->size += hole->size;
+ list_del(&hole->list);
+ free(hole);
+ }
+ goto out;
+ }
+ }
+
+ /* Grow lower hole if it's adjacent */
+ if (next != hole && &next->list != &mgr->va_holes &&
+ (next->offset + next->size) == va) {
+ next->size += size;
+ goto out;
+ }
+ /* FIXME on allocation failure we just lose virtual address space
+ * maybe print a warning
+ */
+ next = calloc(1, sizeof(struct amdgpu_bo_va_hole));
+ if (next) {
+ next->size = size;
+ next->offset = va;
+ list_add(&next->list, &hole->list);
+ }
+ }
out:
pthread_mutex_unlock(&mgr->bo_va_mutex);
}
|
|
From: <Chu...@ke...> - 2018-02-09 09:58:47
|
amdgpu/amdgpu_internal.h | 2
amdgpu/amdgpu_vamgr.c | 122 ++++++++++++++++-------------------------------
2 files changed, 44 insertions(+), 80 deletions(-)
New commits:
commit 69f9faeee6c10d07a9f9f35e175a75f6e7eeecd1
Author: Chunming Zhou <dav...@am...>
Date: Thu Feb 8 14:52:11 2018 +0800
amdgpu: clean up non list code path for vamgr v2
v2: Add missing "goto out"
Signed-off-by: Chunming Zhou <dav...@am...>
Reviewed-by: Christian König <chr...@am...>
Tested-by: Michel Dänzer <mic...@am...>
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index 3e044f11..75276a99 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -53,8 +53,6 @@ struct amdgpu_bo_va_hole {
};
struct amdgpu_bo_va_mgr {
- /* the start virtual address */
- uint64_t va_offset;
uint64_t va_max;
struct list_head va_holes;
pthread_mutex_t bo_va_mutex;
diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
index a2852b55..722067f3 100644
--- a/amdgpu/amdgpu_vamgr.c
+++ b/amdgpu/amdgpu_vamgr.c
@@ -48,12 +48,19 @@ int amdgpu_va_range_query(amdgpu_device_handle dev,
drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start,
uint64_t max, uint64_t alignment)
{
- mgr->va_offset = start;
+ struct amdgpu_bo_va_hole *n;
+
mgr->va_max = max;
mgr->va_alignment = alignment;
list_inithead(&mgr->va_holes);
pthread_mutex_init(&mgr->bo_va_mutex, NULL);
+ pthread_mutex_lock(&mgr->bo_va_mutex);
+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
+ n->size = mgr->va_max;
+ n->offset = start;
+ list_add(&n->list, &mgr->va_holes);
+ pthread_mutex_unlock(&mgr->bo_va_mutex);
}
drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr)
@@ -122,41 +129,14 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
}
}
- if (base_required) {
- if (base_required < mgr->va_offset) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
- offset = mgr->va_offset;
- waste = base_required - mgr->va_offset;
- } else {
- offset = mgr->va_offset;
- waste = offset % alignment;
- waste = waste ? alignment - waste : 0;
- }
-
- if (offset + waste + size > mgr->va_max) {
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
- }
-
- if (waste) {
- n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- n->size = waste;
- n->offset = offset;
- list_add(&n->list, &mgr->va_holes);
- }
-
- offset += waste;
- mgr->va_offset += size + waste;
pthread_mutex_unlock(&mgr->bo_va_mutex);
- return offset;
+ return AMDGPU_INVALID_VA_ADDRESS;
}
static drm_private void
amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size)
{
- struct amdgpu_bo_va_hole *hole;
+ struct amdgpu_bo_va_hole *hole, *next;
if (va == AMDGPU_INVALID_VA_ADDRESS)
return;
@@ -164,61 +144,47 @@ amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size)
size = ALIGN(size, mgr->va_alignment);
pthread_mutex_lock(&mgr->bo_va_mutex);
- if ((va + size) == mgr->va_offset) {
- mgr->va_offset = va;
- /* Delete uppermost hole if it reaches the new top */
- if (!LIST_IS_EMPTY(&mgr->va_holes)) {
- hole = container_of(mgr->va_holes.next, hole, list);
- if ((hole->offset + hole->size) == va) {
- mgr->va_offset = hole->offset;
+ hole = container_of(&mgr->va_holes, hole, list);
+ LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
+ if (next->offset < va)
+ break;
+ hole = next;
+ }
+
+ if (&hole->list != &mgr->va_holes) {
+ /* Grow upper hole if it's adjacent */
+ if (hole->offset == (va + size)) {
+ hole->offset = va;
+ hole->size += size;
+ /* Merge lower hole if it's adjacent */
+ if (next != hole &&
+ &next->list != &mgr->va_holes &&
+ (next->offset + next->size) == va) {
+ next->size += hole->size;
list_del(&hole->list);
free(hole);
}
- }
- } else {
- struct amdgpu_bo_va_hole *next;
-
- hole = container_of(&mgr->va_holes, hole, list);
- LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
- if (next->offset < va)
- break;
- hole = next;
- }
-
- if (&hole->list != &mgr->va_holes) {
- /* Grow upper hole if it's adjacent */
- if (hole->offset == (va + size)) {
- hole->offset = va;
- hole->size += size;
- /* Merge lower hole if it's adjacent */
- if (next != hole &&
- &next->list != &mgr->va_holes &&
- (next->offset + next->size) == va) {
- next->size += hole->size;
- list_del(&hole->list);
- free(hole);
- }
- goto out;
- }
- }
-
- /* Grow lower hole if it's adjacent */
- if (next != hole && &next->list != &mgr->va_holes &&
- (next->offset + next->size) == va) {
- next->size += size;
goto out;
}
+ }
- /* FIXME on allocation failure we just lose virtual address space
- * maybe print a warning
- */
- next = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- if (next) {
- next->size = size;
- next->offset = va;
- list_add(&next->list, &hole->list);
- }
+ /* Grow lower hole if it's adjacent */
+ if (next != hole && &next->list != &mgr->va_holes &&
+ (next->offset + next->size) == va) {
+ next->size += size;
+ goto out;
}
+
+ /* FIXME on allocation failure we just lose virtual address space
+ * maybe print a warning
+ */
+ next = calloc(1, sizeof(struct amdgpu_bo_va_hole));
+ if (next) {
+ next->size = size;
+ next->offset = va;
+ list_add(&next->list, &hole->list);
+ }
+
out:
pthread_mutex_unlock(&mgr->bo_va_mutex);
}
|
|
From: <db...@ke...> - 2018-02-09 16:52:38
|
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
New commits:
commit deb59781fcc1183e19cca67e2db35c2e21f40ed5
Author: Dylan Baker <dy...@pn...>
Date: Wed Feb 7 15:35:24 2018 -0800
meson: include headers in root directory in ext_libdrm
Which is used in wraps.
Signed-off-by: Dylan Baker <dyl...@in...>
Reviewed-by: Eric Anholt <er...@an...>
diff --git a/meson.build b/meson.build
index 1342a5b3..4aaeb7e1 100644
--- a/meson.build
+++ b/meson.build
@@ -294,7 +294,7 @@ libdrm = shared_library(
ext_libdrm = declare_dependency(
link_with : libdrm,
- include_directories : inc_drm,
+ include_directories : [inc_root, inc_drm],
)
install_headers('libsync.h', 'xf86drm.h', 'xf86drmMode.h')
|
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