Thread: drm: Branch 'modesetting-gem' - 8 commits

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libdrm/intel/intel_bufmgr.h     |   35 ++++++++++
 libdrm/intel/intel_bufmgr_gem.c |  131 ++++++++++++++++++++++++++++++++++++++++
 linux-core/drm_compat.c         |   99 ++++++++++++++++++++++++++++++
 linux-core/drm_compat.h         |    3 
 linux-core/drm_vm.c             |   35 +++++-----
 linux-core/i915_gem.c           |   43 +++++++------
 linux-core/i915_gem_debug.c     |    4 -
 linux-core/i915_gem_tiling.c    |    3 
 shared-core/i915_drv.h          |    3 
 shared-core/i915_irq.c          |   51 ++++++++++++++-
 10 files changed, 363 insertions(+), 44 deletions(-)

New commits:
commit 8074b2e83d18bbf85d1c3284f561d849c829dd4b
Merge: c7fb19e... 4585787...
Author: Jesse Barnes <jb...@vi...>
Date:   Thu Aug 7 17:15:50 2008 -0700

    Make modesetting-gem build with recent kernels
    
    Needed to merge in VM fault changes & pci_read_base API update.

diff --cc linux-core/drm_compat.c
index aa825f3,c4ebc2f..d06b9d2
--- a/linux-core/drm_compat.c
+++ b/linux-core/drm_compat.c
@@@ -804,5 -756,105 +804,104 @@@ void *kmap_atomic_prot_pfn(unsigned lon
  }
  
  EXPORT_SYMBOL(kmap_atomic_prot_pfn);
 -
  #endif
  
+ #ifdef DRM_FULL_MM_COMPAT
+ #ifdef DRM_NO_FAULT
+ unsigned long drm_bo_vm_nopfn(struct vm_area_struct *vma,
+ 			      unsigned long address)
+ {
+ 	struct drm_buffer_object *bo = (struct drm_buffer_object *) vma->vm_private_data;
+ 	unsigned long page_offset;
+ 	struct page *page = NULL;
+ 	struct drm_ttm *ttm;
+ 	struct drm_device *dev;
+ 	unsigned long pfn;
+ 	int err;
+ 	unsigned long bus_base;
+ 	unsigned long bus_offset;
+ 	unsigned long bus_size;
+ 	unsigned long ret = NOPFN_REFAULT;
+ 
+ 	if (address > vma->vm_end)
+ 		return NOPFN_SIGBUS;
+ 
+ 	dev = bo->dev;
+ 	err = drm_bo_read_lock(&dev->bm.bm_lock, 1);
+ 	if (err)
+ 		return NOPFN_REFAULT;
+ 
+ 	err = mutex_lock_interruptible(&bo->mutex);
+ 	if (err) {
+ 		drm_bo_read_unlock(&dev->bm.bm_lock);
+ 		return NOPFN_REFAULT;
+ 	}
+ 
+ 	err = drm_bo_wait(bo, 0, 1, 0, 1);
+ 	if (err) {
+ 		ret = (err != -EAGAIN) ? NOPFN_SIGBUS : NOPFN_REFAULT;
+ 		bo->priv_flags &= ~_DRM_BO_FLAG_UNLOCKED;
+ 		goto out_unlock;
+ 	}
+ 
+ 	bo->priv_flags &= ~_DRM_BO_FLAG_UNLOCKED;
+ 
+ 	/*
+ 	 * If buffer happens to be in a non-mappable location,
+ 	 * move it to a mappable.
+ 	 */
+ 
+ 	if (!(bo->mem.flags & DRM_BO_FLAG_MAPPABLE)) {
+ 		uint32_t new_flags = bo->mem.proposed_flags |
+ 			DRM_BO_FLAG_MAPPABLE |
+ 			DRM_BO_FLAG_FORCE_MAPPABLE;
+ 		err = drm_bo_move_buffer(bo, new_flags, 0, 0);
+ 		if (err) {
+ 			ret = (err != -EAGAIN) ? NOPFN_SIGBUS : NOPFN_REFAULT;
+ 			goto out_unlock;
+ 		}
+ 	}
+ 
+ 	err = drm_bo_pci_offset(dev, &bo->mem, &bus_base, &bus_offset,
+ 				&bus_size);
+ 
+ 	if (err) {
+ 		ret = NOPFN_SIGBUS;
+ 		goto out_unlock;
+ 	}
+ 
+ 	page_offset = (address - vma->vm_start) >> PAGE_SHIFT;
+ 
+ 	if (bus_size) {
+ 		struct drm_mem_type_manager *man = &dev->bm.man[bo->mem.mem_type];
+ 
+ 		pfn = ((bus_base + bus_offset) >> PAGE_SHIFT) + page_offset;
+ 		vma->vm_page_prot = drm_io_prot(man->drm_bus_maptype, vma);
+ 	} else {
+ 		ttm = bo->ttm;
+ 
+ 		drm_ttm_fixup_caching(ttm);
+ 		page = drm_ttm_get_page(ttm, page_offset);
+ 		if (!page) {
+ 			ret = NOPFN_OOM;
+ 			goto out_unlock;
+ 		}
+ 		pfn = page_to_pfn(page);
+ 		vma->vm_page_prot = (bo->mem.flags & DRM_BO_FLAG_CACHED) ?
+ 			vm_get_page_prot(vma->vm_flags) :
+ 			drm_io_prot(_DRM_TTM, vma);
+ 	}
+ 
+ 	err = vm_insert_pfn(vma, address, pfn);
+ 	if (err) {
+ 		ret = (err != -EAGAIN) ? NOPFN_OOM : NOPFN_REFAULT;
+ 		goto out_unlock;
+ 	}
+ out_unlock:
+ 	BUG_ON(bo->priv_flags & _DRM_BO_FLAG_UNLOCKED);
+ 	mutex_unlock(&bo->mutex);
+ 	drm_bo_read_unlock(&dev->bm.bm_lock);
+ 	return ret;
+ }
+ #endif
+ #endif
diff --cc linux-core/i915_gem_debug.c
index a2d6f28,0000000..6d50e5b
mode 100644,000000..100644
--- a/linux-core/i915_gem_debug.c
+++ b/linux-core/i915_gem_debug.c
@@@ -1,202 -1,0 +1,202 @@@
 +/*
 + * Copyright Â© 2008 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the "Software"),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 + * IN THE SOFTWARE.
 + *
 + * Authors:
 + *    Keith Packard <ke...@ke...>
 + *
 + */
 +
 +#include "drmP.h"
 +#include "drm.h"
 +#include "drm_compat.h"
 +#include "i915_drm.h"
 +#include "i915_drv.h"
 +
 +#if WATCH_INACTIVE
 +void
 +i915_verify_inactive(struct drm_device *dev, char *file, int line)
 +{
- 	drm_i915_private_t *dev_priv = dev->dev_private;
++	struct drm_i915_private *dev_priv = dev->dev_private;
 +	struct drm_gem_object *obj;
 +	struct drm_i915_gem_object *obj_priv;
 +
 +	list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 +		obj = obj_priv->obj;
 +		if (obj_priv->pin_count || obj_priv->active ||
 +		    (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
 +					   I915_GEM_DOMAIN_GTT)))
 +			DRM_ERROR("inactive %p (p %d a %d w %x)  %s:%d\n",
 +				  obj,
 +				  obj_priv->pin_count, obj_priv->active,
 +				  obj->write_domain, file, line);
 +	}
 +}
 +#endif /* WATCH_INACTIVE */
 +
 +
 +#if WATCH_BUF | WATCH_EXEC | WATCH_PWRITE
 +static void
 +i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
 +		   uint32_t bias, uint32_t mark)
 +{
 +	uint32_t *mem = kmap_atomic(page, KM_USER0);
 +	int i;
 +	for (i = start; i < end; i += 4)
 +		DRM_INFO("%08x: %08x%s\n",
 +			  (int) (bias + i), mem[i / 4],
 +			  (bias + i == mark) ? " ********" : "");
 +	kunmap_atomic(mem, KM_USER0);
 +	/* give syslog time to catch up */
 +	msleep(1);
 +}
 +
 +void
 +i915_gem_dump_object(struct drm_gem_object *obj, int len,
 +		     const char *where, uint32_t mark)
 +{
 +	struct drm_i915_gem_object *obj_priv = obj->driver_private;
 +	int page;
 +
 +	DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset);
 +	for (page = 0; page < (len + PAGE_SIZE-1) / PAGE_SIZE; page++) {
 +		int page_len, chunk, chunk_len;
 +
 +		page_len = len - page * PAGE_SIZE;
 +		if (page_len > PAGE_SIZE)
 +			page_len = PAGE_SIZE;
 +
 +		for (chunk = 0; chunk < page_len; chunk += 128) {
 +			chunk_len = page_len - chunk;
 +			if (chunk_len > 128)
 +				chunk_len = 128;
 +			i915_gem_dump_page(obj_priv->page_list[page],
 +					   chunk, chunk + chunk_len,
 +					   obj_priv->gtt_offset +
 +					   page * PAGE_SIZE,
 +					   mark);
 +		}
 +	}
 +}
 +#endif
 +
 +#if WATCH_LRU
 +void
 +i915_dump_lru(struct drm_device *dev, const char *where)
 +{
- 	drm_i915_private_t		*dev_priv = dev->dev_private;
++	struct drm_i915_private		*dev_priv = dev->dev_private;
 +	struct drm_i915_gem_object	*obj_priv;
 +
 +	DRM_INFO("active list %s {\n", where);
 +	list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
 +			    list)
 +	{
 +		DRM_INFO("    %p: %08x\n", obj_priv,
 +			 obj_priv->last_rendering_seqno);
 +	}
 +	DRM_INFO("}\n");
 +	DRM_INFO("flushing list %s {\n", where);
 +	list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
 +			    list)
 +	{
 +		DRM_INFO("    %p: %08x\n", obj_priv,
 +			 obj_priv->last_rendering_seqno);
 +	}
 +	DRM_INFO("}\n");
 +	DRM_INFO("inactive %s {\n", where);
 +	list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 +		DRM_INFO("    %p: %08x\n", obj_priv,
 +			 obj_priv->last_rendering_seqno);
 +	}
 +	DRM_INFO("}\n");
 +}
 +#endif
 +
 +
 +#if WATCH_COHERENCY
 +void
 +i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
 +{
 +	struct drm_device *dev = obj->dev;
 +	struct drm_i915_gem_object *obj_priv = obj->driver_private;
 +	int page;
 +	uint32_t *gtt_mapping;
 +	uint32_t *backing_map = NULL;
 +	int bad_count = 0;
 +
 +	DRM_INFO("%s: checking coherency of object %p@0x%08x (%d, %dkb):\n",
 +		 __func__, obj, obj_priv->gtt_offset, handle,
 +		 obj->size / 1024);
 +
 +	gtt_mapping = ioremap(dev->agp->base + obj_priv->gtt_offset,
 +			      obj->size);
 +	if (gtt_mapping == NULL) {
 +		DRM_ERROR("failed to map GTT space\n");
 +		return;
 +	}
 +
 +	for (page = 0; page < obj->size / PAGE_SIZE; page++) {
 +		int i;
 +
 +		backing_map = kmap_atomic(obj_priv->page_list[page], KM_USER0);
 +
 +		if (backing_map == NULL) {
 +			DRM_ERROR("failed to map backing page\n");
 +			goto out;
 +		}
 +
 +		for (i = 0; i < PAGE_SIZE / 4; i++) {
 +			uint32_t cpuval = backing_map[i];
 +			uint32_t gttval = readl(gtt_mapping +
 +						page * 1024 + i);
 +
 +			if (cpuval != gttval) {
 +				DRM_INFO("incoherent CPU vs GPU at 0x%08x: "
 +					 "0x%08x vs 0x%08x\n",
 +					 (int)(obj_priv->gtt_offset +
 +					       page * PAGE_SIZE + i * 4),
 +					 cpuval, gttval);
 +				if (bad_count++ >= 8) {
 +					DRM_INFO("...\n");
 +					goto out;
 +				}
 +			}
 +		}
 +		kunmap_atomic(backing_map, KM_USER0);
 +		backing_map = NULL;
 +	}
 +
 + out:
 +	if (backing_map != NULL)
 +		kunmap_atomic(backing_map, KM_USER0);
 +	iounmap(gtt_mapping);
 +
 +	/* give syslog time to catch up */
 +	msleep(1);
 +
 +	/* Directly flush the object, since we just loaded values with the CPU
 +	 * from the backing pages and we don't want to disturb the cache
 +	 * management that we're trying to observe.
 +	 */
 +
 +	i915_gem_clflush_object(obj);
 +}
 +#endif
diff --cc linux-core/i915_gem_tiling.c
index c5825fb,0000000..3ac1f35
mode 100644,000000..100644
--- a/linux-core/i915_gem_tiling.c
+++ b/linux-core/i915_gem_tiling.c
@@@ -1,309 -1,0 +1,310 @@@
 +/*
 + * Copyright Â© 2008 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the "Software"),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 + * IN THE SOFTWARE.
 + *
 + * Authors:
 + *    Eric Anholt <er...@an...>
 + *
 + */
 +
 +#include "drmP.h"
 +#include "drm.h"
 +#include "i915_drm.h"
 +#include "i915_drv.h"
 +
 +/** @file i915_gem_tiling.c
 + *
 + * Support for managing tiling state of buffer objects.
 + *
 + * The idea behind tiling is to increase cache hit rates by rearranging
 + * pixel data so that a group of pixel accesses are in the same cacheline.
 + * Performance improvement from doing this on the back/depth buffer are on
 + * the order of 30%.
 + *
 + * Intel architectures make this somewhat more complicated, though, by
 + * adjustments made to addressing of data when the memory is in interleaved
 + * mode (matched pairs of DIMMS) to improve memory bandwidth.
 + * For interleaved memory, the CPU sends every sequential 64 bytes
 + * to an alternate memory channel so it can get the bandwidth from both.
 + *
 + * The GPU also rearranges its accesses for increased bandwidth to interleaved
 + * memory, and it matches what the CPU does for non-tiled.  However, when tiled
 + * it does it a little differently, since one walks addresses not just in the
 + * X direction but also Y.  So, along with alternating channels when bit
 + * 6 of the address flips, it also alternates when other bits flip --  Bits 9
 + * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
 + * are common to both the 915 and 965-class hardware.
 + *
 + * The CPU also sometimes XORs in higher bits as well, to improve
 + * bandwidth doing strided access like we do so frequently in graphics.  This
 + * is called "Channel XOR Randomization" in the MCH documentation.  The result
 + * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
 + * decode.
 + *
 + * All of this bit 6 XORing has an effect on our memory management,
 + * as we need to make sure that the 3d driver can correctly address object
 + * contents.
 + *
 + * If we don't have interleaved memory, all tiling is safe and no swizzling is
 + * required.
 + *
 + * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
 + * 17 is not just a page offset, so as we page an objet out and back in,
 + * individual pages in it will have different bit 17 addresses, resulting in
 + * each 64 bytes being swapped with its neighbor!
 + *
 + * Otherwise, if interleaved, we have to tell the 3d driver what the address
 + * swizzling it needs to do is, since it's writing with the CPU to the pages
 + * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
 + * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
 + * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
 + * to match what the GPU expects.
 + */
 +
 +/**
 + * Detects bit 6 swizzling of address lookup between IGD access and CPU
 + * access through main memory.
 + */
 +void
 +i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 +{
 +	struct drm_i915_private *dev_priv = dev->dev_private;
 +	struct pci_dev *bridge;
 +	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 +	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 +	int mchbar_offset;
 +	char __iomem *mchbar;
 +	int ret;
 +
 +	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 +	if (bridge == NULL) {
 +		DRM_ERROR("Couldn't get bridge device\n");
 +		return;
 +	}
 +
 +	ret = pci_enable_device(bridge);
 +	if (ret != 0) {
 +		DRM_ERROR("pci_enable_device failed: %d\n", ret);
 +		return;
 +	}
 +
 +	if (IS_I965G(dev))
 +		mchbar_offset = 0x48;
 +	else
 +		mchbar_offset = 0x44;
 +
 +	/* Use resource 2 for our BAR that's stashed in a nonstandard location,
 +	 * since the bridge would only ever use standard BARs 0-1 (though it
 +	 * doesn't anyway)
 +	 */
- 	ret = pci_read_base(bridge, mchbar_offset, &bridge->resource[2]);
++	ret = pci_read_base(bridge, pci_bar_mem64, &bridge->resource[2],
++			    mchbar_offset);
 +	if (ret != 0) {
 +		DRM_ERROR("pci_read_base failed: %d\n", ret);
 +		return;
 +	}
 +
 +	mchbar = ioremap(pci_resource_start(bridge, 2),
 +			 pci_resource_len(bridge, 2));
 +	if (mchbar == NULL) {
 +		DRM_ERROR("Couldn't map MCHBAR to determine tile swizzling\n");
 +		return;
 +	}
 +
 +	if (IS_I965G(dev) && !IS_I965GM(dev)) {
 +		uint32_t chdecmisc;
 +
 +		/* On the 965, channel interleave appears to be determined by
 +		 * the flex bit.  If flex is set, then the ranks (sides of a
 +		 * DIMM) of memory will be "stacked" (physical addresses walk
 +		 * through one rank then move on to the next, flipping channels
 +		 * or not depending on rank configuration).  The GPU in this
 +		 * case does exactly the same addressing as the CPU.
 +		 *
 +		 * Unlike the 945, channel randomization based does not
 +		 * appear to be available.
 +		 *
 +		 * XXX: While the G965 doesn't appear to do any interleaving
 +		 * when the DIMMs are not exactly matched, the G4x chipsets
 +		 * might be for "L-shaped" configurations, and will need to be
 +		 * detected.
 +		 *
 +		 * L-shaped configuration:
 +		 *
 +		 * +-----+
 +		 * |     |
 +		 * |DIMM2|         <-- non-interleaved
 +		 * +-----+
 +		 * +-----+ +-----+
 +		 * |     | |     |
 +		 * |DIMM0| |DIMM1| <-- interleaved area
 +		 * +-----+ +-----+
 +		 */
 +		chdecmisc = readb(mchbar + CHDECMISC);
 +
 +		if (chdecmisc == 0xff) {
 +			DRM_ERROR("Couldn't read from MCHBAR.  "
 +				  "Disabling tiling.\n");
 +		} else if (chdecmisc & CHDECMISC_FLEXMEMORY) {
 +			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 +			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 +		} else {
 +			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 +			swizzle_y = I915_BIT_6_SWIZZLE_9;
 +		}
 +	} else if (IS_I9XX(dev)) {
 +		uint32_t dcc;
 +
 +		/* On 915-945 and GM965, channel interleave by the CPU is
 +		 * determined by DCC.  The CPU will alternate based on bit 6
 +		 * in interleaved mode, and the GPU will then also alternate
 +		 * on bit 6, 9, and 10 for X, but the CPU may also optionally
 +		 * alternate based on bit 17 (XOR not disabled and XOR
 +		 * bit == 17).
 +		 */
 +		dcc = readl(mchbar + DCC);
 +		switch (dcc & DCC_ADDRESSING_MODE_MASK) {
 +		case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
 +		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
 +			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 +			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 +			break;
 +		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
 +			if (IS_I915G(dev) || IS_I915GM(dev) ||
 +			    dcc & DCC_CHANNEL_XOR_DISABLE) {
 +				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 +				swizzle_y = I915_BIT_6_SWIZZLE_9;
 +			} else if (IS_I965GM(dev)) {
 +				/* GM965 only does bit 11-based channel
 +				 * randomization
 +				 */
 +				swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
 +				swizzle_y = I915_BIT_6_SWIZZLE_9_11;
 +			} else {
 +				/* Bit 17 or perhaps other swizzling */
 +				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 +				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 +			}
 +			break;
 +		}
 +		if (dcc == 0xffffffff) {
 +			DRM_ERROR("Couldn't read from MCHBAR.  "
 +				  "Disabling tiling.\n");
 +			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 +			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 +		}
 +	} else {
 +		/* As far as we know, the 865 doesn't have these bit 6
 +		 * swizzling issues.
 +		 */
 +		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 +		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 +	}
 +
 +	iounmap(mchbar);
 +
 +	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
 +	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 +}
 +
 +/**
 + * Sets the tiling mode of an object, returning the required swizzling of
 + * bit 6 of addresses in the object.
 + */
 +int
 +i915_gem_set_tiling(struct drm_device *dev, void *data,
 +		   struct drm_file *file_priv)
 +{
 +	struct drm_i915_gem_set_tiling *args = data;
 +	struct drm_i915_private *dev_priv = dev->dev_private;
 +	struct drm_gem_object *obj;
 +	struct drm_i915_gem_object *obj_priv;
 +
 +	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 +	if (obj == NULL)
 +		return -EINVAL;
 +	obj_priv = obj->driver_private;
 +
 +	mutex_lock(&dev->struct_mutex);
 +
 +	if (args->tiling_mode == I915_TILING_NONE) {
 +		obj_priv->tiling_mode = I915_TILING_NONE;
 +		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 +	} else {
 +		if (args->tiling_mode == I915_TILING_X)
 +			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 +		else
 +			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 +		/* If we can't handle the swizzling, make it untiled. */
 +		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
 +			args->tiling_mode = I915_TILING_NONE;
 +			args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 +		}
 +	}
 +	obj_priv->tiling_mode = args->tiling_mode;
 +
 +	mutex_unlock(&dev->struct_mutex);
 +
 +	drm_gem_object_unreference(obj);
 +
 +	return 0;
 +}
 +
 +/**
 + * Returns the current tiling mode and required bit 6 swizzling for the object.
 + */
 +int
 +i915_gem_get_tiling(struct drm_device *dev, void *data,
 +		   struct drm_file *file_priv)
 +{
 +	struct drm_i915_gem_get_tiling *args = data;
 +	struct drm_i915_private *dev_priv = dev->dev_private;
 +	struct drm_gem_object *obj;
 +	struct drm_i915_gem_object *obj_priv;
 +
 +	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 +	if (obj == NULL)
 +		return -EINVAL;
 +	obj_priv = obj->driver_private;
 +
 +	mutex_lock(&dev->struct_mutex);
 +
 +	args->tiling_mode = obj_priv->tiling_mode;
 +	switch (obj_priv->tiling_mode) {
 +	case I915_TILING_X:
 +		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 +		break;
 +	case I915_TILING_Y:
 +		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 +		break;
 +	case I915_TILING_NONE:
 +		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 +		break;
 +	default:
 +		DRM_ERROR("unknown tiling mode\n");
 +	}
 +
 +	mutex_unlock(&dev->struct_mutex);
 +
 +	drm_gem_object_unreference(obj);
 +
 +	return 0;
 +}
diff --cc shared-core/i915_drv.h
index 2d18655,421572c..087c6d6
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@@ -306,96 -267,7 +306,96 @@@ struct drm_i915_private 
  	u8 saveDACMASK;
  	u8 saveDACDATA[256*3]; /* 256 3-byte colors */
  	u8 saveCR[37];
 -} drm_i915_private_t;
 +
 +	struct {
 +		struct drm_mm gtt_space;
 +
 +		/**
 +		 * List of objects currently involved in rendering from the
 +		 * ringbuffer.
 +		 *
 +		 * A reference is held on the buffer while on this list.
 +		 */
 +		struct list_head active_list;
 +
 +		/**
 +		 * List of objects which are not in the ringbuffer but which
 +		 * still have a write_domain which needs to be flushed before
 +		 * unbinding.
 +		 *
 +		 * A reference is held on the buffer while on this list.
 +		 */
 +		struct list_head flushing_list;
 +
 +		/**
 +		 * LRU list of objects which are not in the ringbuffer and
 +		 * are ready to unbind, but are still in the GTT.
 +		 *
 +		 * A reference is not held on the buffer while on this list,
 +		 * as merely being GTT-bound shouldn't prevent its being
 +		 * freed, and we'll pull it off the list in the free path.
 +		 */
 +		struct list_head inactive_list;
 +
 +		/**
 +		 * List of breadcrumbs associated with GPU requests currently
 +		 * outstanding.
 +		 */
 +		struct list_head request_list;
 +
 +		/**
 +		 * We leave the user IRQ off as much as possible,
 +		 * but this means that requests will finish and never
 +		 * be retired once the system goes idle. Set a timer to
 +		 * fire periodically while the ring is running. When it
 +		 * fires, go retire requests.
 +		 */
 +		struct delayed_work retire_work;
 +
 +		uint32_t next_gem_seqno;
 +
 +		/**
 +		 * Waiting sequence number, if any
 +		 */
 +		uint32_t waiting_gem_seqno;
 +
 +		/**
 +		 * Last seq seen at irq time
 +		 */
 +		uint32_t irq_gem_seqno;
 +
 +		/**
 +		 * Flag if the X Server, and thus DRM, is not currently in
 +		 * control of the device.
 +		 *
 +		 * This is set between LeaveVT and EnterVT.  It needs to be
 +		 * replaced with a semaphore.  It also needs to be
 +		 * transitioned away from for kernel modesetting.
 +		 */
 +		int suspended;
 +
 +		/**
 +		 * Flag if the hardware appears to be wedged.
 +		 *
 +		 * This is set when attempts to idle the device timeout.
 +		 * It prevents command submission from occuring and makes
 +		 * every pending request fail
 +		 */
 +		int wedged;
 +
 +		/** Bit 6 swizzling required for X tiling */
 +		uint32_t bit_6_swizzle_x;
 +		/** Bit 6 swizzling required for Y tiling */
 +		uint32_t bit_6_swizzle_y;
 +	} mm;
- } drm_i915_private_t;
++};
 +
 +struct drm_i915_file_private {
 +	struct {
 +		uint32_t last_gem_seqno;
 +		uint32_t last_gem_throttle_seqno;
 +	} mm;
 +};
  
  enum intel_chip_family {
  	CHIP_I8XX = 0x01,
diff --cc shared-core/i915_irq.c
index 00570e1,ae4081f..1b294bb
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@@ -1101,15 -882,63 +1101,62 @@@ int i915_vblank_swap(struct drm_device 
  */
  void i915_driver_irq_preinstall(struct drm_device * dev)
  {
- 	return;
 -	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
++	struct drm_i915_private *dev_priv = dev->dev_private;
+ 
+ 	I915_WRITE16(HWSTAM, 0xeffe);
+ 	I915_WRITE16(IMR, 0x0);
+ 	I915_WRITE16(IER, 0x0);
  }
  
  int i915_driver_irq_postinstall(struct drm_device * dev)
  {
 -	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
++	struct drm_i915_private *dev_priv = dev->dev_private;
+ 	int ret, num_pipes = 2;
+ 
+ 	DRM_SPININIT(&dev_priv->swaps_lock, "swap");
+ 	INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
+ 	dev_priv->swaps_pending = 0;
+ 
+ 	DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
+ 	dev_priv->user_irq_refcount = 0;
 -	dev_priv->irq_enable_reg = 0;
+ 
+ 	ret = drm_vblank_init(dev, num_pipes);
+ 	if (ret)
+ 		return ret;
+ 
+ 	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
+ 	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
+ 
+ 	i915_enable_interrupt(dev);
+ 	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
+ 
+ 	/*
+ 	 * Initialize the hardware status page IRQ location.
+ 	 */
+ 
+ 	I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
  	return 0;
  }
  
  void i915_driver_irq_uninstall(struct drm_device * dev)
  {
- 	return;
 -	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
++	struct drm_i915_private *dev_priv = dev->dev_private;
+ 	u32 temp;
+ 
+ 	if (!dev_priv)
+ 		return;
+ 
+ 	dev_priv->vblank_pipe = 0;
+ 
+ 	dev_priv->irq_enabled = 0;
+ 	I915_WRITE(HWSTAM, 0xffffffff);
+ 	I915_WRITE(IMR, 0xffffffff);
+ 	I915_WRITE(IER, 0x0);
+ 
+ 	temp = I915_READ(PIPEASTAT);
+ 	I915_WRITE(PIPEASTAT, temp);
+ 	temp = I915_READ(PIPEBSTAT);
+ 	I915_WRITE(PIPEBSTAT, temp);
+ 	temp = I915_READ(IIR);
+ 	I915_WRITE(IIR, temp);
  }
commit c7fb19e9b074281f143b0e1c9d054ebcf5ff1091
Merge: 086716c... ac20e14...
Author: Jesse Barnes <jb...@vi...>
Date:   Thu Aug 7 14:02:04 2008 -0700

    Merge branch 'drm-gem' into modesetting-gem

commit ac20e14d2361160cf199dc31c3fe1ffbacdf5bb7
Author: Keith Packard <ke...@ke...>
Date:   Mon Aug 4 23:33:03 2008 -0700

    Switch from shmem_getpage to read_mapping_page

diff --git a/linux-core/i915_gem.c b/linux-core/i915_gem.c
index 354bd0d..35dc5bd 100644
--- a/linux-core/i915_gem.c
+++ b/linux-core/i915_gem.c
@@ -1083,20 +1083,12 @@ i915_gem_object_get_page_list(struct drm_gem_object *obj)
 	inode = obj->filp->f_path.dentry->d_inode;
 	mapping = inode->i_mapping;
 	for (i = 0; i < page_count; i++) {
-		page = find_get_page(mapping, i);
-		if (page == NULL || !PageUptodate(page)) {
-			if (page) {
-				page_cache_release(page);
-				page = NULL;
-			}
-			ret = shmem_getpage(inode, i, &page, SGP_DIRTY, NULL);
-
-			if (ret) {
-				DRM_ERROR("shmem_getpage failed: %d\n", ret);
-				i915_gem_object_free_page_list(obj);
-				return ret;
-			}
-			unlock_page(page);
+		page = read_mapping_page(mapping, i, NULL);
+		if (IS_ERR(page)) {
+			ret = PTR_ERR(page);
+			DRM_ERROR("read_mapping_page failed: %d\n", ret);
+			i915_gem_object_free_page_list(obj);
+			return ret;
 		}
 		obj_priv->page_list[i] = page;
 	}
commit dc0546c87ffc6701802d6141810c24954274e1ac
Author: Keith Packard <ke...@ke...>
Date:   Tue Aug 5 16:06:40 2008 -0700

    [gem-intel] Retiring flush requests should clear flushed write_domains
    
    When i915_gem_retire_request has a flush which matches an object write
    domain, clear the write domain. This will move the object to the inactive
    list rather than the flushing list, avoiding trouble with objects left stuck
    on the flushing list.

diff --git a/linux-core/i915_gem.c b/linux-core/i915_gem.c
index acded2e..354bd0d 100644
--- a/linux-core/i915_gem.c
+++ b/linux-core/i915_gem.c
@@ -661,6 +661,12 @@ i915_gem_retire_request(struct drm_device *dev,
 			 __func__, request->seqno, obj);
 #endif
 
+		/* If this request flushes the write domain,
+		 * clear the write domain from the object now
+		 */
+		if (request->flush_domains & obj->write_domain)
+		    obj->write_domain = 0;
+
 		if (obj->write_domain != 0) {
 			list_move_tail(&obj_priv->list,
 				       &dev_priv->mm.flushing_list);
@@ -760,7 +766,7 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno)
 	if (dev_priv->mm.wedged)
 		ret = -EIO;
 
-	if (ret)
+	if (ret && ret != -ERESTARTSYS)
 		DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
 			  __func__, ret, seqno, i915_get_gem_seqno(dev));
 
@@ -890,13 +896,6 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 		ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
 		if (ret != 0)
 			return ret;
-		if (write_domain) {
-#if WATCH_BUF
-			DRM_INFO("%s: flushed object %p from write domain %08x\n",
-				 __func__, obj, write_domain);
-#endif
-			obj->write_domain = 0;
-		}
 	}
 
 	return 0;
commit ceb3d5e3834452f9d54f974b8066f90168467443
Author: Keith Packard <ke...@ke...>
Date:   Tue Aug 5 14:44:53 2008 -0700

    [gem-intel] Don't clear write_domain until flush completes
    
    In i915_gem_object_wait_rendering, if the object write domain is being
    written by the GPU, the appropriate flushing commands are written to the
    device and an additional request queued to mark that flush. Finally, the
    function blocks on that new request.
    
    The bug was that the write_domain in the object was cleared before the
    function blocked.
    
    If the wait is interrupted by a signal, the flushing commands may still be
    pending. With the current write_domain information lost, the restarted
    syscall will drop right through the write_domain test as that value was
    lost, and so the function will not block at all. Oops.
    
    Fixed by simply moving the write_domain clear until after the wait_request
    succeeds. Note that the restarted system call will generate an additional
    flush sequence and request, but that should be 'harmless', aside from a
    slight performance impact.
    
    Someday we'll track flushing more accurately and clear write_domains more
    efficiently, but for now, this should suffice.
    
    This bug was discovered in the 2d gem development by running x11perf
    -copypixwin500 and noticing that the window got cleared accidentally.

diff --git a/linux-core/i915_gem.c b/linux-core/i915_gem.c
index 70f1151..acded2e 100644
--- a/linux-core/i915_gem.c
+++ b/linux-core/i915_gem.c
@@ -381,6 +381,10 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 		return -EBADF;
 
 	mutex_lock(&dev->struct_mutex);
+#if WATCH_BUF
+	DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
+		 obj, obj->size, args->read_domains, args->write_domain);
+#endif
 	ret = i915_gem_set_domain(obj, file_priv,
 				  args->read_domains, args->write_domain);
 	drm_gem_object_unreference(obj);
@@ -411,8 +415,8 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 	}
 
 #if WATCH_BUF
-	DRM_INFO("%s: sw_finish %d (%p)\n",
-		 __func__, args->handle, obj);
+	DRM_INFO("%s: sw_finish %d (%p %d)\n",
+		 __func__, args->handle, obj, obj->size);
 #endif
 	obj_priv = obj->driver_private;
 
@@ -853,18 +857,18 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 	struct drm_device *dev = obj->dev;
 	struct drm_i915_gem_object *obj_priv = obj->driver_private;
 	int ret;
+	uint32_t write_domain;
 
 	/* If there are writes queued to the buffer, flush and
 	 * create a new seqno to wait for.
 	 */
-	if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
-		uint32_t write_domain = obj->write_domain;
+	write_domain = obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT);
+	if (write_domain) {
 #if WATCH_BUF
 		DRM_INFO("%s: flushing object %p from write domain %08x\n",
 			  __func__, obj, write_domain);
 #endif
 		i915_gem_flush(dev, 0, write_domain);
-		obj->write_domain = 0;
 
 		i915_gem_object_move_to_active(obj);
 		obj_priv->last_rendering_seqno = i915_add_request(dev,
@@ -874,6 +878,7 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 		DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
 #endif
 	}
+
 	/* If there is rendering queued on the buffer being evicted, wait for
 	 * it.
 	 */
@@ -885,6 +890,13 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 		ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
 		if (ret != 0)
 			return ret;
+		if (write_domain) {
+#if WATCH_BUF
+			DRM_INFO("%s: flushed object %p from write domain %08x\n",
+				 __func__, obj, write_domain);
+#endif
+			obj->write_domain = 0;
+		}
 	}
 
 	return 0;
commit 8e41ce17b4ab72f526cc6e9acd75c3fa81a60433
Author: Keith Packard <ke...@ke...>
Date:   Mon Aug 4 00:34:08 2008 -0700

    Expose pin/unpin/set_tiling/flink APIs

diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h
index 1cf0d51..4d33521 100644
--- a/libdrm/intel/intel_bufmgr.h
+++ b/libdrm/intel/intel_bufmgr.h
@@ -61,6 +61,33 @@ struct intel_bufmgr {
     int (*emit_reloc)(dri_bo *reloc_buf,
 		      uint32_t read_domains, uint32_t write_domain,
 		      uint32_t delta, uint32_t offset, dri_bo *target);
+    /**
+     * Pin a buffer to the aperture and fix the offset until unpinned
+     *
+     * \param buf Buffer to pin
+     * \param alignment Required alignment for aperture, in bytes
+     */
+    int (*pin) (dri_bo *buf, uint32_t alignment);
+    /**
+     * Unpin a buffer from the aperture, allowing it to be removed
+     *
+     * \param buf Buffer to unpin
+     */
+    int (*unpin) (dri_bo *buf);
+    /**
+     * Ask that the buffer be placed in tiling mode
+     *
+     * \param buf Buffer to set tiling mode for
+     * \param tiling_mode desired, and returned tiling mode
+     */
+    int (*set_tiling) (dri_bo *bo, uint32_t *tiling_mode);
+    /**
+     * Create a visible name for a buffer which can be used by other apps
+     *
+     * \param buf Buffer to create a name for
+     * \param name Returned name
+     */
+    int (*flink) (dri_bo *buf, uint32_t *name);
 };
 
 /* intel_bufmgr_gem.c */
@@ -91,5 +118,13 @@ int intel_bo_emit_reloc(dri_bo *reloc_buf,
 			uint32_t read_domains, uint32_t write_domain,
 			uint32_t delta, uint32_t offset, dri_bo *target_buf);
 
+int intel_bo_pin(dri_bo *buf, uint32_t alignment);
+
+int intel_bo_unpin(dri_bo *buf);
+
+int intel_bo_set_tiling(dri_bo *buf, uint32_t *tiling_mode);
+
+int intel_bo_flink(dri_bo *buf, uint32_t *name);
+
 #endif /* INTEL_BUFMGR_GEM_H */
 
diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c
index cdc2a7a..22f8695 100644
--- a/libdrm/intel/intel_bufmgr_gem.c
+++ b/libdrm/intel/intel_bufmgr_gem.c
@@ -768,6 +768,81 @@ dri_gem_post_submit(dri_bo *batch_buf)
     bufmgr_gem->exec_count = 0;
 }
 
+static int
+dri_gem_pin(dri_bo *bo, uint32_t alignment)
+{
+    dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+    dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+    struct drm_i915_gem_pin pin;
+    int ret;
+
+    pin.handle = bo_gem->gem_handle;
+    pin.alignment = alignment;
+
+    ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PIN, &pin);
+    if (ret != 0)
+	return -errno;
+
+    bo->offset = pin.offset;
+    return 0;
+}
+
+static int
+dri_gem_unpin(dri_bo *bo)
+{
+    dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+    dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+    struct drm_i915_gem_unpin unpin;
+    int ret;
+
+    unpin.handle = bo_gem->gem_handle;
+
+    ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
+    if (ret != 0)
+	return -errno;
+
+    return 0;
+}
+
+static int
+dri_gem_set_tiling(dri_bo *bo, uint32_t *tiling_mode)
+{
+    dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+    dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+    struct drm_i915_gem_set_tiling set_tiling;
+    int ret;
+
+    set_tiling.handle = bo_gem->gem_handle;
+    set_tiling.tiling_mode = *tiling_mode;
+
+    ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
+    if (ret != 0) {
+	*tiling_mode = I915_TILING_NONE;
+	return -errno;
+    }
+
+    *tiling_mode = set_tiling.tiling_mode;
+    return 0;
+}
+
+static int
+dri_gem_flink(dri_bo *bo, uint32_t *name)
+{
+    dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+    dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+    struct drm_gem_flink flink;
+    int ret;
+
+    flink.handle = bo_gem->gem_handle;
+
+    ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
+    if (ret != 0)
+	return -errno;
+
+    *name = flink.name;
+    return 0;
+}
+
 /**
  * Enables unlimited caching of buffer objects for reuse.
  *
@@ -832,6 +907,10 @@ intel_bufmgr_gem_init(int fd, int batch_size)
     bufmgr_gem->bufmgr.debug = 0;
     bufmgr_gem->bufmgr.check_aperture_space = dri_gem_check_aperture_space;
     bufmgr_gem->intel_bufmgr.emit_reloc = dri_gem_emit_reloc;
+    bufmgr_gem->intel_bufmgr.pin = dri_gem_pin;
+    bufmgr_gem->intel_bufmgr.unpin = dri_gem_unpin;
+    bufmgr_gem->intel_bufmgr.set_tiling = dri_gem_set_tiling;
+    bufmgr_gem->intel_bufmgr.flink = dri_gem_flink;
     /* Initialize the linked lists for BO reuse cache. */
     for (i = 0; i < INTEL_GEM_BO_BUCKETS; i++)
 	bufmgr_gem->cache_bucket[i].tail = &bufmgr_gem->cache_bucket[i].head;
@@ -851,3 +930,55 @@ intel_bo_emit_reloc(dri_bo *reloc_buf,
     return intel_bufmgr->emit_reloc(reloc_buf, read_domains, write_domain,
 				    delta, offset, target_buf);
 }
+
+int
+intel_bo_pin(dri_bo *bo, uint32_t alignment)
+{
+    struct intel_bufmgr *intel_bufmgr;
+
+    intel_bufmgr = (struct intel_bufmgr *)(bo->bufmgr + 1);
+
+    if (intel_bufmgr->pin)
+	return intel_bufmgr->pin(bo, alignment);
+
+    return 0;
+}
+
+int
+intel_bo_unpin(dri_bo *bo)
+{
+    struct intel_bufmgr *intel_bufmgr;
+
+    intel_bufmgr = (struct intel_bufmgr *)(bo->bufmgr + 1);
+
+    if (intel_bufmgr->unpin)
+	return intel_bufmgr->unpin(bo);
+
+    return 0;
+}
+
+int intel_bo_set_tiling(dri_bo *bo, uint32_t *tiling_mode)
+{
+    struct intel_bufmgr *intel_bufmgr;
+
+    intel_bufmgr = (struct intel_bufmgr *)(bo->bufmgr + 1);
+
+    if (intel_bufmgr->set_tiling)
+	return intel_bufmgr->set_tiling (bo, tiling_mode);
+
+    *tiling_mode = I915_TILING_NONE;
+    return 0;
+}
+
+int intel_bo_flink(dri_bo *bo, uint32_t *name)
+{
+    struct intel_bufmgr *intel_bufmgr;
+
+    intel_bufmgr = (struct intel_bufmgr *)(bo->bufmgr + 1);
+
+    if (intel_bufmgr->flink)
+	return intel_bufmgr->flink (bo, name);
+
+    return -ENODEV;
+}
+
commit 4585787bd1a1d782b9e7c06095f98d09165b8c23
Author: Dave Airlie <ai...@li...>
Date:   Fri Aug 1 07:43:58 2008 +1000

    Revert "i915: Move all of the irq install/uninstall to load time."
    
    This reverts commit 965a72202b439068e62ac341990f51953457b202.
    
    Please re-do over properly

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 47f1f46..852b243 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -1010,7 +1010,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 {
 	struct drm_i915_private *dev_priv;
 	unsigned long base, size;
-	int ret = 0, num_pipes = 2, mmio_bar = IS_I9XX(dev) ? 0 : 1;
+	int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
 
 	/* i915 has 4 more counters */
 	dev->counters += 4;
@@ -1043,57 +1043,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 #endif
 #endif
 
-	I915_WRITE16(HWSTAM, 0xeffe);
-	I915_WRITE16(IMR, 0x0);
-	I915_WRITE16(IER, 0x0);
-
-	DRM_SPININIT(&dev_priv->swaps_lock, "swap");
-	INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
-	dev_priv->swaps_pending = 0;
-
-	DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
-	dev_priv->user_irq_refcount = 0;
-	dev_priv->irq_enable_reg = 0;
-
-	ret = drm_vblank_init(dev, num_pipes);
-	if (ret)
-		return ret;
-
-	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
-	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
-
-	i915_enable_interrupt(dev);
-	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
-
-	/*
-	 * Initialize the hardware status page IRQ location.
-	 */
-
-	I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
-
 	return ret;
 }
 
 int i915_driver_unload(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 temp;
-
-	if (dev_priv) {
-		dev_priv->vblank_pipe = 0;
-
-		dev_priv->irq_enabled = 0;
-		I915_WRITE(HWSTAM, 0xffffffff);
-		I915_WRITE(IMR, 0xffffffff);
-		I915_WRITE(IER, 0x0);
-
-		temp = I915_READ(PIPEASTAT);
-		I915_WRITE(PIPEASTAT, temp);
-		temp = I915_READ(PIPEBSTAT);
-		I915_WRITE(PIPEBSTAT, temp);
-		temp = I915_READ(IIR);
-		I915_WRITE(IIR, temp);
-	}
 
 	if (dev_priv->mmio_map)
 		drm_rmmap(dev, dev_priv->mmio_map);
diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index a77fcf0..421572c 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -307,7 +307,6 @@ extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 extern int i915_driver_irq_postinstall(struct drm_device * dev);
 extern void i915_driver_irq_uninstall(struct drm_device * dev);
-extern void i915_enable_interrupt(struct drm_device *dev);
 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index d507d76..ae4081f 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -672,7 +672,7 @@ void i915_disable_vblank(struct drm_device *dev, int plane)
 	}
 }
 
-void i915_enable_interrupt (struct drm_device *dev)
+static void i915_enable_interrupt (struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	
@@ -882,15 +882,63 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
 */
 void i915_driver_irq_preinstall(struct drm_device * dev)
 {
-	return;
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+	I915_WRITE16(HWSTAM, 0xeffe);
+	I915_WRITE16(IMR, 0x0);
+	I915_WRITE16(IER, 0x0);
 }
 
 int i915_driver_irq_postinstall(struct drm_device * dev)
 {
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int ret, num_pipes = 2;
+
+	DRM_SPININIT(&dev_priv->swaps_lock, "swap");
+	INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
+	dev_priv->swaps_pending = 0;
+
+	DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
+	dev_priv->user_irq_refcount = 0;
+	dev_priv->irq_enable_reg = 0;
+
+	ret = drm_vblank_init(dev, num_pipes);
+	if (ret)
+		return ret;
+
+	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
+	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
+
+	i915_enable_interrupt(dev);
+	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
+
+	/*
+	 * Initialize the hardware status page IRQ location.
+	 */
+
+	I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
 	return 0;
 }
 
 void i915_driver_irq_uninstall(struct drm_device * dev)
 {
-	return;
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	u32 temp;
+
+	if (!dev_priv)
+		return;
+
+	dev_priv->vblank_pipe = 0;
+
+	dev_priv->irq_enabled = 0;
+	I915_WRITE(HWSTAM, 0xffffffff);
+	I915_WRITE(IMR, 0xffffffff);
+	I915_WRITE(IER, 0x0);
+
+	temp = I915_READ(PIPEASTAT);
+	I915_WRITE(PIPEASTAT, temp);
+	temp = I915_READ(PIPEBSTAT);
+	I915_WRITE(PIPEBSTAT, temp);
+	temp = I915_READ(IIR);
+	I915_WRITE(IIR, temp);
 }
commit 10d5b037b85706037df89bf0275436797e4eb559
Author: Dave Airlie <ai...@re...>
Date:   Thu Jul 31 13:12:36 2008 +1000

    drm: add fault handler support so as to be more like possible upstream

diff --git a/linux-core/drm_compat.c b/linux-core/drm_compat.c
index 3d082e7..c4ebc2f 100644
--- a/linux-core/drm_compat.c
+++ b/linux-core/drm_compat.c
@@ -759,3 +759,102 @@ EXPORT_SYMBOL(kmap_atomic_prot_pfn);
 
 #endif
 
+#ifdef DRM_FULL_MM_COMPAT
+#ifdef DRM_NO_FAULT
+unsigned long drm_bo_vm_nopfn(struct vm_area_struct *vma,
+			      unsigned long address)
+{
+	struct drm_buffer_object *bo = (struct drm_buffer_object *) vma->vm_private_data;
+	unsigned long page_offset;
+	struct page *page = NULL;
+	struct drm_ttm *ttm;
+	struct drm_device *dev;
+	unsigned long pfn;
+	int err;
+	unsigned long bus_base;
+	unsigned long bus_offset;
+	unsigned long bus_size;
+	unsigned long ret = NOPFN_REFAULT;
+
+	if (address > vma->vm_end)
+		return NOPFN_SIGBUS;
+
+	dev = bo->dev;
+	err = drm_bo_read_lock(&dev->bm.bm_lock, 1);
+	if (err)
+		return NOPFN_REFAULT;
+
+	err = mutex_lock_interruptible(&bo->mutex);
+	if (err) {
+		drm_bo_read_unlock(&dev->bm.bm_lock);
+		return NOPFN_REFAULT;
+	}
+
+	err = drm_bo_wait(bo, 0, 1, 0, 1);
+	if (err) {
+		ret = (err != -EAGAIN) ? NOPFN_SIGBUS : NOPFN_REFAULT;
+		bo->priv_flags &= ~_DRM_BO_FLAG_UNLOCKED;
+		goto out_unlock;
+	}
+
+	bo->priv_flags &= ~_DRM_BO_FLAG_UNLOCKED;
+
+	/*
+	 * If buffer happens to be in a non-mappable location,
+	 * move it to a mappable.
+	 */
+
+	if (!(bo->mem.flags & DRM_BO_FLAG_MAPPABLE)) {
+		uint32_t new_flags = bo->mem.proposed_flags |
+			DRM_BO_FLAG_MAPPABLE |
+			DRM_BO_FLAG_FORCE_MAPPABLE;
+		err = drm_bo_move_buffer(bo, new_flags, 0, 0);
+		if (err) {
+			ret = (err != -EAGAIN) ? NOPFN_SIGBUS : NOPFN_REFAULT;
+			goto out_unlock;
+		}
+	}
+
+	err = drm_bo_pci_offset(dev, &bo->mem, &bus_base, &bus_offset,
+				&bus_size);
+
+	if (err) {
+		ret = NOPFN_SIGBUS;
+		goto out_unlock;
+	}
+
+	page_offset = (address - vma->vm_start) >> PAGE_SHIFT;
+
+	if (bus_size) {
+		struct drm_mem_type_manager *man = &dev->bm.man[bo->mem.mem_type];
+
+		pfn = ((bus_base + bus_offset) >> PAGE_SHIFT) + page_offset;
+		vma->vm_page_prot = drm_io_prot(man->drm_bus_maptype, vma);
+	} else {
+		ttm = bo->ttm;
+
+		drm_ttm_fixup_caching(ttm);
+		page = drm_ttm_get_page(ttm, page_offset);
+		if (!page) {
+			ret = NOPFN_OOM;
+			goto out_unlock;
+		}
+		pfn = page_to_pfn(page);
+		vma->vm_page_prot = (bo->mem.flags & DRM_BO_FLAG_CACHED) ?
+			vm_get_page_prot(vma->vm_flags) :
+			drm_io_prot(_DRM_TTM, vma);
+	}
+
+	err = vm_insert_pfn(vma, address, pfn);
+	if (err) {
+		ret = (err != -EAGAIN) ? NOPFN_OOM : NOPFN_REFAULT;
+		goto out_unlock;
+	}
+out_unlock:
+	BUG_ON(bo->priv_flags & _DRM_BO_FLAG_UNLOCKED);
+	mutex_unlock(&bo->mutex);
+	drm_bo_read_unlock(&dev->bm.bm_lock);
+	return ret;
+}
+#endif
+#endif
diff --git a/linux-core/drm_compat.h b/linux-core/drm_compat.h
index 3339219..efeee83 100644
--- a/linux-core/drm_compat.h
+++ b/linux-core/drm_compat.h
@@ -312,6 +312,9 @@ extern int drm_bo_map_bound(struct vm_area_struct *vma);
 /* fixme when functions are upstreamed - upstreamed for 2.6.23 */
 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23))
 #define DRM_IDR_COMPAT_FN
+#define DRM_NO_FAULT
+extern unsigned long drm_bo_vm_nopfn(struct vm_area_struct *vma,
+				     unsigned long address);
 #endif
 #ifdef DRM_IDR_COMPAT_FN
 int idr_for_each(struct idr *idp,
diff --git a/linux-core/drm_vm.c b/linux-core/drm_vm.c
index 6618c0a..0d5242d 100644
--- a/linux-core/drm_vm.c
+++ b/linux-core/drm_vm.c
@@ -685,8 +685,8 @@ EXPORT_SYMBOL(drm_mmap);
  * \c Pagefault method for buffer objects.
  *
  * \param vma Virtual memory area.
- * \param address File offset.
- * \return Error or refault. The pfn is manually inserted.
+ * \param vmf vm fault data
+ * \return Error or VM_FAULT_NOPAGE:. The pfn is manually inserted.
  *
  * It's important that pfns are inserted while holding the bo->mutex lock.
  * otherwise we might race with unmap_mapping_range() which is always
@@ -699,8 +699,8 @@ EXPORT_SYMBOL(drm_mmap);
  */
 
 #ifdef DRM_FULL_MM_COMPAT
-static unsigned long drm_bo_vm_nopfn(struct vm_area_struct *vma,
-				     unsigned long address)
+static int drm_bo_vm_fault(struct vm_area_struct *vma,
+				     struct vm_fault *vmf)
 {
 	struct drm_buffer_object *bo = (struct drm_buffer_object *) vma->vm_private_data;
 	unsigned long page_offset;
@@ -712,25 +712,22 @@ static unsigned long drm_bo_vm_nopfn(struct vm_area_struct *vma,
 	unsigned long bus_base;
 	unsigned long bus_offset;
 	unsigned long bus_size;
-	unsigned long ret = NOPFN_REFAULT;
-
-	if (address > vma->vm_end)
-		return NOPFN_SIGBUS;
+	unsigned long ret = VM_FAULT_NOPAGE;
 
 	dev = bo->dev;
 	err = drm_bo_read_lock(&dev->bm.bm_lock, 1);
 	if (err)
-		return NOPFN_REFAULT;
+		return VM_FAULT_NOPAGE;
 
 	err = mutex_lock_interruptible(&bo->mutex);
 	if (err) {
 		drm_bo_read_unlock(&dev->bm.bm_lock);
-		return NOPFN_REFAULT;
+		return VM_FAULT_NOPAGE;
 	}
 
 	err = drm_bo_wait(bo, 0, 1, 0, 1);
 	if (err) {
-		ret = (err != -EAGAIN) ? NOPFN_SIGBUS : NOPFN_REFAULT;
+		ret = (err != -EAGAIN) ? VM_FAULT_SIGBUS : VM_FAULT_NOPAGE;
 		bo->priv_flags &= ~_DRM_BO_FLAG_UNLOCKED;
 		goto out_unlock;
 	}
@@ -748,7 +745,7 @@ static unsigned long drm_bo_vm_nopfn(struct vm_area_struct *vma,
 			DRM_BO_FLAG_FORCE_MAPPABLE;
 		err = drm_bo_move_buffer(bo, new_flags, 0, 0);
 		if (err) {
-			ret = (err != -EAGAIN) ? NOPFN_SIGBUS : NOPFN_REFAULT;
+			ret = (err != -EAGAIN) ? VM_FAULT_SIGBUS : VM_FAULT_NOPAGE;
 			goto out_unlock;
 		}
 	}
@@ -757,11 +754,11 @@ static unsigned long drm_bo_vm_nopfn(struct vm_area_struct *vma,
 				&bus_size);
 
 	if (err) {
-		ret = NOPFN_SIGBUS;
+		ret = VM_FAULT_SIGBUS;
 		goto out_unlock;
 	}
 
-	page_offset = (address - vma->vm_start) >> PAGE_SHIFT;
+	page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> PAGE_SHIFT;
 
 	if (bus_size) {
 		struct drm_mem_type_manager *man = &dev->bm.man[bo->mem.mem_type];
@@ -774,7 +771,7 @@ static unsigned long drm_bo_vm_nopfn(struct vm_area_struct *vma,
 		drm_ttm_fixup_caching(ttm);
 		page = drm_ttm_get_page(ttm, page_offset);
 		if (!page) {
-			ret = NOPFN_OOM;
+			ret = VM_FAULT_OOM;
 			goto out_unlock;
 		}
 		pfn = page_to_pfn(page);
@@ -783,9 +780,9 @@ static unsigned long drm_bo_vm_nopfn(struct vm_area_struct *vma,
 			drm_io_prot(_DRM_TTM, vma);
 	}
 
-	err = vm_insert_pfn(vma, address, pfn);
+	err = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
 	if (err) {
-		ret = (err != -EAGAIN) ? NOPFN_OOM : NOPFN_REFAULT;
+		ret = (err != -EAGAIN) ? VM_FAULT_OOM : VM_FAULT_NOPAGE;
 		goto out_unlock;
 	}
 out_unlock:
@@ -849,8 +846,12 @@ static void drm_bo_vm_close(struct vm_area_struct *vma)
 
 static struct vm_operations_struct drm_bo_vm_ops = {
 #ifdef DRM_FULL_MM_COMPAT
+#ifdef DRM_NO_FAULT
 	.nopfn = drm_bo_vm_nopfn,
 #else
+	.fault = drm_bo_vm_fault,
+#endif
+#else
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19))
 	.nopfn = drm_bo_vm_nopfn,
 #else




Thread: drm: Branch 'modesetting-gem' - 8 commits

dri-patches