From: <ma...@ke...> - 2006-10-14 14:30:31
|
shared-core/nouveau_fifo.c | 29 ++++++++++++++++++++++------- shared-core/nouveau_irq.c | 34 ++++++++++++++++++++++++---------- 2 files changed, 46 insertions(+), 17 deletions(-) New commits: diff-tree 2c5b91aecf3d21684ffca758c034cd9a8ed2155d (from 3a0cd7c7e221f625585675490f626de8677a9dc7) Author: Stephane Marchesin <mar...@ic...> Date: Sat Oct 14 16:36:11 2006 +0200 Again more work on context switches. They work, sometimes. And when they do they seem to screw up the PGRAPH state. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 6de6a61..5b8cabd 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -70,6 +70,7 @@ static void nouveau_fifo_init(drm_device DRM_DEBUG("%s: setting FIFO %d active\n", __func__, dev_priv->cur_fifo); + // FIXME remove all the stuff that's done in nouveau_fifo_alloc NV_WRITE(NV_PFIFO_CACHES, 0x00000000); NV_WRITE(NV_PFIFO_MODE, 0x00000000); @@ -226,6 +227,9 @@ static int nouveau_fifo_alloc(drm_device /* disable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000000); + NV_WRITE(NV_PFIFO_CACH1_DMAPSH, NV_READ(NV_PFIFO_CACH1_DMAPSH)&(~0x1)); + NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000); + NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); switch(dev_priv->card_type) { @@ -273,10 +277,6 @@ static int nouveau_fifo_alloc(drm_device #endif } - /* disable the pusher ? */ - NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0); - NV_WRITE(NV_PFIFO_CACH1_PSH0, 0); - /* enable the fifo dma operation */ NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel)); @@ -291,10 +291,23 @@ static int nouveau_fifo_alloc(drm_device NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base); NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base); NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base); + NV_WRITE(NV_PFIFO_CACH1_DMAI, dev_priv->cmdbuf_obj->instance >> 4); + NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); + NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); - /* reenable the pusher ? */ - NV_WRITE(NV_PFIFO_CACH1_PSH0, 1); - NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 1); + NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); + NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); + NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000); + NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000); +#ifdef __BIG_ENDIAN + NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); +#else + NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); +#endif + NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001); + NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001); + NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); + NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); /* reenable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000001); diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index c3755d7..da68868 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -152,6 +152,20 @@ static void nouveau_fifo_irq_handler(drm NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_CACHE_ERROR); } + if (status & NV_PFIFO_INTR_DMA_PUSHER) { + DRM_INFO("NV: PFIFO DMA pusher interrupt\n"); + + status &= ~NV_PFIFO_INTR_DMA_PUSHER; + NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_DMA_PUSHER); + + NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000); + if (NV_READ(NV_PFIFO_CACH1_DMAP)!=NV_READ(NV_PFIFO_CACH1_DMAG)) + { + uint32_t getval=NV_READ(NV_PFIFO_CACH1_DMAG)+4; + NV_WRITE(NV_PFIFO_CACH1_DMAG,getval); + } + } + if (status) { DRM_INFO("NV: unknown PFIFO interrupt. status=0x%08x\n", status); @@ -213,17 +227,17 @@ static void nouveau_nv10_context_switch( channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); /* 2-channel commute */ - if (channel==0) - channel=1; - else - channel=0; - dev_priv->cur_fifo=channel; - - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000100); - NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER)&0xE0FFFFFF)|(dev_priv->cur_fifo<<24)); - NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); +// if (channel==0) +// channel=1; +// else +// channel=0; +// dev_priv->cur_fifo=channel; + +// NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000100); + NV_WRITE(NV_PGRAPH_CTX_USER, NV_READ(NV_PGRAPH_CTX_USER)|0x1F000000); +// NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); /* touch PGRAPH_CTX_SWITCH* here ? */ - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000100); } static void nouveau_pgraph_irq_handler(drm_device_t *dev) diff-tree 3a0cd7c7e221f625585675490f626de8677a9dc7 (from b509abe413f74bd08f6415dec8147bd07e78a84b) Author: Stephane Marchesin <mar...@ic...> Date: Sat Oct 14 01:21:31 2006 +0200 Add the missing breaks. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 9615e08..6de6a61 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -238,10 +238,12 @@ static int nouveau_fifo_alloc(drm_device case NV_20: case NV_30: ctx_size=64; + break; case NV_40: case G_70: default: ctx_size=128; + break; } ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size; |
From: <dar...@ke...> - 2006-10-16 20:30:13
|
shared-core/nouveau_fifo.c | 149 ++++++++++++++++++++++++++++--------------- shared-core/nouveau_irq.c | 6 - shared-core/nouveau_object.c | 2 shared-core/nouveau_reg.h | 2 4 files changed, 104 insertions(+), 55 deletions(-) New commits: diff-tree 98e718d48fcd166accf1af3c017c34e331ab09cb (from 1943f39d8ce27c799f928bab172e521f4d540166) Author: Ben Skeggs <dar...@ii...> Date: Tue Oct 17 07:29:31 2006 +1100 NV40: FIFO context switching now WorksForMe(tm) diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 96c3c5e..d015d42 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -92,9 +92,12 @@ static void nouveau_fifo_init(drm_device ((dev_priv->objs.ht_bits - 9) << 16) | (dev_priv->objs.ht_base >> 8) ); - dev_priv->ramfc_offset=0x11000; + dev_priv->ramfc_offset=0x12000; dev_priv->ramro_offset=0x11200; - NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); /* RAMIN+0x11000 0.5k */ + if (dev_priv->card_type < NV_40) + NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); /* RAMIN+0x11000 0.5k */ + else + NV_WRITE(0x2220, 0x30002); NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); /* RAMIN+0x11200 0.5k */ NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); @@ -314,6 +317,10 @@ static int nouveau_fifo_alloc(drm_device /* enable the fifo dma operation */ NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel)); + NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base); + NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base); + +if (init->channel == 0) { // FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF); if (dev_priv->card_type >= NV_40) @@ -323,8 +330,6 @@ static int nouveau_fifo_alloc(drm_device NV_WRITE(NV_PFIFO_CACH1_DMAP, init->put_base); NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base); - NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base); - NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base); NV_WRITE(NV_PFIFO_CACH1_DMAI, dev_priv->cmdbuf_obj->instance >> 4); NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); @@ -338,6 +343,7 @@ static int nouveau_fifo_alloc(drm_device #else NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); #endif +} NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); @@ -375,6 +381,8 @@ static int nouveau_fifo_alloc(drm_device void nouveau_fifo_free(drm_device_t* dev,int n) { drm_nouveau_private_t *dev_priv = dev->dev_private; + int i; + dev_priv->fifos[n].used=0; DRM_INFO("%s: freeing fifo %d\n", __func__, n); @@ -382,7 +390,14 @@ void nouveau_fifo_free(drm_device_t* dev NV_WRITE(NV_PFIFO_CACHES, 0x00000000); NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)&~(1<<n)); - // FIXME XXX needs more code + // FIXME XXX needs more code + + /* Clean RAMFC */ + for (i=0;i<128;i+=4) { + DRM_DEBUG("RAMFC +%02x: 0x%08x\n", i, NV_READ(NV_RAMIN + + dev_priv->ramfc_offset + n*128 + i)); + NV_WRITE(NV_RAMIN + dev_priv->ramfc_offset + n*128 + i, 0); + } /* reenable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000001); diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index da68868..cff6bbb 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -133,7 +133,7 @@ void nouveau_irq_uninstall(drm_device_t static void nouveau_fifo_irq_handler(drm_device_t *dev) { - uint32_t status, chmode, chstat; + uint32_t status, chmode, chstat, channel; drm_nouveau_private_t *dev_priv = dev->dev_private; status = NV_READ(NV_PFIFO_INTSTAT); @@ -141,9 +141,9 @@ static void nouveau_fifo_irq_handler(drm return; chmode = NV_READ(NV_PFIFO_MODE); chstat = NV_READ(NV_PFIFO_DMA); + channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); - DRM_DEBUG("NV: PFIFO interrupt! INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", - status, chmode, chstat); + DRM_DEBUG("NV: PFIFO interrupt! Channel=%d, INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", channel, status, chmode, chstat); if (status & NV_PFIFO_INTR_CACHE_ERROR) { DRM_ERROR("NV: PFIFO error interrupt\n"); diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 4e0571b..5f11cfa 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -297,7 +297,7 @@ void nouveau_hash_table_init(drm_device_ dev_priv->objs.ht_base = 0x10000; dev_priv->objs.ht_size = (1 << dev_priv->objs.ht_bits); - dev_priv->objs.first_instance = 0x12000; + dev_priv->objs.first_instance = 0x13000; dev_priv->objs.free_instance = 1024; /*FIXME*/ dev_priv->objs.num_instance = 1024; /*FIXME*/ dev_priv->objs.inst_bmap = drm_calloc diff-tree 1943f39d8ce27c799f928bab172e521f4d540166 (from 95486bbde05ae51975c4d51fd194111788edee9a) Author: Ben Skeggs <dar...@ii...> Date: Tue Oct 17 06:37:40 2006 +1100 Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup code a bit. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 5b8cabd..96c3c5e 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -181,13 +181,88 @@ static int nouveau_dma_init(struct drm_d return 0; } +static void nouveau_context_init(drm_device_t *dev, + drm_nouveau_fifo_alloc_t *init) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t ctx_addr,ctx_size; + int i; + + switch(dev_priv->card_type) + { + case NV_03: + case NV_04: + case NV_05: + ctx_size=32; + break; + case NV_10: + case NV_20: + case NV_30: + default: + ctx_size=64; + break; + } + + ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size; + // clear the fifo context + for(i=0;i<ctx_size/4;i++) + NV_WRITE(ctx_addr+4*i,0x0); + + NV_WRITE(ctx_addr,init->put_base); + NV_WRITE(ctx_addr+4,init->put_base); + if (dev_priv->card_type <= NV_05) + { + // that's what is done in nvosdk, but that part of the code is buggy so... + NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4); +#ifdef __BIG_ENDIAN + NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); +#else + NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); +#endif + } + else + { + NV_WRITE(ctx_addr+12,dev_priv->cmdbuf_obj->instance >> 4/*DMA INST/DMA COUNT*/); +#ifdef __BIG_ENDIAN + NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); +#else + NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); +#endif + } + +} + +static void nouveau_nv40_context_init(drm_device_t *dev, + drm_nouveau_fifo_alloc_t *init) +{ +#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val)) + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t fifoctx; + int i; + + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*128; + for (i=0;i<128;i+=4) + NV_WRITE(fifoctx + i, 0); + + /* Fill entries that are seen filled in dumps of nvidia driver just + * after channel's is put into DMA mode + */ + RAMFC_WR(DMA_PUT , init->put_base); + RAMFC_WR(DMA_GET , init->put_base); + RAMFC_WR(DMA_INSTANCE , dev_priv->cmdbuf_obj->instance >> 4); + RAMFC_WR(DMA_FETCH , 0x30086078); + RAMFC_WR(DMA_SUBROUTINE, init->put_base); + RAMFC_WR(GRCTX_INSTANCE, 0); /* XXX */ + RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); +#undef RAMFC_WR +} + /* allocates and initializes a fifo for user space consumption */ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, DRMFILE filp) { int i; int ret; drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t ctx_addr,ctx_size; /* Init cmdbuf on first FIFO init, this is delayed until now to * give the ddx a chance to configure the cmdbuf with SETPARAM @@ -231,51 +306,10 @@ static int nouveau_fifo_alloc(drm_device NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); - switch(dev_priv->card_type) - { - case NV_03: - case NV_04: - case NV_05: - ctx_size=32; - break; - case NV_10: - case NV_20: - case NV_30: - ctx_size=64; - break; - case NV_40: - case G_70: - default: - ctx_size=128; - break; - } - - ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size; - // clear the fifo context - for(i=0;i<ctx_size/4;i++) - NV_WRITE(ctx_addr+4*i,0x0); - - NV_WRITE(ctx_addr,init->put_base); - NV_WRITE(ctx_addr+4,init->put_base); - if (dev_priv->card_type <= NV_05) - { - // that's what is done in nvosdk, but that part of the code is buggy so... - NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4); -#ifdef __BIG_ENDIAN - NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); -#else - NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); -#endif - } + if (dev_priv->card_type < NV_40) + nouveau_context_init(dev, init); else - { - NV_WRITE(ctx_addr+12,dev_priv->cmdbuf_obj->instance >> 4/*DMA INST/DMA COUNT*/); -#ifdef __BIG_ENDIAN - NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); -#else - NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); -#endif - } + nouveau_nv40_context_init(dev, init); /* enable the fifo dma operation */ NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel)); diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index c74feeb..7a0f429 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -193,7 +193,7 @@ #define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C #define NV40_RAMFC_SEMAPHORE 0x30 #define NV40_RAMFC_DMA_SUBROUTINE 0x34 -#define NV40_RAMFC_GRCTX_INSTANCE_32E0 /* guess */ 0x38 +#define NV40_RAMFC_GRCTX_INSTANCE /* guess */ 0x38 #define NV40_RAMFC_DMA_TIMESLICE 0x3C #define NV40_RAMFC_UNK_40 0x40 #define NV40_RAMFC_UNK_44 0x44 |
From: <dar...@ke...> - 2006-10-17 12:44:20
|
shared-core/nouveau_irq.c | 19 ++++++++++++++++++- shared-core/nouveau_object.c | 1 - shared-core/nouveau_reg.h | 5 +++++ 3 files changed, 23 insertions(+), 2 deletions(-) New commits: diff-tree 55de3f763f0de66b99f1afde9872f0072a84a9e3 (from 07059f427819755e13b051e1422c6e8671c70f92) Author: Ben Skeggs <dar...@ii...> Date: Tue Oct 17 23:44:05 2006 +1100 Useful output on a FIFO error interrupt. diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 086c064..af6109e 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -146,8 +146,25 @@ static void nouveau_fifo_irq_handler(drm DRM_DEBUG("NV: PFIFO interrupt! Channel=%d, INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", channel, status, chmode, chstat); if (status & NV_PFIFO_INTR_CACHE_ERROR) { + uint32_t c1get, c1method, c1data; + DRM_ERROR("NV: PFIFO error interrupt\n"); + c1get = NV_READ(NV_PFIFO_CACH1_GET) >> 2; + if (dev_priv->card_type < NV_40) { + /* Untested, so it may not work.. */ + c1method = NV_READ(NV_PFIFO_CACH1_METHOD(c1get)); + c1data = NV_READ(NV_PFIFO_CACH1_DATA(c1get)); + } else { + c1method = NV_READ(NV40_PFIFO_CACH1_METHOD(c1get)); + c1data = NV_READ(NV40_PFIFO_CACH1_DATA(c1get)); + } + + DRM_ERROR("NV: Channel %d/%d - Method 0x%04x, Data 0x%08x\n", + channel, (c1method >> 13) & 3, + c1method & 0x1ffc, c1data + ); + status &= ~NV_PFIFO_INTR_CACHE_ERROR; NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_CACHE_ERROR); } diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 18c5076..78a4b78 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -290,7 +290,6 @@ static void nouveau_object_instance_free void nouveau_hash_table_init(drm_device_t* dev) { drm_nouveau_private_t *dev_priv=dev->dev_private; - int ht_start, ht_end; int i; dev_priv->objs.ht_bits = 9; diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 7a0f429..b393e87 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -165,7 +165,12 @@ #define NV_PFIFO_CACH1_PUL0 0x00003250 #define NV_PFIFO_CACH1_PUL1 0x00003254 #define NV_PFIFO_CACH1_HASH 0x00003258 +#define NV_PFIFO_CACH1_GET 0x00003270 #define NV_PFIFO_CACH1_ENG 0x00003280 +#define NV_PFIFO_CACH1_METHOD(i) (0x00003800+(i*8)) +#define NV_PFIFO_CACH1_DATA(i) (0x00003804+(i*8)) +#define NV40_PFIFO_CACH1_METHOD(i) (0x00090000+(i*8)) +#define NV40_PFIFO_CACH1_DATA(i) (0x00090004+(i*8)) #define NV_CRTC0_INTSTAT 0x00600100 #define NV_CRTC0_INTEN 0x00600140 diff-tree 07059f427819755e13b051e1422c6e8671c70f92 (from 4b43ee63f90c93701c9f1cdf7fefd1816b316d33) Author: Ben Skeggs <dar...@ii...> Date: Tue Oct 17 23:08:03 2006 +1100 typo diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index cff6bbb..086c064 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -275,7 +275,7 @@ static void nouveau_pgraph_irq_handler(d instance = NV_READ(0x00400158); notify = NV_READ(0x00400150) >> 16; - DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", nsource, nstatus); + DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", instance, notify); status &= ~NV_PGRAPH_INTR_BUFFER_NOTIFY; NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_BUFFER_NOTIFY); |
From: <ai...@ke...> - 2006-11-05 08:50:00
|
linux-core/nouveau_drv.c | 1 - shared-core/nouveau_drv.h | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) New commits: diff-tree 665c8385c7865dcc4f92b9c212d6e2b35d7fa9f0 (from 1e118aeb39076a103c6581640b04a9b7e2a8209a) Author: Dave Airlie <airlied@ppcg5.localdomain> Date: Sun Nov 5 19:46:53 2006 +1100 add powerpc mmio swapper to NV_READ/WRITE macros diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 94b46ef..4b35e6d 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -171,8 +171,13 @@ extern void nouveau_irq_preinstal extern void nouveau_irq_postinstall(drm_device_t*); extern void nouveau_irq_uninstall(drm_device_t*); +#if defined(__powerpc__) +#define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) ) +#define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) ) +#else #define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#endif #endif /* __NOUVEAU_DRV_H__ */ diff-tree 1e118aeb39076a103c6581640b04a9b7e2a8209a (from 06639801ce1d515f790739a70b051498c8615288) Author: Dave Airlie <airlied@ppcg5.localdomain> Date: Sun Nov 5 19:46:30 2006 +1100 remove config.h diff --git a/linux-core/nouveau_drv.c b/linux-core/nouveau_drv.c index 2093ffe..8ad1d84 100644 --- a/linux-core/nouveau_drv.c +++ b/linux-core/nouveau_drv.c @@ -22,7 +22,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <linux/config.h> #include "drmP.h" #include "drm.h" #include "nouveau_drv.h" |
From: <dar...@ke...> - 2006-11-13 17:52:44
|
shared-core/nouveau_drv.h | 2 ++ shared-core/nouveau_fifo.c | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) New commits: diff-tree 35bf8fb5cf8ab4d4e055cdef26531d86dbf822dc (from parents) Merge: 9ef4bbc66c1b055b4450ea9354945d784751cef7 1123ab089075af3141c794696ec394fa46b4353f Author: Ben Skeggs <dar...@ii...> Date: Tue Nov 14 04:52:08 2006 +1100 Merge branch 'nouveau-1' of git+ssh://git.freedesktop.org/git/mesa/drm into nouveau-1 diff-tree 9ef4bbc66c1b055b4450ea9354945d784751cef7 (from f7affda35bb0c47fbc973725e05847669e215d46) Author: Ben Skeggs <dar...@ii...> Date: Tue Nov 14 04:51:13 2006 +1100 Hack around yet another "X restart borkage without nouveau.ko reload" problem. On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper solution to having this problem again in the future.. diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index f579026..ac21f65 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -112,6 +112,7 @@ typedef struct drm_nouveau_private { drm_local_map_t *mmio; drm_local_map_t *fb; + //TODO: Remove me, I'm bogus :) int cur_fifo; struct nouveau_object *fb_obj; @@ -119,6 +120,7 @@ typedef struct drm_nouveau_private { int cmdbuf_ch_size; struct mem_block* cmdbuf_alloc; + int fifo_alloc_count; struct nouveau_fifo fifos[NV_MAX_FIFO_NUMBER]; struct nouveau_object_store objs; /* RAMFC and RAMRO offsets */ diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index cf38964..ef63f08 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -178,7 +178,6 @@ static int nouveau_dma_init(struct drm_d dev_priv->cmdbuf_ch_size = (uint32_t)cb->size / nouveau_fifo_number(dev); dev_priv->cmdbuf_alloc = cb; - nouveau_fifo_init(dev); DRM_INFO("DMA command buffer is %dKiB at 0x%08x(%s)\n", (uint32_t)cb->size>>10, (uint32_t)cb->start, config->cmdbuf.location == NOUVEAU_MEM_FB ? "VRAM" : "AGP"); @@ -306,6 +305,9 @@ static int nouveau_fifo_alloc(drm_device if (ret) return ret; } + /* Initialise PFIFO regs */ + if (!dev_priv->fifo_alloc_count) + nouveau_fifo_init(dev); /* * Alright, here is the full story @@ -409,6 +411,7 @@ static int nouveau_fifo_alloc(drm_device /* FIFO has no objects yet */ dev_priv->fifos[init->channel].objs = NULL; + dev_priv->fifo_alloc_count++; DRM_INFO("%s: initialised FIFO %d\n", __func__, init->channel); return 0; @@ -438,6 +441,8 @@ void nouveau_fifo_free(drm_device_t* dev /* reenable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000001); + + dev_priv->fifo_alloc_count--; } /* cleanups all the fifos from filp */ |
From: <dar...@ke...> - 2006-11-13 22:00:55
|
shared-core/nouveau_drv.h | 15 +- shared-core/nouveau_fifo.c | 279 +++++++++++++++++++++++++++---------------- shared-core/nouveau_object.c | 42 +----- shared-core/nouveau_reg.h | 15 ++ shared-core/nouveau_state.c | 19 ++ 5 files changed, 234 insertions(+), 136 deletions(-) New commits: diff-tree 2fd812f8ef8adb09fd8d17cab869f9fc8b047d75 (from 7002082944a69e1d11b0146b1176fd4293581dcd) Author: Ben Skeggs <dar...@ii...> Date: Tue Nov 14 09:00:31 2006 +1100 Completely untested NV10/20/30 FIFO context switching changes. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index d4e5b1d..c662165 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -220,24 +220,9 @@ static void nouveau_context_init(drm_dev { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_object *cb_obj; - uint32_t ctx_addr,ctx_size; + uint32_t ctx_addr, ctx_size = 32; int i; - switch(dev_priv->card_type) - { - case NV_03: - case NV_04: - case NV_05: - ctx_size=32; - break; - case NV_10: - case NV_20: - case NV_30: - default: - ctx_size=64; - break; - } - cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj; ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size; @@ -247,27 +232,72 @@ static void nouveau_context_init(drm_dev NV_WRITE(ctx_addr,init->put_base); NV_WRITE(ctx_addr+4,init->put_base); - if (dev_priv->card_type <= NV_05) - { - // that's what is done in nvosdk, but that part of the code is buggy so... - NV_WRITE(ctx_addr+8, cb_obj->instance >> 4); + // that's what is done in nvosdk, but that part of the code is buggy so... + NV_WRITE(ctx_addr+8, cb_obj->instance >> 4); #ifdef __BIG_ENDIAN - NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); + NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); #else - NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); + NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); #endif - } - else - { - NV_WRITE(ctx_addr+12,cb_obj->instance >> 4/*DMA INST/DMA COUNT*/); +} + +#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val)) +static void nouveau_nv10_context_init(drm_device_t *dev, + drm_nouveau_fifo_alloc_t *init) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_object *cb_obj; + uint32_t fifoctx; + int i; + + cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj; + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*64; + for (i=0;i<64;i+=4) + NV_WRITE(fifoctx + i, 0); + + /* Fill entries that are seen filled in dumps of nvidia driver just + * after channel's is put into DMA mode + */ + RAMFC_WR(DMA_PUT , init->put_base); + RAMFC_WR(DMA_GET , init->put_base); + RAMFC_WR(DMA_INSTANCE , cb_obj->instance >> 4); #ifdef __BIG_ENDIAN - NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); + RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | + NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | + NV_PFIFO_CACH1_DMAF_MAX_REQS_4 | + NV_PFIFO_CACH1_BIG_ENDIAN); #else - NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); + RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | + NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | + NV_PFIFO_CACH1_DMAF_MAX_REQS_4); #endif - } + RAMFC_WR(DMA_SUBROUTINE, init->put_base); +} + +static void nouveau_nv10_context_save(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t fifoctx; + int channel; + + channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1); + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP)); + RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG)); + RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT)); + RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI)); + RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS)); + RAMFC_WR(DMA_FETCH , NV_READ(NV_PFIFO_CACH1_DMAF)); + RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG)); + RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1)); + RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE)); + RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP)); + RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT)); + RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE)); + RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMAG)); } +#undef RAMFC_WR #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val)) static void nouveau_nv40_context_init(drm_device_t *dev, @@ -391,16 +421,20 @@ static int nouveau_fifo_alloc(drm_device NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); - if (dev_priv->card_type < NV_40) + /* Save current channel's state to it's RAMFC entry. + * + * Then, construct inital RAMFC for new channel, I'm not entirely + * sure this is needed if we activate the channel immediately. + * My understanding is that the GPU will fill RAMFC itself when + * it switches away from the channel + */ + if (dev_priv->card_type < NV_10) { nouveau_context_init(dev, init); - else { - /* Save current channel's state to it's RAMFC entry */ + } else if (dev_priv->card_type < NV_40) { + nouveau_nv10_context_save(dev); + nouveau_nv10_context_init(dev, init); + } else { nouveau_nv40_context_save(dev); - /* Construct inital RAMFC for new channel, I'm not entirely - * sure this is needed if we activate the channel immediately. - * My understanding is that the GPU will fill RAMFC itself - * when it switches away from the channel - */ nouveau_nv40_context_init(dev, init); } diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 844ee86..fe42f98 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -193,6 +193,20 @@ #define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) /* RAMFC offsets */ +#define NV10_RAMFC_DMA_PUT 0x00 +#define NV10_RAMFC_DMA_GET 0x04 +#define NV10_RAMFC_REF_CNT 0x08 +#define NV10_RAMFC_DMA_INSTANCE 0x0C +#define NV10_RAMFC_DMA_STATE 0x10 +#define NV10_RAMFC_DMA_FETCH 0x14 +#define NV10_RAMFC_ENGINE 0x18 +#define NV10_RAMFC_PULL1_ENGINE 0x1C +#define NV10_RAMFC_ACQUIRE_VALUE 0x20 +#define NV10_RAMFC_ACQUIRE_TIMESTAMP 0x24 +#define NV10_RAMFC_ACQUIRE_TIMEOUT 0x28 +#define NV10_RAMFC_SEMAPHORE 0x2C +#define NV10_RAMFC_DMA_SUBROUTINE 0x30 + #define NV40_RAMFC_DMA_PUT 0x00 #define NV40_RAMFC_DMA_GET 0x04 #define NV40_RAMFC_REF_CNT 0x08 diff-tree 7002082944a69e1d11b0146b1176fd4293581dcd (from 35bf8fb5cf8ab4d4e055cdef26531d86dbf822dc) Author: Ben Skeggs <dar...@ii...> Date: Tue Nov 14 08:11:49 2006 +1100 Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO} diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index ac21f65..03c7bd1 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -71,16 +71,14 @@ struct nouveau_fifo drm_local_map_t *map; /* mapping of the regs controling the fifo */ drm_local_map_t *regs; + /* dma object for the command buffer itself */ + struct nouveau_object *cmdbuf_obj; /* objects belonging to this fifo */ struct nouveau_object *objs; }; struct nouveau_object_store { - int ht_bits; - int ht_size; - int ht_base; - uint32_t *inst_bmap; uint32_t first_instance; int num_instance; @@ -116,7 +114,6 @@ typedef struct drm_nouveau_private { int cur_fifo; struct nouveau_object *fb_obj; - struct nouveau_object *cmdbuf_obj; int cmdbuf_ch_size; struct mem_block* cmdbuf_alloc; @@ -124,8 +121,13 @@ typedef struct drm_nouveau_private { struct nouveau_fifo fifos[NV_MAX_FIFO_NUMBER]; struct nouveau_object_store objs; /* RAMFC and RAMRO offsets */ + uint32_t ramht_offset; + uint32_t ramht_size; + uint32_t ramht_bits; uint32_t ramfc_offset; + uint32_t ramfc_size; uint32_t ramro_offset; + uint32_t ramro_size; struct mem_block *agp_heap; struct mem_block *fb_heap; @@ -155,12 +157,13 @@ extern int nouveau_mem_ini extern void nouveau_mem_close(struct drm_device *dev); /* nouveau_fifo.c */ +extern int nouveau_fifo_init(drm_device_t *dev); extern int nouveau_fifo_number(drm_device_t *dev); extern void nouveau_fifo_cleanup(drm_device_t *dev, DRMFILE filp); extern int nouveau_fifo_id_get(drm_device_t *dev, DRMFILE filp); /* nouveau_object.c */ -extern void nouveau_hash_table_init(drm_device_t *dev); +extern int nouveau_object_init(drm_device_t *dev); extern void nouveau_object_cleanup(drm_device_t *dev, DRMFILE filp); extern struct nouveau_object *nouveau_dma_object_create(drm_device_t *dev, uint32_t offset, uint32_t size, int access, uint32_t target); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index ef63f08..d4e5b1d 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -53,63 +53,111 @@ int nouveau_fifo_number(drm_device_t* de * voir nv_driver.c : NVPreInit */ -static void nouveau_fifo_init(drm_device_t* dev) +static int nouveau_fifo_instmem_configure(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; - - /* Init PFIFO - This is an exact copy of what's done in the Xorg ddx so far. - * We should be able to figure out what's happening from the - * resources available.. - */ + int i; - if (dev->irq_enabled) - nouveau_irq_postinstall(dev); + /* Clear RAMIN */ + for (i=0x00710000; i<0x00800000; i++) + NV_WRITE(i, 0x00000000); + + /* FIFO hash table (RAMHT) + * use 4k hash table at RAMIN+0x10000 + * TODO: extend the hash table + */ + dev_priv->ramht_offset = 0x10000; + dev_priv->ramht_bits = 9; + dev_priv->ramht_size = (1 << dev_priv->ramht_bits); + NV_WRITE(NV_PFIFO_RAMHT, + (0x03 << 24) /* search 128 */ | + ((dev_priv->ramht_bits - 9) << 16) | + (dev_priv->ramht_offset >> 8) + ); + DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", + dev_priv->ramht_offset, + dev_priv->ramht_size); + + /* FIFO runout table (RAMRO) - 512k at 0x11200 */ + dev_priv->ramro_offset = 0x11200; + dev_priv->ramro_size = 512; + NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); + DRM_DEBUG("RAMRO offset=0x%x, size=%d\n", + dev_priv->ramro_offset, + dev_priv->ramro_size); + + /* FIFO context table (RAMFC) + * NV40 : Not sure exactly how to position RAMFC on some cards, + * 0x30002 seems to position it at RAMIN+0x20000 on these + * cards. RAMFC is 4kb (32 fifos, 128byte entries). + * Others: Position RAMFC at RAMIN+0x11400 + */ + if (dev_priv->card_type >= NV_40) { + dev_priv->ramfc_offset = 0x20000; + dev_priv->ramfc_size = nouveau_fifo_number(dev) * 128; + NV_WRITE(NV40_PFIFO_RAMFC, 0x30002); + } else if (dev_priv->card_type >= NV_10) { + dev_priv->ramfc_offset = 0x11400; + dev_priv->ramfc_size = nouveau_fifo_number(dev) * 64; + NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); + } else { + dev_priv->ramfc_offset = 0x11400; + dev_priv->ramfc_size = nouveau_fifo_number(dev) * 32; + NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); + } + DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", + dev_priv->ramfc_offset, + dev_priv->ramfc_size); - if (dev_priv->card_type >= NV_40) - NV_WRITE(NV_PGRAPH_NV40_UNK220, dev_priv->fb_obj->instance >> 4); + return 0; +} - DRM_DEBUG("%s: setting FIFO %d active\n", __func__, dev_priv->cur_fifo); +int nouveau_fifo_init(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int ret; - // FIXME remove all the stuff that's done in nouveau_fifo_alloc NV_WRITE(NV_PFIFO_CACHES, 0x00000000); + + ret = nouveau_fifo_instmem_configure(dev); + if (ret) { + DRM_ERROR("Failed to configure instance memory\n"); + return ret; + } + + /* FIXME remove all the stuff that's done in nouveau_fifo_alloc */ + + DRM_DEBUG("Setting defaults for remaining PFIFO regs\n"); + + /* All channels into PIO mode */ NV_WRITE(NV_PFIFO_MODE, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); - if (dev_priv->card_type >= NV_40) - NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|dev_priv->cur_fifo); - else - NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|dev_priv->cur_fifo); - NV_WRITE(NV_PFIFO_CACH1_DMAP, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size); - NV_WRITE(NV_PFIFO_CACH1_DMAG, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size); - NV_WRITE(NV_PFIFO_CACH1_DMAI, dev_priv->cmdbuf_obj->instance >> 4); + /* Channel 0 active, PIO mode */ + NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000000); + /* PUT and GET to 0 */ + NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000); + NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000); + /* No cmdbuf object */ + NV_WRITE(NV_PFIFO_CACH1_DMAI, 0x00000000); NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000); NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000); - NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); + NV_WRITE(NV_PFIFO_SIZE, 0x0000FFFF); NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); - NV_WRITE(NV_PFIFO_RAMHT, - (0x03 << 24) /* search 128 */ | - ((dev_priv->objs.ht_bits - 9) << 16) | - (dev_priv->objs.ht_base >> 8) - ); - /* RAMFC needs to be at RAMIN+0x20000 on NV40, I currently don't know - * how to move it.. - */ - dev_priv->ramfc_offset=0x20000; - if (dev_priv->card_type < NV_40) - NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); /* RAMIN+0x11000 0.5k */ - else - NV_WRITE(0x2220, 0x30002); - dev_priv->ramro_offset=0x11200; - NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); /* RAMIN+0x11200 0.5k */ NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000); #ifdef __BIG_ENDIAN - NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); + NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | + NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | + NV_PFIFO_CACH1_DMAF_MAX_REQS_4 | + NV_PFIFO_CACH1_BIG_ENDIAN); #else - NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); + NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | + NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | + NV_PFIFO_CACH1_DMAF_MAX_REQS_4); #endif NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001); @@ -126,11 +174,7 @@ static void nouveau_fifo_init(drm_device NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff); NV_WRITE(NV_PFIFO_CACHES, 0x00000001); - DRM_DEBUG("%s: CACHE1 GET/PUT readback %d/%d\n", __func__, - NV_READ(NV_PFIFO_CACH1_DMAG), - NV_READ(NV_PFIFO_CACH1_DMAP)); - - DRM_INFO("%s: OK\n", __func__); + return 0; } static int nouveau_dma_init(struct drm_device *dev) @@ -140,14 +184,6 @@ static int nouveau_dma_init(struct drm_d struct mem_block *cb; int cb_min_size = nouveau_fifo_number(dev) * max(NV03_FIFO_SIZE,PAGE_SIZE); - /* XXX this should be done earlier on init */ - nouveau_hash_table_init(dev); - - if (dev_priv->card_type >= NV_40) - dev_priv->fb_obj = nouveau_dma_object_create(dev, - 0, nouveau_mem_fb_amount(dev), - NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM); - /* Defaults for unconfigured values */ if (!config->cmdbuf.location) config->cmdbuf.location = NOUVEAU_MEM_FB; @@ -168,13 +204,6 @@ static int nouveau_dma_init(struct drm_d return DRM_ERR(ENOMEM); } - if (config->cmdbuf.location == NOUVEAU_MEM_AGP) - dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, - cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP); - else - dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, - cb->start - drm_get_resource_start(dev, 1), - cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM); dev_priv->cmdbuf_ch_size = (uint32_t)cb->size / nouveau_fifo_number(dev); dev_priv->cmdbuf_alloc = cb; @@ -190,6 +219,7 @@ static void nouveau_context_init(drm_dev drm_nouveau_fifo_alloc_t *init) { drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_object *cb_obj; uint32_t ctx_addr,ctx_size; int i; @@ -208,6 +238,8 @@ static void nouveau_context_init(drm_dev break; } + cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj; + ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size; // clear the fifo context for(i=0;i<ctx_size/4;i++) @@ -218,7 +250,7 @@ static void nouveau_context_init(drm_dev if (dev_priv->card_type <= NV_05) { // that's what is done in nvosdk, but that part of the code is buggy so... - NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4); + NV_WRITE(ctx_addr+8, cb_obj->instance >> 4); #ifdef __BIG_ENDIAN NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); #else @@ -227,7 +259,7 @@ static void nouveau_context_init(drm_dev } else { - NV_WRITE(ctx_addr+12,dev_priv->cmdbuf_obj->instance >> 4/*DMA INST/DMA COUNT*/); + NV_WRITE(ctx_addr+12,cb_obj->instance >> 4/*DMA INST/DMA COUNT*/); #ifdef __BIG_ENDIAN NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); #else @@ -242,9 +274,11 @@ static void nouveau_nv40_context_init(dr drm_nouveau_fifo_alloc_t *init) { drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_object *cb_obj; uint32_t fifoctx; int i; + cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj; fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*128; for (i=0;i<128;i+=4) NV_WRITE(fifoctx + i, 0); @@ -254,7 +288,7 @@ static void nouveau_nv40_context_init(dr */ RAMFC_WR(DMA_PUT , init->put_base); RAMFC_WR(DMA_GET , init->put_base); - RAMFC_WR(DMA_INSTANCE , dev_priv->cmdbuf_obj->instance >> 4); + RAMFC_WR(DMA_INSTANCE , cb_obj->instance >> 4); RAMFC_WR(DMA_FETCH , 0x30086078); RAMFC_WR(DMA_SUBROUTINE, init->put_base); RAMFC_WR(GRCTX_INSTANCE, 0); /* XXX */ @@ -296,6 +330,7 @@ static int nouveau_fifo_alloc(drm_device int i; int ret; drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_object *cb_obj; /* Init cmdbuf on first FIFO init, this is delayed until now to * give the ddx a chance to configure the cmdbuf with SETPARAM @@ -305,9 +340,6 @@ static int nouveau_fifo_alloc(drm_device if (ret) return ret; } - /* Initialise PFIFO regs */ - if (!dev_priv->fifo_alloc_count) - nouveau_fifo_init(dev); /* * Alright, here is the full story @@ -326,6 +358,23 @@ static int nouveau_fifo_alloc(drm_device if (i==nouveau_fifo_number(dev)) return DRM_ERR(EINVAL); + /* allocate a dma object for the command buffer */ + if (dev_priv->cmdbuf_alloc->flags & NOUVEAU_MEM_AGP) { + cb_obj = nouveau_dma_object_create(dev, + dev_priv->cmdbuf_alloc->start, + dev_priv->cmdbuf_alloc->size, + NV_DMA_ACCESS_RO, + NV_DMA_TARGET_AGP); + } else { + cb_obj = nouveau_dma_object_create(dev, + dev_priv->cmdbuf_alloc->start - + drm_get_resource_start(dev, 1), + dev_priv->cmdbuf_alloc->size, + NV_DMA_ACCESS_RO, + NV_DMA_TARGET_VIDMEM); + } + dev_priv->fifos[i].cmdbuf_obj = cb_obj; + /* that fifo is used */ dev_priv->fifos[i].used=1; dev_priv->fifos[i].filp=filp; @@ -370,7 +419,7 @@ static int nouveau_fifo_alloc(drm_device NV_WRITE(NV_PFIFO_CACH1_DMAP, init->put_base); NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base); - NV_WRITE(NV_PFIFO_CACH1_DMAI, dev_priv->cmdbuf_obj->instance >> 4); + NV_WRITE(NV_PFIFO_CACH1_DMAI, cb_obj->instance >> 4); NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 935297f..abd8bec 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -132,15 +132,14 @@ static uint32_t nouveau_handle_hash(drm_ int fifo) { drm_nouveau_private_t *dev_priv=dev->dev_private; - struct nouveau_object_store *objs=&dev_priv->objs; uint32_t hash = 0; int i; - for (i=32;i>0;i-=objs->ht_bits) { - hash ^= (handle & ((1 << objs->ht_bits) - 1)); - handle >>= objs->ht_bits; + for (i=32;i>0;i-=dev_priv->ramht_bits) { + hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1)); + handle >>= dev_priv->ramht_bits; } - hash ^= fifo << (objs->ht_bits - 4); + hash ^= fifo << (dev_priv->ramht_bits - 4); return hash << 3; } @@ -148,9 +147,8 @@ static int nouveau_hash_table_insert(drm struct nouveau_object *obj) { drm_nouveau_private_t *dev_priv=dev->dev_private; - struct nouveau_object_store *objs=&dev_priv->objs; - int ht_base = NV_RAMIN + objs->ht_base; - int ht_end = ht_base + objs->ht_size; + int ht_base = NV_RAMIN + dev_priv->ramht_offset; + int ht_end = ht_base + dev_priv->ramht_size; int o_ofs, ofs; o_ofs = ofs = nouveau_handle_hash(dev, obj->handle, fifo); @@ -277,38 +275,18 @@ static void nouveau_object_instance_free objs->free_instance++; } -/* Where is the hash table located: - - Base address and size can be calculated from this register: - - ht_base = 0x1000 * GetBitField (pNv->PFIFO[0x0210/4],8:4); - ht_size = 0x1000 << GetBitField (pNv->PFIFO[0x0210/4],17:16); - - and the hash table will be located between address PRAMIN + ht_base and - PRAMIN + ht_base + ht_size. Each hash table entry has two longwords. -*/ -void nouveau_hash_table_init(drm_device_t* dev) +int nouveau_object_init(drm_device_t* dev) { drm_nouveau_private_t *dev_priv=dev->dev_private; - int i; - - dev_priv->objs.ht_bits = 9; - dev_priv->objs.ht_base = 0x10000; - dev_priv->objs.ht_size = (1 << dev_priv->objs.ht_bits); - dev_priv->objs.first_instance = 0x13000; + dev_priv->objs.first_instance = + dev_priv->ramfc_offset +dev_priv->ramfc_size; dev_priv->objs.free_instance = 1024; /*FIXME*/ dev_priv->objs.num_instance = 1024; /*FIXME*/ dev_priv->objs.inst_bmap = drm_calloc (1, dev_priv->objs.num_instance/32, DRM_MEM_DRIVER); - /* clear all of RAMIN - * NOTE: except the bottom 0x10000 bytes, the binary driver doesn't - * like this and will die either sometime during init, or during - * shutdown - leaving the screen in an unusable state... - */ - for (i=0x00710000; i<0x00800000; i+=4) - NV_WRITE(i, 0x00000000); + return 0; } /* diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 868a067..844ee86 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -85,6 +85,7 @@ #define NV_PFIFO_RAMHT 0x00002210 #define NV_PFIFO_RAMFC 0x00002214 #define NV_PFIFO_RAMRO 0x00002218 +#define NV40_PFIFO_RAMFC 0x00002220 #define NV_PFIFO_CACHES 0x00002500 #define NV_PFIFO_MODE 0x00002504 #define NV_PFIFO_DMA 0x00002508 diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 1901f08..b05442f 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -64,6 +64,25 @@ int nouveau_firstopen(struct drm_device DRM_INFO("%lld MB of video ram detected\n",nouveau_mem_fb_amount(dev)>>20); + /* Clear RAMIN + * Determine locations for RAMHT/FC/RO + * Initialise PFIFO + */ + ret = nouveau_fifo_init(dev); + if (ret) return ret; + /* Initialise instance memory allocation */ + ret = nouveau_object_init(dev); + if (ret) return ret; + + /* FIXME: doesn't belong here, and have no idea what it's for.. */ + if (dev_priv->card_type >= NV_40) { + dev_priv->fb_obj = nouveau_dma_object_create(dev, + 0, nouveau_mem_fb_amount(dev), + NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM); + + NV_WRITE(NV_PGRAPH_NV40_UNK220, dev_priv->fb_obj->instance >> 4); + } + return 0; } |
From: <dar...@ke...> - 2006-11-17 23:10:08
|
shared-core/nouveau_fifo.c | 6 +++++- shared-core/nouveau_object.c | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) New commits: diff-tree 9ac7a8b0b4c0431b605c3f8d0b4a696903010c51 (from e9194dd1b068666dd94e73d95dc3cd031a89a6b7) Author: Ben Skeggs <dar...@ii...> Date: Sat Nov 18 10:09:29 2006 +1100 Only return FIFO number if the FIFO is marked as in use.. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 441bde4..b6fc613 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -564,7 +564,7 @@ int nouveau_fifo_id_get(drm_device_t* de int i; for(i=0;i<nouveau_fifo_number(dev);i++) - if (dev_priv->fifos[i].filp == filp) + if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp == filp) return i; return -1; } diff-tree e9194dd1b068666dd94e73d95dc3cd031a89a6b7 (from 18bba3fa29187bb5122ed057989203dc05bc46aa) Author: Ben Skeggs <dar...@ii...> Date: Sat Nov 18 10:03:45 2006 +1100 Check some return vals, fixes a couple of oopses. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 73c4e9f..441bde4 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -403,6 +403,10 @@ static int nouveau_fifo_alloc(drm_device NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM); } + if (!cb_obj) { + DRM_ERROR("unable to alloc object for command buffer\n"); + return DRM_ERR(EINVAL); + } dev_priv->fifos[i].cmdbuf_obj = cb_obj; /* that fifo is used */ diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index abd8bec..0db92ec 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -523,6 +523,8 @@ int nouveau_ioctl_object_init(DRM_IOCTL_ int fifo; fifo = nouveau_fifo_id_get(dev, filp); + if (fifo == -1) + return DRM_ERR(EINVAL); DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_object_init_t __user *) data, sizeof(init)); @@ -577,6 +579,8 @@ int nouveau_ioctl_dma_object_init(DRM_IO int fifo; fifo = nouveau_fifo_id_get(dev, filp); + if (fifo == -1) + return DRM_ERR(EINVAL); DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_dma_object_init_t __user *) data, sizeof(init)); |
From: <ai...@ke...> - 2006-12-19 23:31:18
|
linux-core/Makefile | 3 +-- linux-core/nouveau_drm.h | 1 + linux-core/nouveau_drv.h | 1 + linux-core/nouveau_fifo.c | 1 + linux-core/nouveau_irq.c | 1 + linux-core/nouveau_mem.c | 1 + linux-core/nouveau_object.c | 1 + linux-core/nouveau_reg.h | 1 + linux-core/nouveau_state.c | 1 + 9 files changed, 9 insertions(+), 2 deletions(-) New commits: diff-tree dc1b68aacbfc8d53d78f7388e0e52da1747a1f71 (from 744f9ac9c74f1571b54e08f9eaaaff22dd3230c8) Author: Dave Airlie <airlied@optimus.localdomain> Date: Wed Dec 20 10:29:43 2006 +1100 fixup symlinks via Makefile diff --git a/linux-core/Makefile b/linux-core/Makefile index 8792672..92ddfd3 100644 --- a/linux-core/Makefile +++ b/linux-core/Makefile @@ -107,11 +107,10 @@ NVHEADERS = nv_drv.h $(DRMHEADERS) NVSHARED = nv_drv.h FFBHEADERS = ffb_drv.h $(DRMHEADERS) NOUVEAUHEADERS = nouveau_drv.h nouveau_drm.h nouveau_reg.h $(DRMHEADERS) -NOUVEAUSHARED = nouveau_drv.h nouveau_drm.h nouveau_reg.h nouveau_state.c nouveau_fifo.c nouveau_mem.c nouveau_object.c nouveau_irq.c SHAREDSRC = $(DRMSHARED) $(MGASHARED) $(R128SHARED) $(RADEONSHARED) \ $(SISSHARED) $(TDFXSHARED) $(VIASHARED) $(MACH64SHARED) \ - $(I915SHARED) $(SAVAGESHARED) $(NVSHARED) $(NOUVEAUSHARED) + $(I915SHARED) $(SAVAGESHARED) $(NVSHARED) PROGS = dristat drmstat diff-tree 744f9ac9c74f1571b54e08f9eaaaff22dd3230c8 (from 1a40f3318c2660b83f64f7ed189d0f1692644ee4) Author: Dave Airlie <airlied@optimus.localdomain> Date: Wed Dec 20 10:28:55 2006 +1100 add nouveau symlinks via git diff --git a/linux-core/nouveau_drm.h b/linux-core/nouveau_drm.h new file mode 120000 index 0000000..d300ae0 --- /dev/null +++ b/linux-core/nouveau_drm.h @@ -0,0 +1 @@ +../shared-core/nouveau_drm.h \ No newline at end of file diff --git a/linux-core/nouveau_drv.h b/linux-core/nouveau_drv.h new file mode 120000 index 0000000..8852e26 --- /dev/null +++ b/linux-core/nouveau_drv.h @@ -0,0 +1 @@ +../shared-core/nouveau_drv.h \ No newline at end of file diff --git a/linux-core/nouveau_fifo.c b/linux-core/nouveau_fifo.c new file mode 120000 index 0000000..60759a5 --- /dev/null +++ b/linux-core/nouveau_fifo.c @@ -0,0 +1 @@ +../shared-core/nouveau_fifo.c \ No newline at end of file diff --git a/linux-core/nouveau_irq.c b/linux-core/nouveau_irq.c new file mode 120000 index 0000000..3137b81 --- /dev/null +++ b/linux-core/nouveau_irq.c @@ -0,0 +1 @@ +../shared-core/nouveau_irq.c \ No newline at end of file diff --git a/linux-core/nouveau_mem.c b/linux-core/nouveau_mem.c new file mode 120000 index 0000000..a008520 --- /dev/null +++ b/linux-core/nouveau_mem.c @@ -0,0 +1 @@ +../shared-core/nouveau_mem.c \ No newline at end of file diff --git a/linux-core/nouveau_object.c b/linux-core/nouveau_object.c new file mode 120000 index 0000000..1c1426e --- /dev/null +++ b/linux-core/nouveau_object.c @@ -0,0 +1 @@ +../shared-core/nouveau_object.c \ No newline at end of file diff --git a/linux-core/nouveau_reg.h b/linux-core/nouveau_reg.h new file mode 120000 index 0000000..2ad0739 --- /dev/null +++ b/linux-core/nouveau_reg.h @@ -0,0 +1 @@ +../shared-core/nouveau_reg.h \ No newline at end of file diff --git a/linux-core/nouveau_state.c b/linux-core/nouveau_state.c new file mode 120000 index 0000000..b304f6b --- /dev/null +++ b/linux-core/nouveau_state.c @@ -0,0 +1 @@ +../shared-core/nouveau_state.c \ No newline at end of file |