> Date: Wed, 19 Mar 2008 19:51:57 -0400
> From: alexdeucher@gmail.com
> To: awj_in_japan@hotmail.com
> Subject: Re: [Dri-users] Visual artifacts on radeon 9500 dri
> CC: lreid@cs.okstate.edu; dri-users@lists.sourceforge.net
>
> On Wed, Mar 19, 2008 at 7:29 PM, Alex Jackson <awj_in_japan@hotmail.com> wrote:
> > Wouldn't it be better, now that we have those register docs, to get the
> > number of working pipes from the card itself (specifically GB_PIPE_SELECT)
> > rather than using a list of PCI ids?
>
> Yes, I'm working on it :)
> However, r3xx chips don't have GB_PIPE_SELECT. Only r4xx, rs4xx and r5xx do.

Yeah, I just looked at the newly-dropped R300 doc and noticed that there's no sign of that register.  I guess that's why the 9500s were easy to "softmod" in Windows, and there's no choice for those cards but to use a list of PCI IDs...

According to the R500 doc, it looks like you can just set GB_PIPE_SELECT to the maximum (16 pipes) on all R4xx and R5xx cards and the card will automatically correct it to the actual number of working pipes.  Is this right or am I misinterpreting the doc?

I guess we'll want to query the card anyway for the real number of working pipes when/if we start tweaking the bits in GB_TILE_CONFIG for performance like the binary drivers (presumably) do.  For example it looks like there's a bit in that register that's specific to 12-pipe configurations, and selects one of two ways of splitting the pixels between the three quads, any idea how that works?  Is it something like

[1][2]
[3]

versus

   [1]
[2][3]

??

--AWJ--


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