[Doxygen-users] VHDL Hierachy

[Martyn P. <ma...@di...>]

Hello,

 

I recently had upgraded a doxygen install to the current release and instantly lost all the hierarchy information within the documentation. Trying different versions of doxygen the problem seems to have started after Release 1.8.7 when the parser was changed, all releases after that tag result in the same issue:

 

Some code:

 

library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;

library lib;

 

entity a_module is

            port ( a_in : in std_logic; a_out : out std_logic);

end a_module;

 

architecture behavioral of a_module is

            signal b_in                  : std_logic;

            signal b_out    : std_logic;

            signal c_in                   : std_logic;

            signal c_out     : std_logic;

begin

 

            b_i : entity work.b_module

            port map (b_in => b_in, b_out => b_out);

 

            c_i : entity lib.c_module

            port map (c_in => c_in, c_out => c_out);

 

end behavioral;

 

library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;

 

entity b_module is

            port ( b_in : in std_logic; b_out : out std_logic);

end b_module;

 

architecture behavioral of b_module is

            signal b_in : std_logic;

            signal b_out : std_logic;

begin

            b_out <= b_in;

end behavioral;

 

[c_module is the same code as b_module, just located in a different place]

 

Older version of doxygen identify a_module as using b_module and c_module, newer versions do not. The entities a_module and b_module are in the 'work' scope, c_module is partially compiled elsewhere. 

 

Is there any way to fix this or is there a way to force the class hierarchy. My only option at the moment is to require my user nothing new than 1.8.7 which is not ideal...

 

Many thanks,

 

 - Martyn