Re: [Doxygen-users] VHDL Process Comments Grouped Wrong

[spaceman_spiff <pad...@gm...>]

I kept digging and found a work around for this issue.

This appears to be related to conditionals. If, for instance, I have the
code below without a dummy signal work around, all comments for processes
(and functions) get shifted to the wrong processes (and functions). 

e.g. For the below example, comments to be associated with example_process1
are erroneously associated with example_process2. 

I've found a temporary workaround. If I define a dummy signal between the
conditional and the 1st process, the comments will be grouped correctly.

This may be due to some bug within Doxygen. It seems that Doxygen expects
signals to be documented, and if they are all excluded with a conditional,
you get some sort of associative problem with process or function comments.

--! @cond SIGNALS_TO_EXCLUDE
signal signal_A : std_logic;
signal signal_B : std_logic;
signal signal_n : std_logic;
--! @endcond

-- This signal is a bug workaround for Doxygen. If it is excluded, the
process comments get jacked up
signal dummy_signal : std_logic; 

begin

---------------------------------
--! @brief This is a process that flips a bit
--!
--! @param[in] CLK, 250MHz
---------------------------------
example_process1: process(CLK)
begin
    if rising_edge(CLK) then
         if RST = '1' then
              ibit <= '0';
         else
              ibit <= not ibit;
         end if;
    end if;
end process; 

---------------------------------
--! @brief This is a counter
--!
--! This counter counts to c_max_count
--! then retains its value.
--!
--! @param[in] CLK, 250MHz
---------------------------------
example_process2: process(CLK)
begin
    if rising_edge(CLK) then
         if RST = '1' then
              icount <= (others => '0');
         elsif icount /= c_mac_count then
              icount <= icount + '1';
         else
              icount <= icount;
         end if;
    end if;
end process; 



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