Re: [Doxygen-users] VHDL: how to include elements of a record (and the associated comment)?

[mkk <mk...@gm...>]

I posted Dimitri a patch for this issue
 
checkout and compile the current GIT repository 

documenting a record should now work.

 --! \brief description for a type, which actually is a record

   type my_record_1 is record
      element_11 : std_logic;     --! comment for first element of
my_record_1
      element_12 : std_logic;     --! comment for second element of
my_record_1
   end record;



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