[Doxygen-users] VHDL: 'to' keyword in case statement is regarded as 'syntax error' (bug?)

[Fontaine, F. <Fil...@nl...>]

Hi all,



I just stumbled on something that seems like a bug in Doxygen to me. In VHDL you can use the keyword 'to' within a case statement. For example:



------

case some_integer is

    when 0 => -- do something



    when 1 to 5  =>  -- do something else

    when others =>  -- do this in all other situations

end case;

------



Although this is 'legal' (and synthesizeable) VHDL, Doxygen reports this 'to' keyword as a 'syntax error'. The resulting corresponding output of Doxygen is not complete after this.



Is there a way around this errror?



Thanks in advance,



Filip



P.S. I'm using Doxygen version 1.8.9.1 on Windows 7 (64-bit, Service Pack 1).