[Doxygen-users] vhdl parser: too restrictive on 'if generate'; confused by a '; stderr out of sync

[Walter F.J. M. <w.f...@re...>]

Hi,

beyond the grave speed issues I found three other things worth commenting
in the new VHDL parser used in doxygen 1.8.9:

- it does not accept a 'begin' after an 'if generate' without declarations
   in between. In that case 'begin' is optional. Code like

     PC11: if true generate
     begin
       I0 : ibdr_pc11
         port map (
           ....
         );
     end generate PC11;

   creates a message like
     syntax error at line: nnn : begin

- the construct
     if L(L'left+1) = '"' then
   creates a
     syntax error at line: 493 : '
   Unfortunately it doesn't tell which ' is not understood. The context is

     procedure readgen(                    -- read slv generic base
       L: inout line;                      -- line
       ...
       if L'length >= 2 then
         if L(L'left+1) = '"' then
           case L(L'left) is

- these 'syntax error' lines are written to stderr. When stdout and stderr
   both go to terminal they appear behind "Reading <filename>..." line.
   When using

     doxygen-1.8.9 -d time test.Doxyfile 2>&1 | tee doxygen-1.8.9.log

   they a come completely out of sync and can't be associated with the
   source file.

Both syntax errors don't appear under doxygen 1.8.7.


		With best regards, 	Walter