[Doxygen-users] VHDL Blocks

[Joseph C. <jc...@en...>]

I'm trying to use a code block in a VHDL, but I can't seem to get it
working.  I think I'm following the documentation correctly by indenting 4
spaces relative to the previous paragraph).  I've attached my example
test.vhd, Doxyfile, and doxygen output.  Could someone tell me what I'm
doing wrong?  Or if this is a missing feature for VHDL in doxygen?

Thanks,
Joseph

P.S.  My attachment is a regular .zip, but I had to rename it to .zipped so
Gmail wouldn't block it.  Also, I've only included the html file output to
avoid going over the 60kB attachment limit.