Re: [Doxygen-develop] [PATCH] VHDL Component Instantiation Fixes

[mkk1 <mk...@gm...>]

Robert Abel wrote:
> 
> On 19.03.2012 20:27, Dimitri Van Heesch wrote:
>> Can you send me an example that I can use to test your patch?
> 
> Yes, please find an example here
> <https://sites.google.com/site/rawbdagslair/DoxygenTestProject.7z?attredirects=0&d=1>.
> My example includes the VHDL instantiation bug/graph creation bug and
> the XML tag file bug I posted more recently to the list.
> 
> You will have to run
> 
> old-doxygen DoxyfileB
> old-doxygen DoxyfileA
> 
> new-doxygen DoxyfileB
> new-doxygen DoxyfileA_Fix
> 
> srcA contains all a DFF (sub_component), a senseless inverted DFF
> (sub_sub_component) and a top level entity. Instantiating
> sub_sub_component in toplevel will hide sub_component in toplevel
> completely depending on the order the instantiations are processed by
> the parser. So you will see different results on each parse when you
> switch the locations of dffA, dffNotA and dffB.
> 
> On a side note, I just noticed that detail descriptions on
> instantiations don't work for some reason...
> 
> srcB is only for showcasing the XML tag file bug. It creates two groups
> with "special characters" (though they aren's /that/ special...). When
> you look inside docA, you will find them to be gibberish.
> 
>> I assume your maxlevel hack is used to see is a class is a direct
>> base class or sub class, right?
> Yes. It could be altered to be a boolean, either only direct
> "inheritance" or inheritance over all levels. That what would be needed
> for VHDL at least. However, I thought it might come in handy to have
> control over the depth of the recursion so the abort() can be avoided by
> other language parsers etc.
> 
> Regards,
> 
> Robert
> 
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