Hi,
I just started using Doxygen for VHDL, and I think I have found a bug. We
use arrays of unconstrained elements - a VHDL-2008 feature - a lot in our
design, but this triggers a bug in the VHDL scanner. Consider the
following code:
--------------------------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity top is
end entity top;
architecture str of top is
type slv_vector is array(natural range <>) of std_logic_vector;
signal clk : std_logic;
signal data, q : slv_vector(0 to 10)(15 downto 0);
begin
is_missing_from_diagram_inst : entity work.is_missing_from_diagram port
map(clk, data, q);
end architecture str;
--------------------------------------------------------------------------------------------------------------------------------------------
When compiling this with HAVE_DOT and OPTIMIZE_FOR_VHDL set to yes, the
class hierarchy diagram is missing. If I replace the slv_vector type with
another type such as integer, everything is fine.
I would guess that the definition for arrays of unconstrained elements is
missing from the vhdlparser.y file, but I am no Flex and Bison wizard, so I
thought I'd ask here first before diving into the code again.
--
Trond Danielsen <tro...@no...>
Project Engineer
Norbit Subsea AS <http://www.norbit.no>
+47 404 94 711
Email written on eco-friendly reusable memory
|
