Bug with a signal named "DEFAULT&...

[Bouqs]

Hello all,

I am a new french doxygen user.
I use it to generate html documentation of vhdl code.

An entity of my design contain a signal named DEFAULT (I can't change this name) .
The html page generated was wrong.
That's ok if I rename it.

I am using doxygene 1.8.3.1 on linux 2.6.18-308.13.1.el5.

OPTIMIZE_OUTPUT_VHDL   = YES

test case  :

--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
 port (
 din_0 : in std_logic; --! Mux first input
 DEFAULT : in std_logic; --! Mux Second input
 sel : in std_logic; --! Select input
 mux_out : out std_logic --! Mux output
 );
end entity;
--! @brief Architure definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
 with (sel) select
 mux_out <= din_0 when '0',
 DEFAULT when others;
end architecture;

result :

Thanks
Bouqs

[Bouqs]

sorry, I forgot the picture :