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From: <mta...@us...> - 2008-09-24 17:53:33
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Revision: 999
http://desmume.svn.sourceforge.net/desmume/?rev=999&view=rev
Author: mtabachenko
Date: 2008-09-24 17:53:14 +0000 (Wed, 24 Sep 2008)
Log Message:
-----------
typo fix
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-09-24 17:50:02 UTC (rev 998)
+++ trunk/desmume/src/MMU.cpp 2008-09-24 17:53:14 UTC (rev 999)
@@ -2727,7 +2727,7 @@
return;
case REG_IPCFIFOCNT :
{
-#ifdef 0
+#if 0
u32 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184) ;
u32 cnt_r = T1ReadWord(MMU.MMU_MEM[(proc+1) & 1][0x40], 0x184) ;
if ((val & 0x8000) && !(cnt_l & 0x8000))
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From: <ze...@us...> - 2008-09-25 03:40:15
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Revision: 1001
http://desmume.svn.sourceforge.net/desmume/?rev=1001&view=rev
Author: zeromus
Date: 2008-09-25 03:39:46 +0000 (Thu, 25 Sep 2008)
Log Message:
-----------
fix some unsafe bit logic / bool code
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-09-24 22:25:24 UTC (rev 1000)
+++ trunk/desmume/src/MMU.cpp 2008-09-25 03:39:46 UTC (rev 1001)
@@ -791,8 +791,8 @@
u16 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184);
u32 val = FIFOget(MMU.fifos + proc);
- cnt_l |= (MMU.fifos[proc].empty<<8) | (MMU.fifos[proc].full<<9) | (MMU.fifos[proc].error<<14);
- cnt_r |= (MMU.fifos[proc].empty) | (MMU.fifos[proc].full<<1);
+ cnt_l |= (MMU.fifos[proc].empty?0x0100:0) | (MMU.fifos[proc].full?0x0200:0) | (MMU.fifos[proc].error?0x4000:0);
+ cnt_r |= (MMU.fifos[proc].empty?0x0001:0) | (MMU.fifos[proc].full?0x0002:0);
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
@@ -2761,8 +2761,8 @@
//printlog("write32 (%s): REG_IPCFIFOSEND (%X-%X) val=%X\n", proc?"ARM9":"ARM7",cnt_l,cnt_r,val);
//FIFOadd(MMU.fifos+(proc^1), val);
FIFOadd(MMU.fifos+(proc^1), val);
- cnt_l = (cnt_l & 0xFFFC) | (MMU.fifos[proc^1].full<<1);
- cnt_r = (cnt_r & 0xFCFF) | (MMU.fifos[proc^1].full<<9);
+ cnt_l = (cnt_l & 0xFFFC) | (MMU.fifos[proc^1].full?0x0002:0);
+ cnt_r = (cnt_r & 0xFCFF) | (MMU.fifos[proc^1].full?0x0200:0);
T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, cnt_l);
T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, cnt_r);
MMU.reg_IF[proc^1] |= ((cnt_r & (1<<10))<<8);
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From: <mta...@us...> - 2008-11-15 18:09:43
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Revision: 1125
http://desmume.svn.sourceforge.net/desmume/?rev=1125&view=rev
Author: mtabachenko
Date: 2008-11-15 18:09:41 +0000 (Sat, 15 Nov 2008)
Log Message:
-----------
core:
- temporary implementations for clearing VRAM (garbage on screen);
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-11-15 17:51:17 UTC (rev 1124)
+++ trunk/desmume/src/MMU.cpp 2008-11-15 18:09:41 UTC (rev 1125)
@@ -226,6 +226,8 @@
u32 MMU_ARM7_WAIT32[16]={
1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1,
};
+
+static u8 MMU_VRAMcntSaved[10];
void MMU_Init(void) {
int i;
@@ -256,6 +258,8 @@
MMU.MMU_WAIT32[0] = MMU_ARM9_WAIT32;
MMU.MMU_WAIT32[1] = MMU_ARM7_WAIT32;
+ memset(MMU_VRAMcntSaved, 0, sizeof(MMU_VRAMcntSaved[0])*10);
+
FIFOclear(&MMU.fifos[0]);
FIFOclear(&MMU.fifos[1]);
@@ -312,6 +316,8 @@
memset(MMU.ARM7_ERAM, 0, 0x010000);
memset(MMU.ARM7_REG, 0, 0x010000);
+ memset(MMU_VRAMcntSaved, 0, sizeof(MMU_VRAMcntSaved[0])*10);
+
FIFOclear(&MMU.fifos[0]);
FIFOclear(&MMU.fifos[1]);
@@ -355,6 +361,96 @@
rtcInit();
}
+// temporary implementations for clearing VRAM (garbage on screen)
+// TODO: rewrite VRAM control
+static u8 MMU_checkVRAM(u8 block, u8 val)
+{
+ u32 size = 0;
+ u8 *destination = NULL;
+
+ if ((val & 0x80))
+ {
+ MMU_VRAMcntSaved[block] = val;
+ return 1;
+ }
+
+ if (MMU_VRAMcntSaved[block] == 0) return 2;
+
+ switch (MMU_VRAMcntSaved[block] & 0x07)
+ {
+ case 0:
+ break;
+ case 1:
+ switch (block)
+ {
+ case 0: // A
+ case 1: // B
+ case 2: // C
+ case 3: // D
+ size = 0x20000 ;
+ destination = ARM9Mem.ARM9_ABG + ((MMU_VRAMcntSaved[block] >> 3) & 3) * 0x20000 ;
+ break;
+ case 4: // E
+ size = 0x10000;
+ destination = ARM9Mem.ARM9_ABG ;
+ break;
+ case 5: // F
+ case 6: // G
+ size = 0x4000;
+ destination = ARM9Mem.ARM9_ABG +
+ (((MMU_VRAMcntSaved[block] >> 3) & 0x01) * 0x4000) +
+ (((MMU_VRAMcntSaved[block] >> 4) & 0x1) * 0x10000) ;
+ break;
+ case 8: // H
+ size = 0x8000;
+ destination = ARM9Mem.ARM9_BBG ;
+ break;
+ case 9: // I
+ size = 0x4000;
+ destination = ARM9Mem.ARM9_BBG + 0x8000;
+ break ;
+ }
+ break;
+ case 2:
+ switch(block)
+ {
+ case 0:
+ case 1:
+ // banks A,B are in use for OBJ at AOBJ + ofs * 0x20000
+ size = 0x20000;
+ destination = ARM9Mem.ARM9_AOBJ+(((MMU_VRAMcntSaved[block]>>3)&1)*0x20000);
+ break;
+ case 4: // E
+ size = 0x10000;
+ destination = ARM9Mem.ARM9_AOBJ;
+ break;
+ case 5:
+ case 6:
+ size = 0x4000;
+ destination = ARM9Mem.ARM9_AOBJ+
+ (((MMU_VRAMcntSaved[block]>>3)&1)*0x4000)+
+ (((MMU_VRAMcntSaved[block]>>4)&1)*0x10000);
+ break;
+ }
+ break;
+ case 4:
+ switch(block)
+ {
+ case 2: // C
+ size = 0x20000;
+ destination = ARM9Mem.ARM9_BBG ;
+ break ;
+ case 3: // D
+ size = 0x20000;
+ break ;
+ }
+ break;
+ }
+ if (!destination) return 3;
+ memset(destination, 0, size) ;
+ return 0;
+}
+
/* the VRAM blocks keep their content even when not blended in */
/* to ensure that we write the content back to the LCD ram */
/* FIXME: VRAM Bank E,F,G,H,I missing */
@@ -485,10 +581,6 @@
if (!destination) return ;
if (!source) return ;
memcpy(destination,source,size) ;
-
- //zero 10/10/08 - if vram is not mapped, then when it is read from, it should be zero
- //mimic this by clearing it now.
- memset(source,0,size) ;
}
static void MMU_VRAMReloadFromLCD(u8 block,u8 VRAMBankCnt)
@@ -1091,6 +1183,8 @@
case REG_VRAMCNTD:
if(proc == ARMCPU_ARM9)
{
+ if (MMU_checkVRAM(adr-REG_VRAMCNTA, val) == 1) break;
+
MMU_VRAMWriteBackToLCD(adr-REG_VRAMCNTA) ;
switch(val & 0x1F)
{
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From: <mta...@us...> - 2008-11-18 09:24:29
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Revision: 1136
http://desmume.svn.sourceforge.net/desmume/?rev=1136&view=rev
Author: mtabachenko
Date: 2008-11-18 09:24:23 +0000 (Tue, 18 Nov 2008)
Log Message:
-----------
core:
- fix textures (ex. Castlevania DOS)
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-11-17 21:04:12 UTC (rev 1135)
+++ trunk/desmume/src/MMU.cpp 2008-11-18 09:24:23 UTC (rev 1136)
@@ -1183,6 +1183,24 @@
case REG_VRAMCNTD:
if(proc == ARMCPU_ARM9)
{
+ //
+ // FIXME: simply texture slot handling
+ // This is a first stab and is not correct. It does
+ // not handle a VRAM texture slot becoming
+ // unconfigured.
+ // Revisit all of VRAM control handling for future
+ // release?
+ //
+ if ( val & 0x80) {
+ if ( (val & 0x7) == 3) {
+ int slot_index = (val >> 3) & 0x3;
+
+ ARM9Mem.textureSlotAddr[slot_index] =
+ &ARM9Mem.ARM9_LCD[0x20000 * (adr - REG_VRAMCNTA)];
+
+ gpu3D->NDS_3D_VramReconfigureSignal();
+ }
+ }
if (MMU_checkVRAM(adr-REG_VRAMCNTA, val) == 1) break;
MMU_VRAMWriteBackToLCD(adr-REG_VRAMCNTA) ;
@@ -1212,24 +1230,6 @@
MMU.vram_mode[adr-REG_VRAMCNTA] = 4 | (adr-REG_VRAMCNTA) ;
break ;
}
- //
- // FIXME: simply texture slot handling
- // This is a first stab and is not correct. It does
- // not handle a VRAM texture slot becoming
- // unconfigured.
- // Revisit all of VRAM control handling for future
- // release?
- //
- if ( val & 0x80) {
- if ( (val & 0x7) == 3) {
- int slot_index = (val >> 3) & 0x3;
-
- ARM9Mem.textureSlotAddr[slot_index] =
- &ARM9Mem.ARM9_LCD[0x20000 * (adr - REG_VRAMCNTA)];
-
- gpu3D->NDS_3D_VramReconfigureSignal();
- }
- }
MMU_VRAMReloadFromLCD(adr-REG_VRAMCNTA,val) ;
}
break;
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From: <ric...@us...> - 2008-11-28 22:06:13
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Revision: 1149
http://desmume.svn.sourceforge.net/desmume/?rev=1149&view=rev
Author: riccardom
Date: 2008-11-28 22:06:08 +0000 (Fri, 28 Nov 2008)
Log Message:
-----------
Fix whitespace
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-11-26 14:09:41 UTC (rev 1148)
+++ trunk/desmume/src/MMU.cpp 2008-11-28 22:06:08 UTC (rev 1149)
@@ -40,13 +40,13 @@
#include "mc.h"
static const int save_types[7][2] = {
- {MC_TYPE_AUTODETECT,1},
- {MC_TYPE_EEPROM1,MC_SIZE_4KBITS},
- {MC_TYPE_EEPROM2,MC_SIZE_64KBITS},
- {MC_TYPE_EEPROM2,MC_SIZE_512KBITS},
- {MC_TYPE_FRAM,MC_SIZE_256KBITS},
- {MC_TYPE_FLASH,MC_SIZE_2MBITS},
- {MC_TYPE_FLASH,MC_SIZE_4MBITS}
+ {MC_TYPE_AUTODETECT,1},
+ {MC_TYPE_EEPROM1,MC_SIZE_4KBITS},
+ {MC_TYPE_EEPROM2,MC_SIZE_64KBITS},
+ {MC_TYPE_EEPROM2,MC_SIZE_512KBITS},
+ {MC_TYPE_FRAM,MC_SIZE_256KBITS},
+ {MC_TYPE_FLASH,MC_SIZE_2MBITS},
+ {MC_TYPE_FLASH,MC_SIZE_4MBITS}
};
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From: <mta...@us...> - 2008-11-30 23:54:08
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Revision: 1161
http://desmume.svn.sourceforge.net/desmume/?rev=1161&view=rev
Author: mtabachenko
Date: 2008-11-30 23:54:05 +0000 (Sun, 30 Nov 2008)
Log Message:
-----------
core:
- small fix in VRAM mapping control;
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-11-30 17:09:55 UTC (rev 1160)
+++ trunk/desmume/src/MMU.cpp 2008-11-30 23:54:05 UTC (rev 1161)
@@ -394,7 +394,7 @@
for (int i =0; i < 9; i++)
{
- MMU.LCD_VRAM_ADDR[i] = 0xFFFFFFFF;
+ MMU.LCD_VRAM_ADDR[i] = 0;
for (int t = 0; t < 32; t++)
MMU.VRAM_MAP[i][t] = 7;
}
@@ -412,8 +412,6 @@
u8 engine_offset = (vram_addr >> 14);
u8 block = MMU.VRAM_MAP[engine][engine_offset];
if (block == 7) return NULL;
- if (!MMU.LCDCenable[block]) return NULL;
- if (MMU.LCD_VRAM_ADDR[block] == 0xFFFFFFFF) return NULL;
vram_addr -= MMU.LCD_VRAM_ADDR[block];
u8 *tmp_addr = LCDdst[block] + vram_addr;
return (tmp_addr);
@@ -433,9 +431,6 @@
u8 engine_offset = (vram_addr >> 14);
u8 block = MMU.VRAM_MAP[engine][engine_offset];
if (block == 7) return TRUE;
- if (!MMU.LCDCenable[block]) return TRUE;
- if (MMU.LCD_VRAM_ADDR[block] == 0xFFFFFFFF) return TRUE;
-
//INFO("VRAM %i: engine=%i (offset=%i), map address = 0x%X, MMU address = 0x%X\n", block, engine, engine_offset, vram_addr, *addr);
vram_addr -= MMU.LCD_VRAM_ADDR[block];
vram_addr += LCDdata[block][0];
@@ -446,9 +441,6 @@
static INLINE void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
{
- if (!(VRAMBankCnt & 0x80)) return;
- if (!(VRAMBankCnt & 0x07)) return;
-
u32 vram_map_addr = 0xFFFFFFFF;
BOOL isMapped = FALSE;
u8 *LCD_addr = LCDdst[block];
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From: <mta...@us...> - 2008-12-01 00:26:09
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Revision: 1162
http://desmume.svn.sourceforge.net/desmume/?rev=1162&view=rev
Author: mtabachenko
Date: 2008-12-01 00:26:06 +0000 (Mon, 01 Dec 2008)
Log Message:
-----------
core:
- fix bug in VRAM;
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-11-30 23:54:05 UTC (rev 1161)
+++ trunk/desmume/src/MMU.cpp 2008-12-01 00:26:06 UTC (rev 1162)
@@ -55,6 +55,8 @@
//#define _MMU_DEBUG
#ifdef _MMU_DEBUG
+
+#include <stdarg.h>
void mmu_log_debug(u32 adr, u8 proc, const char *fmt, ...)
{
if ((adr>=0x04000000 && adr<=0x04000800)
@@ -77,7 +79,7 @@
if (adr >= 0x4000004 && adr <= 0x40001C2) return; // ARM7 I/O Map
if (adr >= 0x4000204 && adr <= 0x4000308) return; // Memory and IRQ Control
if (adr >= 0x4000400 && adr <= 0x400051C) return; // Sound Registers
- if (adr >= 0x4100000 && adr <= 0x4000010) return; // IPC/ROM
+ if (adr >= 0x4100000 && adr <= 0x4100010) return; // IPC/ROM
if (adr >= 0x4800000 && adr <= 0x4808000) return; // WLAN Registers
}
@@ -413,8 +415,7 @@
u8 block = MMU.VRAM_MAP[engine][engine_offset];
if (block == 7) return NULL;
vram_addr -= MMU.LCD_VRAM_ADDR[block];
- u8 *tmp_addr = LCDdst[block] + vram_addr;
- return (tmp_addr);
+ return (LCDdst[block] + vram_addr);
}
return NULL;
}
@@ -441,8 +442,10 @@
static INLINE void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
{
+ if (!(VRAMBankCnt & 0x80)) return;
+ if (!(VRAMBankCnt & 0x07)) return;
+
u32 vram_map_addr = 0xFFFFFFFF;
- BOOL isMapped = FALSE;
u8 *LCD_addr = LCDdst[block];
switch (VRAMBankCnt & 0x07)
@@ -511,7 +514,7 @@
ARM9Mem.textureSlotAddr[slot_index] = LCD_addr;
gpu3D->NDS_3D_VramReconfigureSignal();
}
- return;
+ break;
case 4: // E
ARM9Mem.texPalSlot[0] = LCD_addr;
ARM9Mem.texPalSlot[1] = LCD_addr+0x2000;
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From: <lu...@us...> - 2008-12-04 18:46:09
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Revision: 1163
http://desmume.svn.sourceforge.net/desmume/?rev=1163&view=rev
Author: luigi__
Date: 2008-12-04 18:46:02 +0000 (Thu, 04 Dec 2008)
Log Message:
-----------
Fixed a few 3D function mismatches (for example setting light direction through reg at 0x040004C8 would assign the value as light color)
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-01 00:26:06 UTC (rev 1162)
+++ trunk/desmume/src/MMU.cpp 2008-12-04 18:46:02 UTC (rev 1163)
@@ -37,19 +37,19 @@
#include "rtc.h"
#include "GPU_osd.h"
#include "zero_private.h"
-#include "mc.h"
-
-static const int save_types[7][2] = {
- {MC_TYPE_AUTODETECT,1},
- {MC_TYPE_EEPROM1,MC_SIZE_4KBITS},
- {MC_TYPE_EEPROM2,MC_SIZE_64KBITS},
- {MC_TYPE_EEPROM2,MC_SIZE_512KBITS},
- {MC_TYPE_FRAM,MC_SIZE_256KBITS},
- {MC_TYPE_FLASH,MC_SIZE_2MBITS},
- {MC_TYPE_FLASH,MC_SIZE_4MBITS}
-};
-
+#include "mc.h"
+static const int save_types[7][2] = {
+ {MC_TYPE_AUTODETECT,1},
+ {MC_TYPE_EEPROM1,MC_SIZE_4KBITS},
+ {MC_TYPE_EEPROM2,MC_SIZE_64KBITS},
+ {MC_TYPE_EEPROM2,MC_SIZE_512KBITS},
+ {MC_TYPE_FRAM,MC_SIZE_256KBITS},
+ {MC_TYPE_FLASH,MC_SIZE_2MBITS},
+ {MC_TYPE_FLASH,MC_SIZE_4MBITS}
+};
+
+
#define ROM_MASK 3
//#define _MMU_DEBUG
@@ -2001,11 +2001,11 @@
((u32 *)(MMU.MMU_MEM[proc][0x40]))[0x460>>2] = val;
if(proc == ARMCPU_ARM9)
{
- gfx3d_glLoadMatrix4x4(val);
+ gfx3d_glMultMatrix4x4(val);
}
return;
}
- // Multiply 4x4 matrix - Parameters:12
+ // Multiply 4x3 matrix - Parameters:12
case 0x04000464:
{
((u32 *)(MMU.MMU_MEM[proc][0x40]))[0x464>>2] = val;
@@ -2191,7 +2191,7 @@
((u32 *)(MMU.MMU_MEM[proc][0x40]))[0x4C8>>2] = val;
if(proc == ARMCPU_ARM9)
{
- gfx3d_glLightColor (val);
+ gfx3d_glLightDirection(val);
}
return;
}
@@ -2904,8 +2904,8 @@
case 1 : dstinc = -sz; break;
case 2 : dstinc = 0; break;
case 3 : dstinc = sz; break; //reload
- default:
- return;
+ default:
+ return;
}
switch((u >> 2)&0x3) {
case 0 : srcinc = sz; break;
@@ -2913,8 +2913,8 @@
case 2 : srcinc = 0; break;
case 3 : // reserved
return;
- default:
- return;
+ default:
+ return;
}
if ((MMU.DMACrt[proc][num]>>26)&1)
for(; i < taille; ++i)
@@ -3486,11 +3486,11 @@
{
if(proc==0) _MMU_write8<0ul>(adr,val);
else _MMU_write8<1ul>(adr,val);
-}
-
-void mmu_select_savetype(int type, int *bmemtype, u32 *bmemsize) {
- if (type<0 || type > 5) return;
- *bmemtype=save_types[type][0];
- *bmemsize=save_types[type][1];
- mc_realloc(&MMU.bupmem, *bmemtype, *bmemsize);
-}
+}
+
+void mmu_select_savetype(int type, int *bmemtype, u32 *bmemsize) {
+ if (type<0 || type > 5) return;
+ *bmemtype=save_types[type][0];
+ *bmemsize=save_types[type][1];
+ mc_realloc(&MMU.bupmem, *bmemtype, *bmemsize);
+}
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From: <ric...@us...> - 2008-12-07 15:33:33
|
Revision: 1173
http://desmume.svn.sourceforge.net/desmume/?rev=1173&view=rev
Author: riccardom
Date: 2008-12-07 15:33:29 +0000 (Sun, 07 Dec 2008)
Log Message:
-----------
Make a loop counter variable unsigned to shut up gcc warnings.
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-07 15:28:44 UTC (rev 1172)
+++ trunk/desmume/src/MMU.cpp 2008-12-07 15:33:29 UTC (rev 1173)
@@ -586,7 +586,7 @@
MMU.LCD_VRAM_ADDR[block] = vram_map_addr;
MMU.LCDCenable[block] = TRUE;
- for (int i = 0; i < LCDdata[block][1]; i++)
+ for (uint i = 0; i < LCDdata[block][1]; i++)
MMU.VRAM_MAP[engine][engine_offset + i] = (u8)block;
//INFO("VRAM %i mapping: engine=%i (offset=%i), address = 0x%X, MST=%i\n", block, engine, engine_offset, MMU.LCD_VRAM_ADDR[block], VRAMBankCnt & 0x07);
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From: <ya...@us...> - 2008-12-07 15:54:13
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Revision: 1177
http://desmume.svn.sourceforge.net/desmume/?rev=1177&view=rev
Author: yabause
Date: 2008-12-07 15:54:10 +0000 (Sun, 07 Dec 2008)
Log Message:
-----------
fixed compilation for windows
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-07 15:53:35 UTC (rev 1176)
+++ trunk/desmume/src/MMU.cpp 2008-12-07 15:54:10 UTC (rev 1177)
@@ -586,7 +586,7 @@
MMU.LCD_VRAM_ADDR[block] = vram_map_addr;
MMU.LCDCenable[block] = TRUE;
- for (uint i = 0; i < LCDdata[block][1]; i++)
+ for (unsigned int i = 0; i < LCDdata[block][1]; i++)
MMU.VRAM_MAP[engine][engine_offset + i] = (u8)block;
//INFO("VRAM %i mapping: engine=%i (offset=%i), address = 0x%X, MST=%i\n", block, engine, engine_offset, MMU.LCD_VRAM_ADDR[block], VRAMBankCnt & 0x07);
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|
|
From: <mta...@us...> - 2008-12-08 10:18:54
|
Revision: 1186
http://desmume.svn.sourceforge.net/desmume/?rev=1186&view=rev
Author: mtabachenko
Date: 2008-12-08 10:18:50 +0000 (Mon, 08 Dec 2008)
Log Message:
-----------
- exclude check address range in VRAM (may crash in some games :( );
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-08 09:15:40 UTC (rev 1185)
+++ trunk/desmume/src/MMU.cpp 2008-12-08 10:18:50 UTC (rev 1186)
@@ -408,6 +408,7 @@
u8 engine = (vram_addr >> 21);
vram_addr &= 0x01FFFFF;
u8 engine_offset = (vram_addr >> 14);
+ if (engine_offset > 31) return NULL;
u8 block = MMU.VRAM_MAP[engine][engine_offset];
if (block == 7) return NULL;
vram_addr -= MMU.LCD_VRAM_ADDR[block];
@@ -452,11 +453,13 @@
addr -= MMU.LCD_VRAM_ADDR[block];
addr += LCDdata[block][0];
+#if 0
if ((addr < 0x6800000) || (addr> 0x68A3FFF)) // FIXME: this is hack
{
- //LOG("Address is out range 0x%X in block %i\n", addr, block);
+ LOG("Address is out range 0x%X in block %i\n", addr, block);
addr = save_addr;
}
+#endif
}
return (addr);
}
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|
|
From: <mta...@us...> - 2008-12-08 12:31:48
|
Revision: 1187
http://desmume.svn.sourceforge.net/desmume/?rev=1187&view=rev
Author: mtabachenko
Date: 2008-12-08 12:31:43 +0000 (Mon, 08 Dec 2008)
Log Message:
-----------
core:
- fix VRAM mapping control (now this correct, in future need only add WRAM mapping);
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-08 10:18:50 UTC (rev 1186)
+++ trunk/desmume/src/MMU.cpp 2008-12-08 12:31:43 UTC (rev 1187)
@@ -52,6 +52,8 @@
#define ROM_MASK 3
+//#define CHECK_VRAM
+
//#define _MMU_DEBUG
#ifdef _MMU_DEBUG
@@ -234,8 +236,8 @@
u32 gxIRQ = 0;
// VRAM mapping
-static u8 last_engine_offset[4] = {0x00, 0x00, 0x00, 0x00};
u8 *LCDdst[10] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
+u8 *EngineAddr[4] = { NULL, NULL, NULL, NULL };
const static u32 LCDdata[10][2]= {
{0x6800000, 8}, // Bank A
{0x6820000, 8}, // Bank B
@@ -305,10 +307,10 @@
void MMU_clearMem()
{
- memset(ARM9Mem.ARM9_ABG, 0, 0x080000); // TODO: remove this
- memset(ARM9Mem.ARM9_AOBJ, 0, 0x040000); // don't need now
- memset(ARM9Mem.ARM9_BBG, 0, 0x020000); //
- memset(ARM9Mem.ARM9_BOBJ, 0, 0x020000); // ----------------|
+ memset(ARM9Mem.ARM9_ABG, 0, 0x080000);
+ memset(ARM9Mem.ARM9_AOBJ, 0, 0x040000);
+ memset(ARM9Mem.ARM9_BBG, 0, 0x020000);
+ memset(ARM9Mem.ARM9_BOBJ, 0, 0x020000);
memset(ARM9Mem.ARM9_DTCM, 0, 0x4000);
memset(ARM9Mem.ARM9_ITCM, 0, 0x8000);
@@ -375,6 +377,11 @@
LCDdst[8] = ARM9Mem.ARM9_LCD + 0x98000; // Bank H
LCDdst[9] = ARM9Mem.ARM9_LCD + 0xA0000; // Bank I
+ EngineAddr[0] = ARM9Mem.ARM9_ABG; // Engine ABG
+ EngineAddr[1] = ARM9Mem.ARM9_BBG; // Engine BBG
+ EngineAddr[2] = ARM9Mem.ARM9_AOBJ; // Engine BOBJ
+ EngineAddr[3] = ARM9Mem.ARM9_BOBJ; // Engine BOBJ
+
for (int i = 0; i < 4; i++)
{
ARM9Mem.ExtPal[0][i] = ARM9Mem.ARM9_LCD;
@@ -408,9 +415,23 @@
u8 engine = (vram_addr >> 21);
vram_addr &= 0x01FFFFF;
u8 engine_offset = (vram_addr >> 14);
- if (engine_offset > 31) return NULL;
u8 block = MMU.VRAM_MAP[engine][engine_offset];
- if (block == 7) return NULL;
+ if (block == 7)
+ {
+ switch (engine)
+ {
+ case 0: // Engine ABG
+ return (ARM9Mem.ARM9_ABG + vram_addr);
+ case 1: // Engine BBG
+ return (ARM9Mem.ARM9_BBG + vram_addr);
+ case 2: // Engine AOBJ
+ return (ARM9Mem.ARM9_AOBJ + vram_addr);
+ case 3: // Engine BOBJ
+ return (ARM9Mem.ARM9_BOBJ + vram_addr);
+ }
+ LOG("render: VRAM not mapped to LCD\n");
+ return NULL;
+ }
vram_addr -= MMU.LCD_VRAM_ADDR[block];
return (LCDdst[block] + vram_addr);
}
@@ -430,36 +451,9 @@
addr &= 0x01FFFFF;
u8 engine_offset = (addr >> 14);
u8 block = MMU.VRAM_MAP[engine][engine_offset];
-
- if (block == 7) // corrections VRAM mapping
- {
- block = MMU.VRAM_MAP[engine][last_engine_offset[engine]];
-
- //LOG("Engine offset = %i/%i in block %i (size %i, offs %i): \n",
- //engine_offset, last_engine_offset[engine], block,
- //LCDdata[block][1], engine_offset+LCDdata[block][1]);
-
- for (int i = 0; i < LCDdata[block][1]; i++)
- {
- if (MMU.VRAM_MAP[engine][engine_offset + i] != 7)
- LOG("\nVRAM already mapping %i\n", i);
- MMU.VRAM_MAP[engine][engine_offset + i] = (u8)block;
- }
- }
- //LOG("VRAM %i: engine=%i (offset=%i), map address = 0x%X, MMU address = 0x%X\n", block, engine, engine_offset, vram_addr, *addr);
- last_engine_offset[engine] = engine_offset;
-
- //u32 tmp02 = addr;
+ if (block == 7) return save_addr; // not mapped to LCD
addr -= MMU.LCD_VRAM_ADDR[block];
addr += LCDdata[block][0];
-
-#if 0
- if ((addr < 0x6800000) || (addr> 0x68A3FFF)) // FIXME: this is hack
- {
- LOG("Address is out range 0x%X in block %i\n", addr, block);
- addr = save_addr;
- }
-#endif
}
return (addr);
}
@@ -588,7 +582,6 @@
{
ARM9Mem.ObjExtPal[0][0] = LCD_addr;
ARM9Mem.ObjExtPal[0][1] = LCD_addr + 0x2000;
-
}
break;
}
@@ -608,12 +601,14 @@
MMU.LCD_VRAM_ADDR[block] = vram_map_addr;
MMU.LCDCenable[block] = TRUE;
- for (unsigned int i = 0; i < LCDdata[block][1]; i++)
+ for (unsigned int i = 0; i <= LCDdata[block][1]; i++)
MMU.VRAM_MAP[engine][engine_offset + i] = (u8)block;
- //INFO("VRAM %i mapping: engine=%i (offset=%i), address = 0x%X, MST=%i\n", block, engine, engine_offset, MMU.LCD_VRAM_ADDR[block], VRAMBankCnt & 0x07);
+ //LOG("VRAM %i mapping: engine=%i (offset=%i, size=%i), address = 0x%X, MST=%i\n",
+ // block, engine, engine_offset, LCDdata[block][1]*0x4000, MMU.LCD_VRAM_ADDR[block], VRAMBankCnt & 0x07);
return;
}
+
MMU.LCDCenable[block] = FALSE;
}
@@ -1090,8 +1085,19 @@
if(proc == ARMCPU_ARM9) GPU_setBLDY_EVY(SubScreen.gpu,val) ;
break;
+#ifdef CHECKVRAM
+ case 0x4000247: // block 7
+ INFO("------- MMU write 08: writing in VRAM block 7 0x%X (stat=0x%X)\n", val,
+ T1ReadByte(MMU.MMU_MEM[proc][0x40], 0x241));
+ break;
+#endif
case REG_VRAMCNTA:
case REG_VRAMCNTB:
+#ifdef CHECKVRAM
+ if(proc == ARMCPU_ARM7)
+ INFO("******* MMU write 08: writing in VRAM block B 0x%X (stat=0x%X)\n", val,
+ T1ReadByte(MMU.MMU_MEM[proc][0x40], 0x241));
+#endif
case REG_VRAMCNTC:
case REG_VRAMCNTD:
case REG_VRAMCNTE:
@@ -1537,7 +1543,23 @@
}
return;
}
+#ifdef CHECKVRAM
+ case 0x4000247: // block 7
+ INFO("-------- MMU write 16: writing in VRAM block 7 0x%X\n", val);
+ break;
case REG_VRAMCNTA:
+ case REG_VRAMCNTB:
+ case REG_VRAMCNTC:
+ case REG_VRAMCNTD:
+ case REG_VRAMCNTE:
+ case REG_VRAMCNTF:
+ case REG_VRAMCNTG:
+ case REG_VRAMCNTH:
+ case REG_VRAMCNTI:
+ INFO("MMU write 16: VRAM block %i 0x%X\n", adr-REG_VRAMCNTA, val);
+ break;
+#else
+ case REG_VRAMCNTA:
MMU_write8(proc,adr,val & 0xFF) ;
MMU_write8(proc,adr+1,val >> 8) ;
@@ -1557,7 +1579,7 @@
case REG_VRAMCNTI:
MMU_write8(proc,adr,val & 0xFF) ;
return ;
-
+#endif
case REG_IE :
MMU.reg_IE[proc] = (MMU.reg_IE[proc]&0xFFFF0000) | val;
if ( MMU.reg_IME[proc]) {
@@ -2374,8 +2396,25 @@
//GPULOG("SUB INIT 32B %08X\r\n", val);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x1000, val);
return;
+#ifdef CHECKVRAM
+ case 0x4000247: // block 7
+ INFO("------- MMU write 32: writing in VRAM block 7 0x%X (stat=0x%X)\n", val,
+ T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x241));
+ break;
case REG_VRAMCNTA:
+ case REG_VRAMCNTB:
+ case REG_VRAMCNTC:
+ case REG_VRAMCNTD:
case REG_VRAMCNTE:
+ case REG_VRAMCNTF:
+ case REG_VRAMCNTG:
+ case REG_VRAMCNTH:
+ case REG_VRAMCNTI:
+ INFO("MMU write 32: VRAM block %i 0x%X\n", adr-REG_VRAMCNTA, val);
+ break;
+#else
+ case REG_VRAMCNTA:
+ case REG_VRAMCNTE:
MMU_write8(proc,adr,val & 0xFF) ;
MMU_write8(proc,adr+1,val >> 8) ;
MMU_write8(proc,adr+2,val >> 16) ;
@@ -2384,6 +2423,7 @@
case REG_VRAMCNTI:
MMU_write8(proc,adr,val & 0xFF) ;
return ;
+#endif
case REG_IME : {
u32 old_val = MMU.reg_IME[proc];
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|
|
From: <mta...@us...> - 2008-12-08 13:11:10
|
Revision: 1188
http://desmume.svn.sourceforge.net/desmume/?rev=1188&view=rev
Author: mtabachenko
Date: 2008-12-08 13:11:05 +0000 (Mon, 08 Dec 2008)
Log Message:
-----------
core:
- some fixes;
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-08 12:31:43 UTC (rev 1187)
+++ trunk/desmume/src/MMU.cpp 2008-12-08 13:11:05 UTC (rev 1188)
@@ -416,22 +416,7 @@
vram_addr &= 0x01FFFFF;
u8 engine_offset = (vram_addr >> 14);
u8 block = MMU.VRAM_MAP[engine][engine_offset];
- if (block == 7)
- {
- switch (engine)
- {
- case 0: // Engine ABG
- return (ARM9Mem.ARM9_ABG + vram_addr);
- case 1: // Engine BBG
- return (ARM9Mem.ARM9_BBG + vram_addr);
- case 2: // Engine AOBJ
- return (ARM9Mem.ARM9_AOBJ + vram_addr);
- case 3: // Engine BOBJ
- return (ARM9Mem.ARM9_BOBJ + vram_addr);
- }
- LOG("render: VRAM not mapped to LCD\n");
- return NULL;
- }
+ if (block == 7) return (EngineAddr[engine] + vram_addr);
vram_addr -= MMU.LCD_VRAM_ADDR[block];
return (LCDdst[block] + vram_addr);
}
@@ -462,6 +447,13 @@
{
if (!(VRAMBankCnt & 0x80)) return;
if (!(VRAMBankCnt & 0x07)) return;
+
+ for (int i = 0; i < 4; i++)
+ {
+ for (int t = 0; t < 32; t++)
+ if (MMU.VRAM_MAP[i][t] == block)
+ MMU.VRAM_MAP[i][t] = 7;
+ }
u32 vram_map_addr = 0xFFFFFFFF;
u8 *LCD_addr = LCDdst[block];
@@ -586,13 +578,6 @@
break;
}
- for (int i = 0; i < 4; i++)
- {
- for (int t = 0; t < 32; t++)
- if (MMU.VRAM_MAP[i][t] == block)
- MMU.VRAM_MAP[i][t] = 7;
- }
-
if (vram_map_addr != 0xFFFFFFFF)
{
u8 engine = (vram_map_addr >> 21);
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|
|
From: <lu...@us...> - 2008-12-13 20:30:39
|
Revision: 1194
http://desmume.svn.sourceforge.net/desmume/?rev=1194&view=rev
Author: luigi__
Date: 2008-12-13 20:30:31 +0000 (Sat, 13 Dec 2008)
Log Message:
-----------
Fixed ARM9 hardware division when the denom is zero (see http://nocash.emubase.de/gbatek.htm#dsmaths)
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-10 18:31:56 UTC (rev 1193)
+++ trunk/desmume/src/MMU.cpp 2008-12-13 20:30:31 UTC (rev 1194)
@@ -2530,8 +2530,8 @@
}
if(den==0)
{
- res = 0;
- mod = 0;
+ res = ((num < 0) ? 1 : -1);
+ mod = num;
cnt |= 0x4000;
cnt &= 0x7FFF;
}
@@ -2583,8 +2583,8 @@
}
if(den==0)
{
- res = 0;
- mod = 0;
+ res = ((num < 0) ? 1 : -1);
+ mod = num;
cnt |= 0x4000;
cnt &= 0x7FFF;
}
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|
|
From: <ric...@us...> - 2008-12-15 21:25:51
|
Revision: 1200
http://desmume.svn.sourceforge.net/desmume/?rev=1200&view=rev
Author: riccardom
Date: 2008-12-15 21:25:46 +0000 (Mon, 15 Dec 2008)
Log Message:
-----------
Make functions without declaration static and remove unused i variables.
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-14 19:48:43 UTC (rev 1199)
+++ trunk/desmume/src/MMU.cpp 2008-12-15 21:25:46 UTC (rev 1200)
@@ -41,7 +41,7 @@
#include "mc.h"
//http://home.utah.edu/~nahaj/factoring/isqrt.c.html
-u64 isqrt (u64 x) {
+static u64 isqrt (u64 x) {
u64 squaredbit, remainder, root;
if (x<1) return 0;
@@ -1340,7 +1340,7 @@
//=========================================================================================================
//=========================================================================================================
//================================================= MMU write 08
-void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
+static void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
{
#ifdef INTERNAL_DTCM_WRITE
if(((adr & ~0x3FFF) == MMU.DTCMRegion))
@@ -1531,7 +1531,7 @@
}
//================================================= MMU ARM9 write 16
-void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
+static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
{
#ifdef INTERNAL_DTCM_WRITE
if((adr & ~0x3FFF) == MMU.DTCMRegion)
@@ -2048,7 +2048,7 @@
}
//================================================= MMU ARM9 write 32
-void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
+static void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
{
#ifdef INTERNAL_DTCM_WRITE
if((adr&(~0x3FFF)) == MMU.DTCMRegion)
@@ -2698,8 +2698,6 @@
return;
case REG_GCROMCTRL :
{
- unsigned int i;
-
if(MEM_8(MMU.MMU_MEM[ARMCPU_ARM9], REG_GCCMDOUT) == 0xB7)
{
MMU.dscard[ARMCPU_ARM9].address = (MEM_8(MMU.MMU_MEM[ARMCPU_ARM9], REG_GCCMDOUT+1) << 24) | (MEM_8(MMU.MMU_MEM[ARMCPU_ARM9], REG_GCCMDOUT+2) << 16) | (MEM_8(MMU.MMU_MEM[ARMCPU_ARM9], REG_GCCMDOUT+3) << 8) | (MEM_8(MMU.MMU_MEM[ARMCPU_ARM9], REG_GCCMDOUT+4));
@@ -2795,7 +2793,7 @@
}
//================================================= MMU ARM9 read 08
-u8 FASTCALL _MMU_ARM9_read08(u32 adr)
+static u8 FASTCALL _MMU_ARM9_read08(u32 adr)
{
#ifdef INTERNAL_DTCM_READ
if((adr&(~0x3FFF)) == MMU.DTCMRegion)
@@ -2817,7 +2815,7 @@
}
//================================================= MMU ARM9 read 16
-u16 FASTCALL _MMU_ARM9_read16(u32 adr)
+static u16 FASTCALL _MMU_ARM9_read16(u32 adr)
{
#ifdef INTERNAL_DTCM_READ
if((adr&(~0x3FFF)) == MMU.DTCMRegion)
@@ -2878,7 +2876,7 @@
}
//================================================= MMU ARM9 read 32
-u32 FASTCALL _MMU_ARM9_read32(u32 adr)
+static u32 FASTCALL _MMU_ARM9_read32(u32 adr)
{
#ifdef INTERNAL_DTCM_READ
if((adr&(~0x3FFF)) == MMU.DTCMRegion)
@@ -3045,7 +3043,7 @@
//=========================================================================================================
//=========================================================================================================
//================================================= MMU ARM7 write 08
-void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
+static void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
{
// CFlash writing, Mic
if ((adr>=0x9000000)&&(adr<0x9900000))
@@ -3078,7 +3076,7 @@
}
//================================================= MMU ARM7 write 16
-void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
+static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
{
// CFlash writing, Mic
if ((adr>=0x08800000)&&(adr<0x09900000))
@@ -3485,7 +3483,7 @@
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
}
//================================================= MMU ARM7 write 32
-void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
+static void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
{
// CFlash writing, Mic
if ((adr>=0x9000000)&&(adr<0x9900000)) {
@@ -3720,8 +3718,6 @@
return;
case REG_GCROMCTRL :
{
- unsigned int i;
-
if(MEM_8(MMU.MMU_MEM[ARMCPU_ARM7], REG_GCCMDOUT) == 0xB7)
{
MMU.dscard[ARMCPU_ARM7].address = (MEM_8(MMU.MMU_MEM[ARMCPU_ARM7], REG_GCCMDOUT+1) << 24) | (MEM_8(MMU.MMU_MEM[ARMCPU_ARM7], REG_GCCMDOUT+2) << 16) | (MEM_8(MMU.MMU_MEM[ARMCPU_ARM7], REG_GCCMDOUT+3) << 8) | (MEM_8(MMU.MMU_MEM[ARMCPU_ARM7], REG_GCCMDOUT+4));
@@ -3778,7 +3774,7 @@
}
//================================================= MMU ARM7 read 08
-u8 FASTCALL _MMU_ARM7_read08(u32 adr)
+static u8 FASTCALL _MMU_ARM7_read08(u32 adr)
{
#ifdef EXPERIMENTAL_WIFI
/* wifi mac access */
@@ -3800,7 +3796,7 @@
return MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF]];
}
//================================================= MMU ARM7 read 16
-u16 FASTCALL _MMU_ARM7_read16(u32 adr)
+static u16 FASTCALL _MMU_ARM7_read16(u32 adr)
{
#ifdef EXPERIMENTAL_WIFI
/* wifi mac access */
@@ -3848,7 +3844,7 @@
return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]);
}
//================================================= MMU ARM7 read 32
-u32 FASTCALL _MMU_ARM7_read32(u32 adr)
+static u32 FASTCALL _MMU_ARM7_read32(u32 adr)
{
// CFlash reading, Mic
if ((adr>=0x9000000)&&(adr<0x9900000))
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|
|
From: <mta...@us...> - 2008-12-21 20:23:00
|
Revision: 1211
http://desmume.svn.sourceforge.net/desmume/?rev=1211&view=rev
Author: mtabachenko
Date: 2008-12-21 20:22:56 +0000 (Sun, 21 Dec 2008)
Log Message:
-----------
core:
- fixed silly bug in VRAM mapping (typo)
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-21 15:47:42 UTC (rev 1210)
+++ trunk/desmume/src/MMU.cpp 2008-12-21 20:22:56 UTC (rev 1211)
@@ -461,7 +461,7 @@
return (LCDdst[block] + vram_addr);
}
-//extern void NDS_Pause();
+extern void NDS_Pause();
static FORCEINLINE u32 MMU_LCDmap(u32 addr)
{
if ((addr < 0x6000000)) return addr;
@@ -481,25 +481,10 @@
u8 block = MMU.VRAM_MAP[engine][engine_offset];
if (block == 7) return (save_addr); // not mapped to LCD
- u32 addr2 = addr - MMU.LCD_VRAM_ADDR[block];
- u32 addr3 = addr2 + LCDdata[block][0];
- if (addr3 > 0x68A3FFF)
- {
- //INFO("Address 0x%X mapped to 0x%X (ret 0x%X, VRAM_ADDR 0x%X)\n", save_addr, addr3 , addr2, MMU.LCD_VRAM_ADDR[block]);
- //INFO("Engine %i; Engine offset %i, Block %i, addr 0x%X\n", engine, engine_offset, block, MMU.LCD_VRAM_ADDR[block]);
- //INFO("\n");
- //NDS_Pause();
-
- // This is incorrect. I made this temporally for non crash emu.
- // I will endeavour to the release to correct.
- return save_addr;
- }
- return (addr2 + LCDdata[block][0]);
- addr += LCDdata[block][0];
- return save_addr;
+ addr -= MMU.LCD_VRAM_ADDR[block];
+ return (addr + LCDdata[block][0]);
}
-//#define LOG_VRAM_ERROR() INFO("No data for block %i MST %i\n", block, VRAMBankCnt & 0x07);
-#define LOG_VRAM_ERROR() ;
+#define LOG_VRAM_ERROR() LOG("No data for block %i MST %i\n", block, VRAMBankCnt & 0x07);
static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
{
@@ -659,7 +644,7 @@
MMU.LCD_VRAM_ADDR[block] = vram_map_addr;
MMU.LCDCenable[block] = TRUE;
- for (unsigned int i = 0; i <= LCDdata[block][1]; i++)
+ for (unsigned int i = 0; i < LCDdata[block][1]; i++)
MMU.VRAM_MAP[engine][engine_offset + i] = (u8)block;
//INFO("VRAM %i mapping: eng=%i (offs=%i, size=%i), addr = 0x%X, MST=%i (faddr 0x%X)\n",
@@ -1714,6 +1699,31 @@
case REG_DISPA_WINOUT:
GPU_setWINOUT16(MainScreen.gpu, val) ;
break ;
+
+ case REG_DISPB_BG0HOFS:
+ GPU_setBGxHOFS(0, SubScreen.gpu, val);
+ break;
+ case REG_DISPB_BG0VOFS:
+ GPU_setBGxVOFS(0, SubScreen.gpu, val);
+ break;
+ case REG_DISPB_BG1HOFS:
+ GPU_setBGxHOFS(1, SubScreen.gpu, val);
+ break;
+ case REG_DISPB_BG1VOFS:
+ GPU_setBGxVOFS(1, SubScreen.gpu, val);
+ break;
+ case REG_DISPB_BG2HOFS:
+ GPU_setBGxHOFS(2, SubScreen.gpu, val);
+ break;
+ case REG_DISPB_BG2VOFS:
+ GPU_setBGxVOFS(2, SubScreen.gpu, val);
+ break;
+ case REG_DISPB_BG3HOFS:
+ GPU_setBGxHOFS(3, SubScreen.gpu, val);
+ break;
+ case REG_DISPB_BG3VOFS:
+ GPU_setBGxVOFS(3, SubScreen.gpu, val);
+ break;
case REG_DISPB_WININ:
GPU_setWININ(SubScreen.gpu, val) ;
break ;
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <lu...@us...> - 2008-12-22 10:45:29
|
Revision: 1212
http://desmume.svn.sourceforge.net/desmume/?rev=1212&view=rev
Author: luigi__
Date: 2008-12-22 10:45:25 +0000 (Mon, 22 Dec 2008)
Log Message:
-----------
Fixed 16-bit and 32-bit accesses to the VRAM regs
Added basic support for the VRAMSTAT, WRAMCNT, WRAMSTAT and EXMEMCNT regs (writes to these regs now write the appropriate values at the other side)
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-21 20:22:56 UTC (rev 1211)
+++ trunk/desmume/src/MMU.cpp 2008-12-22 10:45:25 UTC (rev 1212)
@@ -102,20 +102,20 @@
{
if (adr >= 0x4000000 && adr <= 0x400006C) return; // Display Engine A
if (adr >= 0x40000B0 && adr <= 0x4000132) return; // DMA, Timers and Keypad
- if (adr >= 0x4000180 && adr <= 0x40001BA) return; // IPC/ROM
- if (adr >= 0x4000204 && adr <= 0x4000249) return; // Memory & IRQ control
- if (adr >= 0x4000280 && adr <= 0x4000304) return; // Maths
- if (adr >= 0x4000320 && adr <= 0x40006A3) return; // 3D dispaly engine
- if (adr >= 0x4100000 && adr <= 0x4100012) return; // IPC/ROM
+ //if (adr >= 0x4000180 && adr <= 0x40001BA) return; // IPC/ROM
+ //if (adr >= 0x4000204 && adr <= 0x4000249) return; // Memory & IRQ control
+ ///if (adr >= 0x4000280 && adr <= 0x4000304) return; // Maths
+ //if (adr >= 0x4000320 && adr <= 0x40006A3) return; // 3D dispaly engine
+ //if (adr >= 0x4100000 && adr <= 0x4100012) return; // IPC/ROM
}
else
{
- if (adr >= 0x4000000 && adr <= 0x4000003) return; // ????
+ //if (adr >= 0x4000000 && adr <= 0x4000003) return; // ????
if (adr >= 0x4000004 && adr <= 0x40001C2) return; // ARM7 I/O Map
- if (adr >= 0x4000204 && adr <= 0x4000308) return; // Memory and IRQ Control
- if (adr >= 0x4000400 && adr <= 0x400051C) return; // Sound Registers
- if (adr >= 0x4100000 && adr <= 0x4100010) return; // IPC/ROM
- if (adr >= 0x4800000 && adr <= 0x4808000) return; // WLAN Registers
+ //if (adr >= 0x4000204 && adr <= 0x4000308) return; // Memory and IRQ Control
+ //if (adr >= 0x4000400 && adr <= 0x400051C) return; // Sound Registers
+ //if (adr >= 0x4100000 && adr <= 0x4100010) return; // IPC/ROM
+ //if (adr >= 0x4800000 && adr <= 0x4808000) return; // WLAN Registers
}
va_list list;
@@ -511,6 +511,8 @@
case 2: // C
case 3: // D Engine A, BG
vram_map_addr = ((VRAMBankCnt >> 3) & 3) * 0x20000;
+ if(block == 2) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 2);
+ if(block == 3) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 1);
break ;
case 4: // E Engine A, BG
vram_map_addr = 0x0000000;
@@ -538,6 +540,12 @@
case 1: // B Engine A, OBJ
vram_map_addr = 0x0400000 + (((VRAMBankCnt>>3)&1)*0x20000);
break;
+ case 2: // C
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 1);
+ break;
+ case 3: // D
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 2);
+ break;
case 4: // E Engine A, OBJ
vram_map_addr = 0x0400000;
break;
@@ -572,6 +580,8 @@
int slot_index = (VRAMBankCnt >> 3) & 0x3;
ARM9Mem.textureSlotAddr[slot_index] = LCD_addr;
gpu3D->NDS_3D_VramReconfigureSignal();
+ if(block == 2) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 2);
+ if(block == 3) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 1);
}
break;
case 4: // E
@@ -602,9 +612,11 @@
{
case 2: // C Engine B, BG
vram_map_addr = 0x0200000;
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 2);
break ;
case 3: // D Engine B, OBJ
vram_map_addr = 0x0600000;
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 1);
break ;
case 4: // E Engine A, BG
ARM9Mem.ExtPal[0][0] = LCD_addr;
@@ -1501,12 +1513,11 @@
GPU_setBLDY_EVY(SubScreen.gpu,val) ;
break;
- #ifdef CHECKVRAM
- case 0x4000247: // block 7
- INFO("------- MMU write 08: writing in VRAM block 7 0x%X (stat=0x%X)\n", val,
- T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x241));
+ case 0x4000247:
+ /* Update WRAMSTAT at the ARM7 side */
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, val);
break;
- #endif
+
case REG_VRAMCNTA:
case REG_VRAMCNTB:
case REG_VRAMCNTC:
@@ -1765,6 +1776,14 @@
return;
+ case REG_EXMEMCNT:
+ {
+ u16 oldval = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204);
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x204, val);
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204, (val & 0xFF80) | (oldval & 0x7F));
+ }
+ return;
+
case REG_AUXSPICNT:
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][(REG_AUXSPICNT >> 20) & 0xff], REG_AUXSPICNT & 0xfff, val);
AUX_SPI_CNT = val;
@@ -1821,25 +1840,20 @@
return;
case REG_VRAMCNTA:
- case REG_VRAMCNTB:
case REG_VRAMCNTC:
- case REG_VRAMCNTD:
case REG_VRAMCNTE:
- case REG_VRAMCNTF:
- case REG_VRAMCNTG:
MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, val >> 8);
return;
- case REG_VRAMCNTG+1: // WRAM ???
- MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, val >> 8);
+ case REG_VRAMCNTG:
+ MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
+ /* Update WRAMSTAT at the ARM7 side */
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, val >> 8);
return;
case REG_VRAMCNTH:
MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, val >> 8);
return;
- case REG_VRAMCNTI:
- MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
- return;
case REG_IME:
{
@@ -2294,29 +2308,22 @@
return;
case REG_VRAMCNTA:
- case REG_VRAMCNTB:
- case REG_VRAMCNTC:
- case REG_VRAMCNTD:
- case REG_VRAMCNTE:
- case REG_VRAMCNTF:
- case REG_VRAMCNTG:
MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, (val >> 8) & 0xFF);
MMU_VRAMmapControl(adr-REG_VRAMCNTA+2, (val >> 16) & 0xFF);
MMU_VRAMmapControl(adr-REG_VRAMCNTA+3, (val >> 24) & 0xFF);
return;
- case REG_VRAMCNTG+1:
+ case REG_VRAMCNTE:
MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, (val >> 8) & 0xFF);
MMU_VRAMmapControl(adr-REG_VRAMCNTA+2, (val >> 16) & 0xFF);
+ /* Update WRAMSTAT at the ARM7 side */
+ T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, (val >> 24) & 0xFF);
return;
case REG_VRAMCNTH:
MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, (val >> 8) & 0xFF);
return;
- case REG_VRAMCNTI:
- MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
- return;
case REG_IME :
{
@@ -2950,6 +2957,13 @@
/* Address is an IO register */
switch(adr)
{
+ case REG_EXMEMCNT:
+ {
+ u16 oldval = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204);
+ T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204, (val & 0x7F) | (oldval & 0xFF80));
+ }
+ return;
+
case REG_AUXSPICNT:
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPICNT >> 20) & 0xff], REG_AUXSPICNT & 0xfff, val);
AUX_SPI_CNT = val;
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ric...@us...> - 2008-12-23 23:26:09
|
Revision: 1224
http://desmume.svn.sourceforge.net/desmume/?rev=1224&view=rev
Author: riccardom
Date: 2008-12-23 22:49:46 +0000 (Tue, 23 Dec 2008)
Log Message:
-----------
Fix missing indentation.
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-23 22:41:37 UTC (rev 1223)
+++ trunk/desmume/src/MMU.cpp 2008-12-23 22:49:46 UTC (rev 1224)
@@ -730,12 +730,12 @@
case 0:
num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
- break;
+ break;
case 3: //gbatek says this is same as mode 1
case 1:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
- break;
+ break;
case 2:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x298);
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <mta...@us...> - 2008-12-24 10:27:45
|
Revision: 1229
http://desmume.svn.sourceforge.net/desmume/?rev=1229&view=rev
Author: mtabachenko
Date: 2008-12-24 10:27:39 +0000 (Wed, 24 Dec 2008)
Log Message:
-----------
core:
- fix debug log in MMU;
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-24 02:21:46 UTC (rev 1228)
+++ trunk/desmume/src/MMU.cpp 2008-12-24 10:27:39 UTC (rev 1229)
@@ -22,6 +22,8 @@
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+//#define NEW_IRQ 1
+
#include <stdlib.h>
#include <math.h>
#include <string.h>
@@ -92,46 +94,55 @@
#ifdef _MMU_DEBUG
#include <stdarg.h>
-void mmu_log_debug(u32 adr, u8 proc, const char *fmt, ...)
+void mmu_log_debug_ARM9(u32 adr, const char *fmt, ...)
{
- if ((adr>=0x04000000 && adr<=0x04000800)
- ||(adr>=0x04100000 && adr<=0x04100010)
- ||(adr>=0x04800000 && adr<=0x04808000))
- {
- if (proc==ARMCPU_ARM9)
- {
- if (adr >= 0x4000000 && adr <= 0x400006C) return; // Display Engine A
- if (adr >= 0x40000B0 && adr <= 0x4000132) return; // DMA, Timers and Keypad
- //if (adr >= 0x4000180 && adr <= 0x40001BA) return; // IPC/ROM
- //if (adr >= 0x4000204 && adr <= 0x4000249) return; // Memory & IRQ control
- ///if (adr >= 0x4000280 && adr <= 0x4000304) return; // Maths
- //if (adr >= 0x4000320 && adr <= 0x40006A3) return; // 3D dispaly engine
- //if (adr >= 0x4100000 && adr <= 0x4100012) return; // IPC/ROM
- }
- else
- {
- //if (adr >= 0x4000000 && adr <= 0x4000003) return; // ????
- if (adr >= 0x4000004 && adr <= 0x40001C2) return; // ARM7 I/O Map
- //if (adr >= 0x4000204 && adr <= 0x4000308) return; // Memory and IRQ Control
- //if (adr >= 0x4000400 && adr <= 0x400051C) return; // Sound Registers
- //if (adr >= 0x4100000 && adr <= 0x4100010) return; // IPC/ROM
- //if (adr >= 0x4800000 && adr <= 0x4808000) return; // WLAN Registers
- }
+ if (adr < 0x4000000) return;
+ if (adr > 0x4100014) return;
- va_list list;
- char msg[512];
+ if (adr >= 0x4000000 && adr <= 0x400006E) return; // Display Engine A
+ if (adr >= 0x40000B0 && adr <= 0x4000134) return; // DMA, Timers and Keypad
+ if (adr >= 0x4000180 && adr <= 0x40001BC) return; // IPC/ROM
+ if (adr >= 0x4000204 && adr <= 0x400024A) return; // Memory & IRQ control
+ if (adr >= 0x4000280 && adr <= 0x4000306) return; // Maths
+ if (adr >= 0x4000320 && adr <= 0x40006A3) return; // 3D dispaly engine
+ if (adr >= 0x4001000 && adr <= 0x400106E) return; // Display Engine B
+ if (adr >= 0x4100000 && adr <= 0x4100014) return; // IPC/ROM
- memset(msg,0,512);
+ va_list list;
+ char msg[512];
- va_start(list,fmt);
- _vsnprintf(msg,511,fmt,list);
- va_end(list);
+ memset(msg,0,512);
- INFO("MMU ARM%s 0x%08X: %s\n",proc==ARMCPU_ARM9?"9":"7",adr, msg);
- }
+ va_start(list,fmt);
+ _vsnprintf(msg,511,fmt,list);
+ va_end(list);
+
+ INFO("MMU ARM9 0x%08X: %s\n", adr, msg);
}
-#else
-#define mmu_log_debug(...)
+
+void mmu_log_debug_ARM7(u32 adr, const char *fmt, ...)
+{
+ if (adr < 0x4000004) return;
+ if (adr > 0x4808FFF) return;
+
+ if (adr >= 0x4000004 && adr <= 0x40001C4) return; // ARM7 I/O Map
+ if (adr >= 0x4000204 && adr <= 0x400030C) return; // Memory and IRQ Control
+ if (adr >= 0x4000400 && adr <= 0x400051E) return; // Sound Registers
+ if (adr >= 0x4100000 && adr <= 0x4100014) return; // IPC/ROM
+ //if (adr >= 0x4800000 && adr <= 0x4808FFF) return; // WLAN Registers
+
+ va_list list;
+ char msg[512];
+
+ memset(msg,0,512);
+
+ va_start(list,fmt);
+ _vsnprintf(msg,511,fmt,list);
+ va_end(list);
+
+ INFO("MMU ARM7 0x%08X: %s\n", adr, msg);
+
+}
#endif
/*
@@ -730,12 +741,12 @@
case 0:
num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
- break;
+ break;
case 3: //gbatek says this is same as mode 1
case 1:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
- break;
+ break;
case 2:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x298);
@@ -1529,11 +1540,6 @@
case REG_VRAMCNTI:
MMU_VRAMmapControl(adr-REG_VRAMCNTA, val);
break;
- case REG_DISPA_DISPCAPCNT :
- //INFO("MMU write8: REG_DISPA_DISPCAPCNT 0x%X\n", val);
- GPU_set_DISPCAPCNT(val);
- T1WriteByte(ARM9Mem.ARM9_REG, 0x64, val);
- break;
#ifdef LOG_CARD
case 0x040001A0 : /* TODO (clear): ??? */
case 0x040001A1 :
@@ -1549,6 +1555,9 @@
LOG("%08X : %02X\r\n", adr, val);
#endif
}
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM9(adr, "(write08) %0x%X", val);
+#endif
MMU.MMU_MEM[ARMCPU_ARM9][0x40][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val;
return;
}
@@ -2125,6 +2134,9 @@
return;
//case REG_AUXSPICNT : execute = FALSE;
}
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM9(adr, "(write16) %0x%X", val);
+#endif
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
return;
}
@@ -2639,6 +2651,10 @@
return;
}
}
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM9(adr, "(write32) %0x%X", val);
+#endif
+
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
return;
}
@@ -2665,6 +2681,10 @@
if ((adr>=0x9000000)&&(adr<0x9900000))
return (unsigned char)cflash_read(adr);
#endif
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM9(adr, "(read08) %0x%X",
+ MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF]]);
+#endif
adr = MMU_LCDmap(adr);
@@ -2723,6 +2743,10 @@
case REG_POSTFLG :
return 1;
}
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM9(adr, "(read16) %0x%X",
+ T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]));
+#endif
return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]);
}
@@ -2877,6 +2901,10 @@
return val;
}
}
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM9(adr, "(read32) %0x%X",
+ T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]));
+#endif
return T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]);
}
@@ -2917,6 +2945,9 @@
if ( adr == REG_RTC ) rtcWrite(val);
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM7(adr, "(write08) %0x%X", val);
+#endif
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]]=val;
}
@@ -3328,6 +3359,9 @@
return;
//case REG_AUXSPICNT : execute = FALSE;
}
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM7(adr, "(write16) %0x%X", val);
+#endif
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
return;
}
@@ -3618,6 +3652,9 @@
}
return;
}
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM7(adr, "(write32) %0x%X", val);
+#endif
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
return;
}
@@ -3646,6 +3683,11 @@
if (adr == REG_RTC) return rtcRead();
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM7(adr, "(read08) %0x%X",
+ MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF]]);
+#endif
+
return MMU.MMU_MEM[ARMCPU_ARM7][(adr>>20)&0xFF][adr&MMU.MMU_MASK[ARMCPU_ARM7][(adr>>20)&0xFF]];
}
//================================================= MMU ARM7 read 16
@@ -3690,9 +3732,13 @@
case REG_POSTFLG :
return 1;
}
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM7(adr, "(read16) %0x%X",
+ T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]));
+#endif
return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]);
}
-
+
/* Returns data from memory */
return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]);
}
@@ -3772,6 +3818,10 @@
return val;
}
}
+#ifdef _MMU_DEBUG
+ mmu_log_debug_ARM7(adr, "(read32) %0x%X",
+ T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]));
+#endif
return T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20)]);
}
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|
|
From: <lu...@us...> - 2008-12-26 17:35:30
|
Revision: 1244
http://desmume.svn.sourceforge.net/desmume/?rev=1244&view=rev
Author: luigi__
Date: 2008-12-26 17:35:28 +0000 (Fri, 26 Dec 2008)
Log Message:
-----------
Oops, I forgot that the div/sqrt cycles are in 33 mhz units, not 66mhz units...
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-26 16:29:36 UTC (rev 1243)
+++ trunk/desmume/src/MMU.cpp 2008-12-26 17:35:28 UTC (rev 1244)
@@ -730,7 +730,7 @@
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B4, 0);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B0, cnt | 0x8000);
- MMU.sqrtCycles = (nds.cycles + 26);
+ MMU.sqrtCycles = (nds.cycles + 13);
MMU.sqrtResult = ret;
MMU.sqrtCnt = (cnt & 0x7FFF);
MMU.sqrtRunning = TRUE;
@@ -746,18 +746,18 @@
case 0:
num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
- MMU.divCycles = (nds.cycles + 34);
+ MMU.divCycles = (nds.cycles + 18);
break;
case 3: //gbatek says this is same as mode 1
case 1:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
- MMU.divCycles = (nds.cycles + 68);
+ MMU.divCycles = (nds.cycles + 34);
break;
case 2:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x298);
- MMU.divCycles = (nds.cycles + 68);
+ MMU.divCycles = (nds.cycles + 34);
break;
}
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|
|
From: <lu...@us...> - 2008-12-26 21:03:57
|
Revision: 1246
http://desmume.svn.sourceforge.net/desmume/?rev=1246&view=rev
Author: luigi__
Date: 2008-12-26 21:03:53 +0000 (Fri, 26 Dec 2008)
Log Message:
-----------
Oh, stupid of me : I was wrong with div/sqrt cycles again. They must be doubled to be 33mhz units, ie 13 cycles in 33mhz would be 26 cycles for nds.cycles.
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-26 20:05:43 UTC (rev 1245)
+++ trunk/desmume/src/MMU.cpp 2008-12-26 21:03:53 UTC (rev 1246)
@@ -730,7 +730,7 @@
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B4, 0);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B0, cnt | 0x8000);
- MMU.sqrtCycles = (nds.cycles + 13);
+ MMU.sqrtCycles = (nds.cycles + 26);
MMU.sqrtResult = ret;
MMU.sqrtCnt = (cnt & 0x7FFF);
MMU.sqrtRunning = TRUE;
@@ -746,18 +746,18 @@
case 0:
num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
- MMU.divCycles = (nds.cycles + 18);
+ MMU.divCycles = (nds.cycles + 36);
break;
case 3: //gbatek says this is same as mode 1
case 1:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
- MMU.divCycles = (nds.cycles + 34);
+ MMU.divCycles = (nds.cycles + 68);
break;
case 2:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x298);
- MMU.divCycles = (nds.cycles + 34);
+ MMU.divCycles = (nds.cycles + 68);
break;
}
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|
|
From: <lu...@us...> - 2008-12-27 19:19:14
|
Revision: 1261
http://desmume.svn.sourceforge.net/desmume/?rev=1261&view=rev
Author: luigi__
Date: 2008-12-27 19:19:06 +0000 (Sat, 27 Dec 2008)
Log Message:
-----------
Removed the proc variables for execdiv and execsqrt since the ARM7 deosn't have the div/sqrt funcs.
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-27 11:09:16 UTC (rev 1260)
+++ trunk/desmume/src/MMU.cpp 2008-12-27 19:19:06 UTC (rev 1261)
@@ -708,25 +708,24 @@
}
char txt[80];
-template<u32 proc>
void execsqrt() {
u32 ret;
- u16 cnt = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x2B0);
+ u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0);
switch(cnt&1)
{
case 0: {
- u32 v = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x2B8);
+ u32 v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
ret = isqrt(v);
break;
}
case 1: {
- u64 v = T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x2B8);
+ u64 v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
ret = isqrt(v);
break;
}
}
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B4, 0);
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B0, cnt | 0x8000);
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B4, 0);
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0, cnt | 0x8000);
MMU.sqrtCycles = (nds.cycles + 26);
MMU.sqrtResult = ret;
@@ -734,27 +733,26 @@
MMU.sqrtRunning = TRUE;
}
-template<u32 proc>
void execdiv() {
- u16 cnt = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x280);
+ u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280);
s64 num,den;
s64 res,mod;
switch(cnt&3)
{
case 0:
- num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x290);
- den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
+ num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
+ den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
MMU.divCycles = (nds.cycles + 36);
break;
case 3: //gbatek says this is same as mode 1
case 1:
- num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
- den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
+ num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
+ den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
MMU.divCycles = (nds.cycles + 68);
break;
case 2:
- num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
- den = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x298);
+ num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
+ den = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
MMU.divCycles = (nds.cycles + 68);
break;
}
@@ -777,11 +775,11 @@
(u32)(den>>32), (u32)den,
(u32)(res>>32), (u32)res);
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A0, 0);
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A4, 0);
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A8, 0);
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2AC, 0);
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x280, ((cnt & 0xBFFF) | 0x8000));
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, 0);
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, 0);
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, 0);
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2AC, 0);
+ T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280, ((cnt & 0xBFFF) | 0x8000));
MMU.divResult = res;
MMU.divMod = mod;
@@ -2421,26 +2419,26 @@
case REG_DIVDENOM :
{
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298, val);
- execdiv<ARMCPU_ARM9>();
+ execdiv();
return;
}
case REG_DIVDENOM+4 :
{
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x29C, val);
- execdiv<ARMCPU_ARM9>();
+ execdiv();
return;
}
case REG_SQRTPARAM :
{
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8, val);
- execsqrt<ARMCPU_ARM9>();
+ execsqrt();
return;
}
case REG_SQRTPARAM+4 :
{
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2BC, val);
- execsqrt<ARMCPU_ARM9>();
+ execsqrt();
return;
}
case REG_IPCSYNC :
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|
|
From: <sha...@us...> - 2008-12-28 14:27:29
|
Revision: 1269
http://desmume.svn.sourceforge.net/desmume/?rev=1269&view=rev
Author: shashClp
Date: 2008-12-28 14:27:17 +0000 (Sun, 28 Dec 2008)
Log Message:
-----------
[2471938] Applied patch attached on this issue.
- This is too from the infamous r1196, which I already
said was useless and stupid.
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-28 12:13:19 UTC (rev 1268)
+++ trunk/desmume/src/MMU.cpp 2008-12-28 14:27:17 UTC (rev 1269)
@@ -1,3727 +1,3712 @@
-/* Copyright (C) 2006 yopyop
- yop...@if...
- yopyop156.ifrance.com
-
- Copyright (C) 2007 shash
- Copyright (C) 2007-2008 DeSmuME team
-
- This file is part of DeSmuME
-
- DeSmuME is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- DeSmuME is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with DeSmuME; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-//#define NEW_IRQ 1
-
-#include <stdlib.h>
-#include <math.h>
-#include <string.h>
-#include <assert.h>
-
-#include "debug.h"
-#include "NDSSystem.h"
-#include "cflash.h"
-#include "cp15.h"
-#include "wifi.h"
-#include "registers.h"
-#include "render3D.h"
-#include "gfx3d.h"
-#include "rtc.h"
-#include "GPU_osd.h"
-#include "zero_private.h"
-#include "mc.h"
-
-//http://home.utah.edu/~nahaj/factoring/isqrt.c.html
-static u64 isqrt (u64 x) {
- u64 squaredbit, remainder, root;
-
- if (x<1) return 0;
-
- /* Load the binary constant 01 00 00 ... 00, where the number
- * of zero bits to the right of the single one bit
- * is even, and the one bit is as far left as is consistant
- * with that condition.)
- */
- squaredbit = (u64) ((((u64) ~0LL) >> 1) &
- ~(((u64) ~0LL) >> 2));
- /* This portable load replaces the loop that used to be
- * here, and was donated by leg...@xm...
- */
-
- /* Form bits of the answer. */
- remainder = x; root = 0;
- while (squaredbit > 0) {
- if (remainder >= (squaredbit | root)) {
- remainder -= (squaredbit | root);
- root >>= 1; root |= squaredbit;
- } else {
- root >>= 1;
- }
- squaredbit >>= 2;
- }
-
- return root;
-}
-
-
-static const int save_types[7][2] = {
- {MC_TYPE_AUTODETECT,1},
- {MC_TYPE_EEPROM1,MC_SIZE_4KBITS},
- {MC_TYPE_EEPROM2,MC_SIZE_64KBITS},
- {MC_TYPE_EEPROM2,MC_SIZE_512KBITS},
- {MC_TYPE_FRAM,MC_SIZE_256KBITS},
- {MC_TYPE_FLASH,MC_SIZE_2MBITS},
- {MC_TYPE_FLASH,MC_SIZE_4MBITS}
-};
-
-u16 partie = 1;
-
-#define ROM_MASK 3
-
-//#define _MMU_DEBUG
-
-#ifdef _MMU_DEBUG
-
-#include <stdarg.h>
-void mmu_log_debug_ARM9(u32 adr, const char *fmt, ...)
-{
- if (adr < 0x4000000) return;
- if (adr > 0x4100014) return;
-
- if (adr >= 0x4000000 && adr <= 0x400006E) return; // Display Engine A
- if (adr >= 0x40000B0 && adr <= 0x4000134) return; // DMA, Timers and Keypad
- if (adr >= 0x4000180 && adr <= 0x40001BC) return; // IPC/ROM
- if (adr >= 0x4000204 && adr <= 0x400024A) return; // Memory & IRQ control
- if (adr >= 0x4000280 && adr <= 0x4000306) return; // Maths
- if (adr >= 0x4000320 && adr <= 0x40006A3) return; // 3D dispaly engine
- if (adr >= 0x4001000 && adr <= 0x400106E) return; // Display Engine B
- if (adr >= 0x4100000 && adr <= 0x4100014) return; // IPC/ROM
-
- va_list list;
- char msg[512];
-
- memset(msg,0,512);
-
- va_start(list,fmt);
- _vsnprintf(msg,511,fmt,list);
- va_end(list);
-
- INFO("MMU ARM9 0x%08X: %s\n", adr, msg);
-}
-
-void mmu_log_debug_ARM7(u32 adr, const char *fmt, ...)
-{
- if (adr < 0x4000004) return;
- if (adr > 0x4808FFF) return;
-
- if (adr >= 0x4000004 && adr <= 0x40001C4) return; // ARM7 I/O Map
- if (adr >= 0x4000204 && adr <= 0x400030C) return; // Memory and IRQ Control
- if (adr >= 0x4000400 && adr <= 0x400051E) return; // Sound Registers
- if (adr >= 0x4100000 && adr <= 0x4100014) return; // IPC/ROM
- //if (adr >= 0x4800000 && adr <= 0x4808FFF) return; // WLAN Registers
-
- va_list list;
- char msg[512];
-
- memset(msg,0,512);
-
- va_start(list,fmt);
- _vsnprintf(msg,511,fmt,list);
- va_end(list);
-
- INFO("MMU ARM7 0x%08X: %s\n", adr, msg);
-
-}
-#endif
-
-/*
- *
- */
-#define EARLY_MEMORY_ACCESS 1
-
-#define INTERNAL_DTCM_READ 1
-#define INTERNAL_DTCM_WRITE 1
-
-//#define LOG_CARD
-//#define LOG_GPU
-//#define LOG_DMA
-//#define LOG_DMA2
-//#define LOG_DIV
-
-char szRomPath[512];
-char szRomBaseName[512];
-
-#define DUP2(x) x, x
-#define DUP4(x) x, x, x, x
-#define DUP8(x) x, x, x, x, x, x, x, x
-#define DUP16(x) x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x
-
-MMU_struct MMU;
-
-u8 * MMU_struct::MMU_MEM[2][256] = {
- //arm9
- {
- /* 0X*/ DUP16(ARM9Mem.ARM9_ITCM),
- /* 1X*/ //DUP16(ARM9Mem.ARM9_ITCM)
- /* 1X*/ DUP16(MMU.UNUSED_RAM),
- /* 2X*/ DUP16(ARM9Mem.MAIN_MEM),
- /* 3X*/ DUP16(MMU.SWIRAM),
- /* 4X*/ DUP16(ARM9Mem.ARM9_REG),
- /* 5X*/ DUP16(ARM9Mem.ARM9_VMEM),
- /* 6X*/ DUP2(ARM9Mem.ARM9_ABG),
- DUP2(ARM9Mem.ARM9_BBG),
- DUP2(ARM9Mem.ARM9_AOBJ),
- DUP2(ARM9Mem.ARM9_BOBJ),
- DUP8(ARM9Mem.ARM9_LCD),
- /* 7X*/ DUP16(ARM9Mem.ARM9_OAM),
- /* 8X*/ DUP16(NULL),
- /* 9X*/ DUP16(NULL),
- /* AX*/ DUP16(MMU.CART_RAM),
- /* BX*/ DUP16(MMU.UNUSED_RAM),
- /* CX*/ DUP16(MMU.UNUSED_RAM),
- /* DX*/ DUP16(MMU.UNUSED_RAM),
- /* EX*/ DUP16(MMU.UNUSED_RAM),
- /* FX*/ DUP16(ARM9Mem.ARM9_BIOS)
- },
- //arm7
- {
- /* 0X*/ DUP16(MMU.ARM7_BIOS),
- /* 1X*/ DUP16(MMU.UNUSED_RAM),
- /* 2X*/ DUP16(ARM9Mem.MAIN_MEM),
- /* 3X*/ DUP8(MMU.SWIRAM),
- DUP8(MMU.ARM7_ERAM),
- /* 4X*/ DUP8(MMU.ARM7_REG),
- DUP8(MMU.ARM7_WIRAM),
- /* 5X*/ DUP16(MMU.UNUSED_RAM),
- /* 6X*/ DUP16(ARM9Mem.ARM9_ABG),
- /* 7X*/ DUP16(MMU.UNUSED_RAM),
- /* 8X*/ DUP16(NULL),
- /* 9X*/ DUP16(NULL),
- /* AX*/ DUP16(MMU.CART_RAM),
- /* BX*/ DUP16(MMU.UNUSED_RAM),
- /* CX*/ DUP16(MMU.UNUSED_RAM),
- /* DX*/ DUP16(MMU.UNUSED_RAM),
- /* EX*/ DUP16(MMU.UNUSED_RAM),
- /* FX*/ DUP16(MMU.UNUSED_RAM)
- }
-};
-
-u32 MMU_struct::MMU_MASK[2][256] = {
- //arm9
- {
- /* 0X*/ DUP16(0x00007FFF),
- /* 1X*/ //DUP16(0x00007FFF)
- /* 1X*/ DUP16(0x00000003),
- /* 2X*/ DUP16(0x003FFFFF),
- /* 3X*/ DUP16(0x00007FFF),
- /* 4X*/ DUP16(0x00FFFFFF),
- /* 5X*/ DUP16(0x000007FF),
- /* 6X*/ DUP2(0x0007FFFF),
- DUP2(0x0001FFFF),
- DUP2(0x0003FFFF),
- DUP2(0x0001FFFF),
- DUP8(0x000FFFFF),
- /* 7X*/ DUP16(0x000007FF),
- /* 8X*/ DUP16(ROM_MASK),
- /* 9X*/ DUP16(ROM_MASK),
- /* AX*/ DUP16(0x0000FFFF),
- /* BX*/ DUP16(0x00000003),
- /* CX*/ DUP16(0x00000003),
- /* DX*/ DUP16(0x00000003),
- /* EX*/ DUP16(0x00000003),
- /* FX*/ DUP16(0x00007FFF)
- },
- //arm7
- {
- /* 0X*/ DUP16(0x00003FFF),
- /* 1X*/ DUP16(0x00000003),
- /* 2X*/ DUP16(0x003FFFFF),
- /* 3X*/ DUP8(0x00007FFF),
- DUP8(0x0000FFFF),
- /* 4X*/ DUP8(0x00FFFFFF),
- DUP8(0x0000FFFF),
- /* 5X*/ DUP16(0x00000003),
- /* 6X*/ DUP16(0x0003FFFF),
- /* 7X*/ DUP16(0x00000003),
- /* 8X*/ DUP16(ROM_MASK),
- /* 9X*/ DUP16(ROM_MASK),
- /* AX*/ DUP16(0x0000FFFF),
- /* BX*/ DUP16(0x00000003),
- /* CX*/ DUP16(0x00000003),
- /* DX*/ DUP16(0x00000003),
- /* EX*/ DUP16(0x00000003),
- /* FX*/ DUP16(0x00000003)
- }
-};
-
-
-TWaitState MMU_struct::MMU_WAIT16[2][16] = {
- { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm9
- { 1, 1, 1, 1, 1, 1, 1, 1, 5, 5, 5, 1, 1, 1, 1, 1 }, //arm7
-};
-
-TWaitState MMU_struct::MMU_WAIT32[2][16] = {
- { 1, 1, 1, 1, 1, 2, 2, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm9
- { 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 5, 1, 1, 1, 1, 1 }, //arm7
-};
-
-
-// VRAM mapping
-u8 *LCDdst[10] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
-u8 *EngineAddr[4] = { NULL, NULL, NULL, NULL };
-const static u32 LCDdata[10][2]= {
- {0x6800000, 8}, // Bank A
- {0x6820000, 8}, // Bank B
- {0x6840000, 8}, // Bank C
- {0x6860000, 8}, // Bank D
- {0x6880000, 4}, // Bank E
- {0x6890000, 1}, // Bank F
- {0x6894000, 1}, // Bank G
- {0, 0},
- {0x6898000, 2}, // Bank H
- {0x68A0000, 1}}; // Bank I
-
-void MMU_Init(void) {
- int i;
-
- LOG("MMU init\n");
-
- memset(&MMU, 0, sizeof(MMU_struct));
-
- MMU.CART_ROM = MMU.UNUSED_RAM;
-
- for(i = 0x80; i<0xA0; ++i)
- {
- MMU_struct::MMU_MEM[0][i] = MMU.CART_ROM;
- MMU_struct::MMU_MEM[1][i] = MMU.CART_ROM;
- }
-
-
- MMU.DTCMRegion = 0x027C0000;
- MMU.ITCMRegion = 0x00000000;
-
- IPC_FIFOclear();
- GFX_FIFOclear();
-
- mc_init(&MMU.fw, MC_TYPE_FLASH); /* init fw device */
- mc_alloc(&MMU.fw, NDS_FW_SIZE_V1);
- MMU.fw.fp = NULL;
-
- // Init Backup Memory device, this should really be done when the rom is loaded
- mc_init(&MMU.bupmem, MC_TYPE_AUTODETECT);
- mc_alloc(&MMU.bupmem, 1);
- MMU.bupmem.fp = NULL;
- rtcInit();
-}
-
-void MMU_DeInit(void) {
- LOG("MMU deinit\n");
- if (MMU.fw.fp)
- fclose(MMU.fw.fp);
- mc_free(&MMU.fw);
- if (MMU.bupmem.fp)
- fclose(MMU.bupmem.fp);
- mc_free(&MMU.bupmem);
-}
-
-//Card rom & ram
-
-u16 SPI_CNT = 0;
-u16 SPI_CMD = 0;
-u16 AUX_SPI_CNT = 0;
-u16 AUX_SPI_CMD = 0;
-
-u32 rom_mask = 0;
-
-u32 DMASrc[2][4] = {{0, 0, 0, 0}, {0, 0, 0, 0}};
-u32 DMADst[2][4] = {{0, 0, 0, 0}, {0, 0, 0, 0}};
-
-void MMU_clearMem()
-{
- memset(ARM9Mem.ARM9_ABG, 0, 0x080000);
- memset(ARM9Mem.ARM9_AOBJ, 0, 0x040000);
- memset(ARM9Mem.ARM9_BBG, 0, 0x020000);
- memset(ARM9Mem.ARM9_BOBJ, 0, 0x020000);
-
- memset(ARM9Mem.ARM9_DTCM, 0, 0x4000);
- memset(ARM9Mem.ARM9_ITCM, 0, 0x8000);
- memset(ARM9Mem.ARM9_LCD, 0, 0x0A4000);
- memset(ARM9Mem.ARM9_OAM, 0, 0x0800);
- memset(ARM9Mem.ARM9_REG, 0, 0x01000000);
- memset(ARM9Mem.ARM9_VMEM, 0, 0x0800);
- memset(ARM9Mem.MAIN_MEM, 0, 0x400000);
-
- memset(ARM9Mem.blank_memory, 0, 0x020000);
-
- memset(MMU.ARM7_ERAM, 0, 0x010000);
- memset(MMU.ARM7_REG, 0, 0x010000);
-
- IPC_FIFOclear();
- GFX_FIFOclear();
-
- MMU.DTCMRegion = 0x027C0000;
- MMU.ITCMRegion = 0x00000000;
-
- memset(MMU.timer, 0, sizeof(u16) * 2 * 4);
- memset(MMU.timerMODE, 0, sizeof(s32) * 2 * 4);
- memset(MMU.timerON, 0, sizeof(u32) * 2 * 4);
- memset(MMU.timerRUN, 0, sizeof(u32) * 2 * 4);
- memset(MMU.timerReload, 0, sizeof(u16) * 2 * 4);
-
- memset(MMU.reg_IME, 0, sizeof(u32) * 2);
- memset(MMU.reg_IE, 0, sizeof(u32) * 2);
- memset(MMU.reg_IF, 0, sizeof(u32) * 2);
-
- memset(MMU.DMAStartTime, 0, sizeof(u32) * 2 * 4);
- memset(MMU.DMACycle, 0, sizeof(s32) * 2 * 4);
- memset(MMU.DMACrt, 0, sizeof(u32) * 2 * 4);
- memset(MMU.DMAing, 0, sizeof(BOOL) * 2 * 4);
-
- memset(MMU.dscard, 0, sizeof(nds_dscard) * 2);
-
- MainScreen.offset = 0;
- SubScreen.offset = 192;
- osdA->setOffset(MainScreen.offset);
- osdB->setOffset(SubScreen.offset);
-
- /* setup the texture slot pointers */
-#if 0
- ARM9Mem.textureSlotAddr[0] = ARM9Mem.blank_memory;
- ARM9Mem.textureSlotAddr[1] = ARM9Mem.blank_memory;
- ARM9Mem.textureSlotAddr[2] = ARM9Mem.blank_memory;
- ARM9Mem.textureSlotAddr[3] = ARM9Mem.blank_memory;
-#else
- ARM9Mem.textureSlotAddr[0] = &ARM9Mem.ARM9_LCD[0x20000 * 0];
- ARM9Mem.textureSlotAddr[1] = &ARM9Mem.ARM9_LCD[0x20000 * 1];
- ARM9Mem.textureSlotAddr[2] = &ARM9Mem.ARM9_LCD[0x20000 * 2];
- ARM9Mem.textureSlotAddr[3] = &ARM9Mem.ARM9_LCD[0x20000 * 3];
-#endif
-
- LCDdst[0] = ARM9Mem.ARM9_LCD; // Bank A
- LCDdst[1] = ARM9Mem.ARM9_LCD + 0x20000; // Bank B
- LCDdst[2] = ARM9Mem.ARM9_LCD + 0x40000; // Bank C
- LCDdst[3] = ARM9Mem.ARM9_LCD + 0x60000; // Bank D
- LCDdst[4] = ARM9Mem.ARM9_LCD + 0x80000; // Bank E
- LCDdst[5] = ARM9Mem.ARM9_LCD + 0x90000; // Bank F
- LCDdst[6] = ARM9Mem.ARM9_LCD + 0x94000; // Bank G
- LCDdst[7] = NULL;
- LCDdst[8] = ARM9Mem.ARM9_LCD + 0x98000; // Bank H
- LCDdst[9] = ARM9Mem.ARM9_LCD + 0xA0000; // Bank I
-
- EngineAddr[0] = ARM9Mem.ARM9_ABG; // Engine ABG
- EngineAddr[1] = ARM9Mem.ARM9_BBG; // Engine BBG
- EngineAddr[2] = ARM9Mem.ARM9_AOBJ; // Engine BOBJ
- EngineAddr[3] = ARM9Mem.ARM9_BOBJ; // Engine BOBJ
-
- for (int i = 0; i < 4; i++)
- {
- ARM9Mem.ExtPal[0][i] = ARM9Mem.ARM9_LCD;
- ARM9Mem.ExtPal[1][i] = ARM9Mem.ARM9_LCD;
- }
- ARM9Mem.ObjExtPal[0][1] = ARM9Mem.ARM9_LCD;
- ARM9Mem.ObjExtPal[0][2] = ARM9Mem.ARM9_LCD;
- ARM9Mem.ObjExtPal[1][1] = ARM9Mem.ARM9_LCD;
- ARM9Mem.ObjExtPal[1][2] = ARM9Mem.ARM9_LCD;
-
- ARM9Mem.texPalSlot[0] = ARM9Mem.ARM9_LCD;
- ARM9Mem.texPalSlot[1] = ARM9Mem.ARM9_LCD;
- ARM9Mem.texPalSlot[2] = ARM9Mem.ARM9_LCD;
- ARM9Mem.texPalSlot[3] = ARM9Mem.ARM9_LCD;
-
- for (int i =0; i < 9; i++)
- {
- MMU.LCD_VRAM_ADDR[i] = 0;
- for (int t = 0; t < 32; t++)
- MMU.VRAM_MAP[i][t] = 7;
- }
- rtcInit();
- partie = 1;
-}
-
-// VRAM mapping control
-u8 *MMU_RenderMapToLCD(u32 vram_addr)
-{
- if ((vram_addr < 0x6000000)) return NULL;
- if ((vram_addr > 0x661FFFF)) return NULL; // Engine BOBJ max 128KB
-
- // holes
- if ((vram_addr > 0x6080000) && (vram_addr < 0x6200000)) return NULL; // Engine ABG max 512KB
- if ((vram_addr > 0x6220000) && (vram_addr < 0x6400000)) return NULL; // Engine BBG max 128KB
- if ((vram_addr > 0x6420000) && (vram_addr < 0x6600000)) return NULL; // Engine AOBJ max 256KB
-
- vram_addr &= 0x0FFFFFF;
- u8 engine = (vram_addr >> 21);
- vram_addr &= 0x01FFFFF;
- u8 engine_offset = (vram_addr >> 14);
- u8 block = MMU.VRAM_MAP[engine][engine_offset];
- if (block == 7) return (EngineAddr[engine] + vram_addr); // not mapped to LCD
- vram_addr -= MMU.LCD_VRAM_ADDR[block];
- return (LCDdst[block] + vram_addr);
-}
-
-extern void NDS_Pause();
-static FORCEINLINE u32 MMU_LCDmap(u32 addr)
-{
- if ((addr < 0x6000000)) return addr;
- if ((addr > 0x661FFFF)) return addr; // Engine BOBJ max 128KB
-
- // holes
- if ((addr > 0x6080000) && (addr < 0x6200000)) return addr; // Engine ABG max 512KB
- if ((addr > 0x6220000) && (addr < 0x6400000)) return addr; // Engine BBG max 128KB
- if ((addr > 0x6420000) && (addr < 0x6600000)) return addr; // Engine AOBJ max 256KB
-
- u32 save_addr = addr;
-
- addr &= 0x0FFFFFF;
- u8 engine = (addr >> 21);
- addr &= 0x01FFFFF;
- u8 engine_offset = (addr >> 14);
- u8 block = MMU.VRAM_MAP[engine][engine_offset];
- if (block == 7) return (save_addr); // not mapped to LCD
-
- addr -= MMU.LCD_VRAM_ADDR[block];
- return (addr + LCDdata[block][0]);
-}
-#define LOG_VRAM_ERROR() LOG("No data for block %i MST %i\n", block, VRAMBankCnt & 0x07);
-
-static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
-{
- if (!(VRAMBankCnt & 0x80)) return;
- if (!(VRAMBankCnt & 0x07)) return;
-
- for (int i = 0; i < 4; i++)
- {
- for (int t = 0; t < 32; t++)
- if (MMU.VRAM_MAP[i][t] == block)
- MMU.VRAM_MAP[i][t] = 7;
- }
-
- u32 vram_map_addr = 0xFFFFFFFF;
- u8 *LCD_addr = LCDdst[block];
-
- switch (VRAMBankCnt & 0x07)
- {
- case 1:
- switch(block)
- {
- case 0: // A
- case 1: // B
- case 2: // C
- case 3: // D Engine A, BG
- vram_map_addr = ((VRAMBankCnt >> 3) & 3) * 0x20000;
- if(block == 2) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 2);
- if(block == 3) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 1);
- break ;
- case 4: // E Engine A, BG
- vram_map_addr = 0x0000000;
- break;
- case 5: // F
- case 6: // G Engine A, BG
- vram_map_addr = (((VRAMBankCnt>>3)&1)*0x4000)+(((VRAMBankCnt>>4)&1)*0x10000);
- break;
- case 8: // H Engine B, BG
- vram_map_addr = 0x0200000;
- break ;
- case 9: // I Engine B, BG
- vram_map_addr = 0x0208000;
- break;
- default:
- LOG_VRAM_ERROR();
- break;
- }
- break ;
-
- case 2:
- switch(block)
- {
- case 0: // A
- case 1: // B Engine A, OBJ
- vram_map_addr = 0x0400000 + (((VRAMBankCnt>>3)&1)*0x20000);
- break;
- case 2: // C
- T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 1);
- break;
- case 3: // D
- T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) | 2);
- break;
- case 4: // E Engine A, OBJ
- vram_map_addr = 0x0400000;
- break;
- case 5: // F
- case 6: // G Engine A, OBJ
- vram_map_addr = 0x0400000 + (((VRAMBankCnt>>3)&1)*0x4000)+(((VRAMBankCnt>>4)&1)*0x10000);
- break;
- case 8: // H Engine B, BG
- ARM9Mem.ExtPal[1][0] = LCD_addr;
- ARM9Mem.ExtPal[1][1] = LCD_addr+0x2000;
- ARM9Mem.ExtPal[1][2] = LCD_addr+0x4000;
- ARM9Mem.ExtPal[1][3] = LCD_addr+0x6000;
- break;
- case 9: // I Engine B, OBJ
- vram_map_addr = 0x0600000;
- break;
- default:
- LOG_VRAM_ERROR();
- break;
- }
- break ;
-
- case 3:
- switch (block)
- {
- case 0: // A
- case 1: // B
- case 2: // C
- case 3: // D
- // Textures
- {
- int slot_index = (VRAMBankCnt >> 3) & 0x3;
- ARM9Mem.textureSlotAddr[slot_index] = LCD_addr;
- gpu3D->NDS_3D_VramReconfigureSignal();
- if(block == 2) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 2);
- if(block == 3) T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 1);
- }
- break;
- case 4: // E
- ARM9Mem.texPalSlot[0] = LCD_addr;
- ARM9Mem.texPalSlot[1] = LCD_addr+0x2000;
- ARM9Mem.texPalSlot[2] = LCD_addr+0x4000;
- ARM9Mem.texPalSlot[3] = LCD_addr+0x6000;
- break;
- case 5: // F
- case 6: // G
- {
- u8 tmp_slot = ((VRAMBankCnt >> 3) & 0x01) + (((VRAMBankCnt >> 4) & 0x01)*4);
- ARM9Mem.texPalSlot[tmp_slot] = LCD_addr;
- }
- break;
- case 9: // I Engine B, OBJ
- ARM9Mem.ObjExtPal[1][0] = LCD_addr;
- ARM9Mem.ObjExtPal[1][1] = LCD_addr+0x2000;
- break;
- default:
- LOG_VRAM_ERROR();
- break;
- }
- break ;
-
- case 4:
- switch(block)
- {
- case 2: // C Engine B, BG
- vram_map_addr = 0x0200000;
- T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 2);
- break ;
- case 3: // D Engine B, OBJ
- vram_map_addr = 0x0600000;
- T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240, T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x240) & 1);
- break ;
- case 4: // E Engine A, BG
- ARM9Mem.ExtPal[0][0] = LCD_addr;
- ARM9Mem.ExtPal[0][1] = LCD_addr+0x2000;
- ARM9Mem.ExtPal[0][2] = LCD_addr+0x4000;
- ARM9Mem.ExtPal[0][3] = LCD_addr+0x6000;
- break;
- case 5: // F
- case 6: // G Engine A, BG
- {
- u8 tmp_slot = (VRAMBankCnt >> 2) & 0x02;
- ARM9Mem.ExtPal[0][tmp_slot] = LCD_addr;
- ARM9Mem.ExtPal[0][tmp_slot+1] = LCD_addr+0x2000;
- }
- break;
- default:
- LOG_VRAM_ERROR();
- break;
- }
- break;
-
- case 5:
- if ((block == 5) || (block == 6)) // F, G Engine A, OBJ
- {
- ARM9Mem.ObjExtPal[0][0] = LCD_addr;
- ARM9Mem.ObjExtPal[0][1] = LCD_addr + 0x2000;
- }
- break;
- }
-
- if (vram_map_addr != 0xFFFFFFFF)
- {
- //u32 vr = vram_map_addr;
- u8 engine = (vram_map_addr >> 21);
- vram_map_addr &= 0x001FFFFF;
- u8 engine_offset = (vram_map_addr >> 14);
- MMU.LCD_VRAM_ADDR[block] = vram_map_addr;
- MMU.LCDCenable[block] = TRUE;
-
- for (unsigned int i = 0; i < LCDdata[block][1]; i++)
- MMU.VRAM_MAP[engine][engine_offset + i] = (u8)block;
-
- //INFO("VRAM %i mapping: eng=%i (offs=%i, size=%i), addr = 0x%X, MST=%i (faddr 0x%X)\n",
- // block, engine, engine_offset, LCDdata[block][1]*0x4000, MMU.LCD_VRAM_ADDR[block], VRAMBankCnt & 0x07,
- // vr + 0x6000000);
- return;
- }
-
- MMU.LCDCenable[block] = FALSE;
-}
-
-void MMU_setRom(u8 * rom, u32 mask)
-{
- unsigned int i;
- MMU.CART_ROM = rom;
-
- for(i = 0x80; i<0xA0; ++i)
- {
- MMU_struct::MMU_MEM[0][i] = rom;
- MMU_struct::MMU_MEM[1][i] = rom;
- MMU_struct::MMU_MASK[0][i] = mask;
- MMU_struct::MMU_MASK[1][i] = mask;
- }
- rom_mask = mask;
-}
-
-void MMU_unsetRom()
-{
- unsigned int i;
- MMU.CART_ROM=MMU.UNUSED_RAM;
-
- for(i = 0x80; i<0xA0; ++i)
- {
- MMU_struct::MMU_MEM[0][i] = MMU.UNUSED_RAM;
- MMU_struct::MMU_MEM[1][i] = MMU.UNUSED_RAM;
- MMU_struct::MMU_MASK[0][i] = ROM_MASK;
- MMU_struct::MMU_MASK[1][i] = ROM_MASK;
- }
- rom_mask = ROM_MASK;
-}
-char txt[80];
-
-void execsqrt() {
- u32 ret;
- u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0);
- switch(cnt&1)
- {
- case 0: {
- u32 v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
- ret = isqrt(v);
- break;
- }
- case 1: {
- u64 v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
- ret = isqrt(v);
- break;
- }
- }
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B4, 0);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0, cnt | 0x8000);
-
- MMU.sqrtCycles = (nds.cycles + 26);
- MMU.sqrtResult = ret;
- MMU.sqrtCnt = (cnt & 0x7FFF);
- MMU.sqrtRunning = TRUE;
-}
-
-void execdiv() {
- u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280);
- s64 num,den;
- s64 res,mod;
- switch(cnt&3)
- {
- case 0:
- num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
- den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
- MMU.divCycles = (nds.cycles + 36);
- break;
- case 3: //gbatek says this is same as mode 1
- case 1:
- num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
- den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
- MMU.divCycles = (nds.cycles + 68);
- break;
- case 2:
- num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
- den = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
- MMU.divCycles = (nds.cycles + 68);
- break;
- }
-
- if(den==0)
- {
- res = ((num < 0) ? 1 : -1);
- mod = num;
- cnt |= 0x4000;
- cnt &= 0x7FFF;
- }
- else
- {
- res = num / den;
- mod = num % den;
- cnt &= 0x3FFF;
- }
-
- DIVLOG("DIV %08X%08X / %08X%08X = %08X%08X\r\n", (u32)(num>>32), (u32)num,
- (u32)(den>>32), (u32)den,
- (u32)(res>>32), (u32)res);
-
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, 0);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, 0);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, 0);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2AC, 0);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280, ((cnt & 0xBFFF) | 0x8000));
-
- MMU.divResult = res;
- MMU.divMod = mod;
- MMU.divCnt = (cnt & 0x7FFF);
- MMU.divRunning = TRUE;
-}
-
-void FASTCALL MMU_doDMA(u32 proc, u32 num)
-{
- u32 src = DMASrc[proc][num];
- u32 dst = DMADst[proc][num];
- u32 taille;
-
- if(src==dst)
- {
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0xB8 + (0xC*num), T1ReadLong(MMU.MMU_MEM[proc][0x40], 0xB8 + (0xC*num)) & 0x7FFFFFFF);
- return;
- }
-
- if((!(MMU.DMACrt[proc][num]&(1<<31)))&&(!(MMU.DMACrt[proc][num]&(1<<25))))
- { /* not enabled and not to be repeated */
- MMU.DMAStartTime[proc][num] = 0;
- MMU.DMACycle[proc][num] = 0;
- //MMU.DMAing[proc][num] = FALSE;
- return;
- }
-
-
- /* word count */
- taille = (MMU.DMACrt[proc][num]&0xFFFF);
-
- // If we are in "Main memory display" mode just copy an entire
- // screen (256x192 pixels).
- // Reference: http://nocash.emubase.de/gbatek.htm#dsvideocaptureandmainmemorydisplaymode
- // (under DISP_MMEM_FIFO)
- if ((MMU.DMAStartTime[proc][num]==4) && // Must be in main memory display mode
- (taille==4) && // Word must be 4
- (((MMU.DMACrt[proc][num]>>26)&1) == 1)) // Transfer mode must be 32bit wide
- taille = 24576; //256*192/2;
-
- if(MMU.DMAStartTime[proc][num] == 5)
- taille *= 0x80;
-
- MMU.DMACycle[proc][num] = taille + nds.cycles;
- MMU.DMAing[proc][num] = TRUE;
- MMU.CheckDMAs |= (1<<(num+(proc<<2)));
-
- DMALOG("proc %d, dma %d src %08X dst %08X start %d taille %d repeat %s %08X\r\n",
- proc, num, src, dst, MMU.DMAStartTime[proc][num], taille,
- (MMU.DMACrt[proc][num]&(1<<25))?"on":"off",MMU.DMACrt[proc][num]);
-
- if(!(MMU.DMACrt[proc][num]&(1<<25)))
- MMU.DMAStartTime[proc][num] = 0;
-
- // transfer
- {
- u32 i=0;
- // 32 bit or 16 bit transfer ?
- int sz = ((MMU.DMACrt[proc][num]>>26)&1)? 4 : 2;
- int dstinc,srcinc;
- int u=(MMU.DMACrt[proc][num]>>21);
- switch(u & 0x3) {
- case 0 : dstinc = sz; break;
- case 1 : dstinc = -sz; break;
- case 2 : dstinc = 0; break;
- case 3 : dstinc = sz; break; //reload
- default:
- return;
- }
- switch((u >> 2)&0x3) {
- case 0 : srcinc = sz; break;
- case 1 : srcinc = -sz; break;
- case 2 : srcinc = 0; break;
- case 3 : // reserved
- return;
- default:
- return;
- }
- if ((MMU.DMACrt[proc][num]>>26)&1)
- for(; i < taille; ++i)
- {
- MMU_write32(proc, dst, MMU_read32(proc, src));
- dst += dstinc;
- src += srcinc;
- }
- else
- for(; i < taille; ++i)
- {
- MMU_write16(proc, dst, MMU_read16(proc, src));
- dst += dstinc;
- src += srcinc;
- }
-
- //write back the addresses
- DMASrc[proc][num] = src;
- if((u & 0x3)!=3) //but dont write back dst if we were supposed to reload
- DMADst[proc][num] = dst;
- }
-}
-
-#ifdef MMU_ENABLE_ACL
-
-INLINE void check_access(u32 adr, u32 access) {
- /* every other mode: sys */
- access |= 1;
- if ((NDS_ARM9.CPSR.val & 0x1F) == 0x10) {
- /* is user mode access */
- access ^= 1 ;
- }
- if (armcp15_isAccessAllowed((armcp15_t *)NDS_ARM9.coproc[15],adr,access)==FALSE) {
- execute = FALSE ;
- }
-}
-INLINE void check_access_write(u32 adr) {
- u32 access = CP15_ACCESS_WRITE;
- check_access(adr, access)
-}
-
-u8 FASTCALL MMU_read8_acl(u32 proc, u32 adr, u32 access)
-{
- /* on arm9 we need to check the MPU regions */
- if (proc == ARMCPU_ARM9)
- check_access(u32 adr, u32 access);
- return MMU_read8(proc,adr);
-}
-u16 FASTCALL MMU_read16_acl(u32 proc, u32 adr, u32 access)
-{
- /* on arm9 we need to check the MPU regions */
- if (proc == ARMCPU_ARM9)
- check_access(u32 adr, u32 access);
- return MMU_read16(proc,adr);
-}
-u32 FASTCALL MMU_read32_acl(u32 proc, u32 adr, u32 access)
-{
- /* on arm9 we need to check the MPU regions */
- if (proc == ARMCPU_ARM9)
- check_access(u32 adr, u32 access);
- return MMU_read32(proc,adr);
-}
-
-void FASTCALL MMU_write8_acl(u32 proc, u32 adr, u8 val)
-{
- /* check MPU region on ARM9 */
- if (proc == ARMCPU_ARM9)
- check_access_write(adr);
- MMU_write8(proc,adr,val);
-}
-void FASTCALL MMU_write16_acl(u32 proc, u32 adr, u16 val)
-{
- /* check MPU region on ARM9 */
- if (proc == ARMCPU_ARM9)
- check_access_write(adr);
- MMU_write16(proc,adr,val) ;
-}
-void FASTCALL MMU_write32_acl(u32 proc, u32 adr, u32 val)
-{
- /* check MPU region on ARM9 */
- if (proc == ARMCPU_ARM9)
- check_access_write(adr);
- MMU_write32(proc,adr,val) ;
-}
-#endif
-
-#ifdef PROFILE_MEMORY_ACCESS
-
-#define PROFILE_PREFETCH 0
-#define PROFILE_READ 1
-#define PROFILE_WRITE 2
-
-struct mem_access_profile {
- u64 num_accesses;
- u32 address_mask;
- u32 masked_value;
-};
-
-#define PROFILE_NUM_MEM_ACCESS_PROFILES 4
-
-static u64 profile_num_accesses[2][3];
-static u64 profile_unknown_addresses[2][3];
-static struct mem_access_profile
-profile_memory_accesses[2][3][PROFILE_NUM_MEM_ACCESS_PROFILES];
-
-static void
-setup_profiling( void) {
- int i;
-
- for ( i = 0; i < 2; i++) {
- int access_type;
-
- for ( access_type = 0; access_type < 3; access_type++) {
- profile_num_accesses[i][access_type] = 0;
- profile_unknown_addresses[i][access_type] = 0;
-
- /*
- * Setup the access testing structures
- */
- profile_memory_accesses[i][access_type][0].address_mask = 0x0e000000;
- profile_memory_accesses[i][access_type][0].masked_value = 0x00000000;
- profile_memory_accesses[i][access_type][0].num_accesses = 0;
-
- /* main memory */
- profile_memory_accesses[i][access_type][1].address_mask = 0x0f000000;
- profile_memory_accesses[i][access_type][1].masked_value = 0x02000000;
- profile_memory_accesses[i][access_type][1].num_accesses = 0;
-
- /* shared memory */
- profile_memory_accesses[i][access_type][2].address_mask = 0x0f800000;
- profile_memory_accesses[i][access_type][2].masked_value = 0x03000000;
- profile_memory_accesses[i][access_type][2].num_accesses = 0;
-
- /* arm7 memory */
- profile_memory_accesses[i][access_type][3].address_mask = 0x0f800000;
- profile_memory_accesses[i][access_type][3].masked_value = 0x03800000;
- profile_memory_accesses[i][access_type][3].num_accesses = 0;
- }
- }
-}
-
-static void
-profile_memory_access( int arm9, u32 adr, int access_type) {
- static int first = 1;
- int mem_profile;
- int address_found = 0;
-
- if ( first) {
- setup_profiling();
- first = 0;
- }
-
- profile_num_accesses[arm9][access_type] += 1;
-
- for ( mem_profile = 0;
- mem_profile < PROFILE_NUM_MEM_ACCESS_PROFILES &&
- !address_found;
- mem_profile++) {
- if ( (adr & profile_memory_accesses[arm9][access_type][mem_profile].address_mask) ==
- profile_memory_accesses[arm9][access_type][mem_profile].masked_value) {
- /*printf( "adr %08x mask %08x res %08x expected %08x\n",
- adr,
- profile_memory_accesses[arm9][access_type][mem_profile].address_mask,
- adr & profile_memory_accesses[arm9][access_type][mem_profile].address_mask,
- profile_memory_accesses[arm9][access_type][mem_profile].masked_value);*/
- address_found = 1;
- profile_memory_accesses[arm9][access_type][mem_profile].num_accesses += 1;
- }
- }
-
- if ( !address_found) {
- profile_unknown_addresses[arm9][access_type] += 1;
- }
-}
-
-
-static const char *access_type_strings[] = {
- "prefetch",
- "read ",
- "write "
-};
-
-void
-print_memory_profiling( void) {
- int arm;
-
- printf("------ Memory access profile ------\n");
-
- for ( arm = 0; arm < 2; arm++) {
- int access_type;
-
- for ( access_type = 0; access_type < 3; access_type++) {
- int mem_profile;
- printf("ARM%c: num of %s %lld\n",
- arm ? '9' : '7',
- access_type_strings[access_type],
- profile_num_accesses[arm][access_type]);
-
- for ( mem_profile = 0;
- mem_profile < PROFILE_NUM_MEM_ACCESS_PROFILES;
- mem_profile++) {
- printf( "address %08x: %lld\n",
- profile_memory_accesses[arm][access_type][mem_profile].masked_value,
- profile_memory_accesses[arm][access_type][mem_profile].num_accesses);
- }
-
- printf( "unknown addresses %lld\n",
- profile_unknown_addresses[arm][access_type]);
-
- printf( "\n");
- }
- }
-
- printf("------ End of Memory access profile ------\n\n");
-}
-#else
-void
-print_memory_profiling( void) {
-}
-#endif /* End of PROFILE_MEMORY_ACCESS area */
-
-static u16 FASTCALL
-arm9_prefetch16( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 1, adr, PROFILE_PREFETCH);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- if((adr & ~0x3FFF) == MMU.DTCMRegion)
- {
- /* Returns data from DTCM (ARM9 only) */
- return T1ReadWord(ARM9Mem.ARM9_DTCM, adr & 0x3FFF);
- }
- /* access to main memory */
- if ( (adr & 0x0f000000) == 0x02000000) {
- return T1ReadWord( MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20) & 0xFF],
- adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]);
- }
-#endif
-
- return MMU_read16( ARMCPU_ARM9, adr);
-}
-static u32 FASTCALL
-arm9_prefetch32( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 1, adr, PROFILE_PREFETCH);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- if((adr & ~0x3FFF) == MMU.DTCMRegion)
- {
- /* Returns data from DTCM (ARM9 only) */
- return T1ReadLong(ARM9Mem.ARM9_DTCM, adr & 0x3FFF);
- }
- /* access to main memory */
- if ( (adr & 0x0f000000) == 0x02000000) {
- return T1ReadLong( MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20) & 0xFF],
- adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]);
- }
-#endif
-
- return MMU_read32( ARMCPU_ARM9, adr);
-}
-
-static u8 FASTCALL
-arm9_read8( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 1, adr, PROFILE_READ);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- if( (adr&(~0x3FFF)) == MMU.DTCMRegion)
- {
- return ARM9Mem.ARM9_DTCM[adr&0x3FFF];
- }
- /* access to main memory */
- if ( (adr & 0x0f000000) == 0x02000000) {
- return MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20) & 0xFF]
- [adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]];
- }
-#endif
-
- return MMU_read8( ARMCPU_ARM9, adr);
-}
-static u16 FASTCALL
-arm9_read16( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 1, adr, PROFILE_READ);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- if((adr & ~0x3FFF) == MMU.DTCMRegion)
- {
- /* Returns data from DTCM (ARM9 only) */
- return T1ReadWord(ARM9Mem.ARM9_DTCM, adr & 0x3FFF);
- }
-
- /* access to main memory */
- if ( (adr & 0x0f000000) == 0x02000000) {
- return T1ReadWord( MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20) & 0xFF],
- adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]);
- }
-#endif
-
- return MMU_read16( ARMCPU_ARM9, adr);
-}
-static u32 FASTCALL
-arm9_read32( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 1, adr, PROFILE_READ);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- if((adr & ~0x3FFF) == MMU.DTCMRegion)
- {
- /* Returns data from DTCM (ARM9 only) */
- return T1ReadLong(ARM9Mem.ARM9_DTCM, adr & 0x3FFF);
- }
- /* access to main memory */
- if ( (adr & 0x0f000000) == 0x02000000) {
- return T1ReadLong( MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20) & 0xFF],
- adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]);
- }
-#endif
-
- return MMU_read32( ARMCPU_ARM9, adr);
-}
-
-
-static void FASTCALL
-arm9_write8(void *data, u32 adr, u8 val) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 1, adr, PROFILE_WRITE);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- if( (adr & ~0x3FFF) == MMU.DTCMRegion)
- {
- /* Writes data in DTCM (ARM9 only) */
- ARM9Mem.ARM9_DTCM[adr&0x3FFF] = val;
- return ;
- }
- /* main memory */
- if ( (adr & 0x0f000000) == 0x02000000) {
- MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF]
- [adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF]] = val;
- return;
- }
-#endif
-
- MMU_write8( ARMCPU_ARM9, adr, val);
-}
-static void FASTCALL
-arm9_write16(void *data, u32 adr, u16 val) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 1, adr, PROFILE_WRITE);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- if((adr & ~0x3FFF) == MMU.DTCMRegion)
- {
- /* Writes in DTCM (ARM9 only) */
- T1WriteWord(ARM9Mem.ARM9_DTCM, adr & 0x3FFF, val);
- return;
- }
- /* main memory */
- if ( (adr & 0x0f000000) == 0x02000000) {
- T1WriteWord( MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF],
- adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF], val);
- return;
- }
-#endif
-
- MMU_write16( ARMCPU_ARM9, adr, val);
-}
-static void FASTCALL
-arm9_write32(void *data, u32 adr, u32 val) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 1, adr, PROFILE_WRITE);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- if((adr & ~0x3FFF) == MMU.DTCMRegion)
- {
- /* Writes in DTCM (ARM9 only) */
- T1WriteLong(ARM9Mem.ARM9_DTCM, adr & 0x3FFF, val);
- return;
- }
- /* main memory */
- if ( (adr & 0x0f000000) == 0x02000000) {
- T1WriteLong( MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF],
- adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF], val);
- return;
- }
-#endif
-
- MMU_write32( ARMCPU_ARM9, adr, val);
-}
-
-
-
-
-static u16 FASTCALL
-arm7_prefetch16( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 0, adr, PROFILE_PREFETCH);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- /* ARM7 private memory */
- if ( (adr & 0x0f800000) == 0x03800000) {
- T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF],
- adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]);
- }
-#endif
-
- return MMU_read16( ARMCPU_ARM7, adr);
-}
-static u32 FASTCALL
-arm7_prefetch32( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 0, adr, PROFILE_PREFETCH);
-#endif
-
-#ifdef EARLY_MEMORY_ACCESS
- /* ARM7 private memory */
- if ( (adr & 0x0f800000) == 0x03800000) {
- T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF],
- adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]);
- }
-#endif
-
- return MMU_read32( ARMCPU_ARM7, adr);
-}
-
-static u8 FASTCALL
-arm7_read8( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 0, adr, PROFILE_READ);
-#endif
-
- return MMU_read8( ARMCPU_ARM7, adr);
-}
-static u16 FASTCALL
-arm7_read16( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 0, adr, PROFILE_READ);
-#endif
-
- return MMU_read16( ARMCPU_ARM7, adr);
-}
-static u32 FASTCALL
-arm7_read32( void *data, u32 adr) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 0, adr, PROFILE_READ);
-#endif
-
- return MMU_read32( ARMCPU_ARM7, adr);
-}
-
-static void FASTCALL
-arm7_write8(void *data, u32 adr, u8 val) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 0, adr, PROFILE_WRITE);
-#endif
-
- MMU_write8( ARMCPU_ARM7, adr, val);
-}
-static void FASTCALL
-arm7_write16(void *data, u32 adr, u16 val) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 0, adr, PROFILE_WRITE);
-#endif
-
- MMU_write16( ARMCPU_ARM7, adr, val);
-}
-static void FASTCALL
-arm7_write32(void *data, u32 adr, u32 val) {
-#ifdef PROFILE_MEMORY_ACCESS
- profile_memory_access( 0, adr, PROFILE_WRITE);
-#endif
-
- MMU_write32( ARMCPU_ARM7, adr, val);
-}
-
-
-
-/*
- * the base memory interfaces
- */
-struct armcpu_memory_iface arm9_base_memory_iface = {
- arm9_prefetch32,
- arm9_prefetch16,
-
- arm9_read8,
- arm9_read16,
- arm9_read32,
-
- arm9_write8,
- arm9_write16,
- arm9_write32
-};
-
-struct armcpu_memory_iface arm7_base_memory_iface = {
- arm7_prefetch32,
- arm7_prefetch16,
-
- arm7_read8,
- arm7_read16,
- arm7_read32,
-
- arm7_write8,
- arm7_write16,
- arm7_write32
-};
-
-/*
- * The direct memory interface for the ARM9.
- * This avoids the ARM9 protection unit when accessing
- * memory.
- */
-struct armcpu_memory_iface arm9_direct_memory_iface = {
- NULL,
- NULL,
-
- arm9_read8,
- arm9_read16,
- arm9_read32,
-
- arm9_write8,
- arm9_write16,
- arm9_write32
-};
-
-//================================================================================================== ARM9 *
-//=========================================================================================================
-//=========================================================================================================
-//================================================= MMU write 08
-static void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
-{
-#ifdef INTERNAL_DTCM_WRITE
- if(((adr & ~0x3FFF) == MMU.DTCMRegion))
- {
- /* Writes data in DTCM (ARM9 only) */
- ARM9Mem.ARM9_DTCM[adr & 0x3FFF] = val;
- return ;
- }
-#endif
- if(adr < 0x02000000)
- {
- T1WriteByte(ARM9Mem.ARM9_ITCM, adr&0x7FFF, val);
- return ;
- }
- // ???
-#if 0
- // CFlash writing, Mic
- if ((adr>=0x9000000)&&(adr<0x9900000)) {
- cflash_write(adr,val);
- return;
- }
-#endif
-
- adr &= 0x0FFFFFFF;
-
- if (adr >> 24 == 4)
- {
- switch(adr)
- {
- case REG_DISPA_WIN0H:
- GPU_setWIN0_H1(MainScreen.gpu, val);
- break ;
- case REG_DISPA_WIN0H+1:
- GPU_setWIN0_H0 (MainScreen.gpu, val);
- break ;
- case REG_DISPA_WIN1H:
- GPU_setWIN1_H1 (MainScreen.gpu,val);
- break ;
- case REG_DISPA_WIN1H+1:
- GPU_setWIN1_H0 (MainScreen.gpu,val);
- break ;
-
- case REG_DISPB_WIN0H:
- GPU_setWIN0_H1(SubScreen.gpu,val);
- break ;
- case REG_DISPB_WIN0H+1:
- GPU_setWIN0_H0(SubScreen.gpu,val);
- break ;
- case REG_DISPB_WIN1H:
- GPU_setWIN1_H1(SubScreen.gpu,val);
- break ;
- case REG_DISPB_WIN1H+1:
- GPU_setWIN1_H0(SubScreen.gpu,val);
- break ;
-
- case REG_DISPA_WIN0V:
- GPU_setWIN0_V1(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN0V+1:
- GPU_setWIN0_V0(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN1V:
- GPU_setWIN1_V1(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN1V+1:
- GPU_setWIN1_V0(MainScreen.gpu,val) ;
- break ;
-
- case REG_DISPB_WIN0V:
- GPU_setWIN0_V1(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN0V+1:
- GPU_setWIN0_V0(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN1V:
- GPU_setWIN1_V1(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN1V+1:
- GPU_setWIN1_V0(SubScreen.gpu,val) ;
- break ;
-
- case REG_DISPA_WININ:
- GPU_setWININ0(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WININ+1:
- GPU_setWININ1(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WINOUT:
- GPU_setWINOUT(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WINOUT+1:
- GPU_setWINOBJ(MainScreen.gpu,val);
- break ;
-
- case REG_DISPB_WININ:
- GPU_setWININ0(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WININ+1:
- GPU_setWININ1(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WINOUT:
- GPU_setWINOUT(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WINOUT+1:
- GPU_setWINOBJ(SubScreen.gpu,val) ;
- break ;
-
- case REG_DISPA_BLDCNT:
- GPU_setBLDCNT_HIGH(MainScreen.gpu,val);
- break;
- case REG_DISPA_BLDCNT+1:
- GPU_setBLDCNT_LOW (MainScreen.gpu,val);
- break;
-
- case REG_DISPB_BLDCNT:
- GPU_setBLDCNT_HIGH (SubScreen.gpu,val);
- break;
- case REG_DISPB_BLDCNT+1:
- GPU_setBLDCNT_LOW (SubScreen.gpu,val);
- break;
-
- case REG_DISPA_BLDALPHA:
- GPU_setBLDALPHA_EVB(MainScreen.gpu,val) ;
- break;
- case REG_DISPA_BLDALPHA+1:
- GPU_setBLDALPHA_EVA(MainScreen.gpu,val) ;
- break;
-
- case REG_DISPB_BLDALPHA:
- GPU_setBLDALPHA_EVB(SubScreen.gpu,val) ;
- break;
- case REG_DISPB_BLDALPHA+1:
- GPU_setBLDALPHA_EVA(SubScreen.gpu,val);
- break;
-
- case REG_DISPA_BLDY:
- GPU_setBLDY_EVY(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_BLDY:
- GPU_setBLDY_EVY(SubScreen.gpu,val) ;
- break;
-
- case 0x4000247:
- /* Update WRAMSTAT at the ARM7 side */
- T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, val);
- break;
-
- case REG_VRAMCNTA:
- case REG_VRAMCNTB:
- case REG_VRAMCNTC:
- case REG_VRAMCNTD:
- case REG_VRAMCNTE:
- case REG_VRAMCNTF:
- case REG_VRAMCNTG:
- case REG_VRAMCNTH:
- case REG_VRAMCNTI:
- MMU_VRAMmapControl(adr-REG_VRAMCNTA, val);
- break;
- #ifdef LOG_CARD
- case 0x040001A0 : /* TODO (clear): ??? */
- case 0x040001A1 :
- case 0x040001A2 :
- case 0x040001A8 :
- case 0x040001A9 :
- case 0x040001AA :
- case 0x040001AB :
- case 0x040001AC :
- case 0x040001AD :
- case 0x040001AE :
- case 0x040001AF :
- LOG("%08X : %02X\r\n", adr, val);
- #endif
- }
-#ifdef _MMU_DEBUG
- mmu_log_debug_ARM9(adr, "(write08) %0x%X", val);
-#endif
- MMU.MMU_MEM[ARMCPU_ARM9][0x40][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val;
- return;
- }
-
- adr = MMU_LCDmap(adr);
-
- // Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
- MMU.MMU_MEM[ARMCPU_ARM9][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val;
-}
-
-static INLINE void MMU_IPCSync(u8 proc, u32 val)
-{
- //INFO("IPC%s sync 0x%08X\n", proc?"7":"9", val);
- u32 IPCSYNC_local = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x180) & 0xFFFF;
- u32 IPCSYNC_remote = T1ReadLong(MMU.MMU_MEM[proc^1][0x40], 0x180);
-
- IPCSYNC_local = (IPCSYNC_local&0x6000)|(val&0xf00)|(IPCSYNC_local&0xf);
- IPCSYNC_remote =(IPCSYNC_remote&0x6f00)|(val>>8)&0xf;
-
- T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x180, IPCSYNC_local);
- T1WriteLong(MMU.MMU_MEM[proc^1][0x40], 0x180, IPCSYNC_remote);
-
- if ((val & 0x2000) && (IPCSYNC_remote & 0x4000))
- NDS_makeInt(proc^1, 17);
-}
-
-//================================================= MMU ARM9 write 16
-static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
-{
-#ifdef INTERNAL_DTCM_WRITE
- if((adr & ~0x3FFF) == MMU.DTCMRegion)
- {
- /* Writes in DTCM (ARM9 only) */
- T1WriteWord(ARM9Mem.ARM9_DTCM, adr & 0x3FFF, val);
- return;
- }
-#endif
- if (adr < 0x02000000)
- {
- T1WriteWord(ARM9Mem.ARM9_ITCM, adr&0x7FFF, val);
- return ;
- }
-
- // ???
-#if 0
- // CFlash writing, Mic
- if ((adr>=0x08800000)&&(adr<0x09900000))
- {
- cflash_write(adr,val);
- return;
- }
-#endif
-
- adr &= 0x0FFFFFFF;
-
- if((adr >> 24) == 4)
- {
- if(adr >= 0x04000380 && adr <= 0x040003BE)
- {
- //toon table
- ((u16 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(adr-0x04000000)>>1] = val;
- gfx3d_UpdateToonTable(&((MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[(0x380)]);
- return;
- }
- /* Address is an IO register */
-
- switch(adr)
- {
- case 0x0400035C:
- {
- ((u16 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x35C>>1] = val;
- gfx3d_glFogOffset (val);
- return;
- }
- case 0x04000340:
- {
- ((u16 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x340>>1] = val;
- gfx3d_glAlphaFunc(val);
- return;
- }
- case 0x04000060:
- {
- ((u16 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x060>>1] = val;
- gfx3d_Control(val);
- return;
- }
- case 0x04000354:
- {
- ((u16 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x354>>1] = val;
- gfx3d_glClearDepth(val);
- return;
- }
-
- case REG_DISPA_BLDCNT:
- GPU_setBLDCNT(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_BLDCNT:
- GPU_setBLDCNT(SubScreen.gpu,val) ;
- break ;
- case REG_DISPA_BLDALPHA:
- GPU_setBLDALPHA(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_BLDALPHA:
- GPU_setBLDALPHA(SubScreen.gpu,val) ;
- break ;
- case REG_DISPA_BLDY:
- GPU_setBLDY_EVY(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_BLDY:
- GPU_setBLDY_EVY(SubScreen.gpu,val) ;
- break;
- case REG_DISPA_MASTERBRIGHT:
- GPU_setMasterBrightness (MainScreen.gpu, val);
- break;
- /*
- case REG_DISPA_MOSAIC:
- GPU_setMOSAIC(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_MOSAIC:
- GPU_setMOSAIC(SubScreen.gpu,val) ;
- break ;
- */
- case REG_DISPA_BG0HOFS:
- GPU_setBGxHOFS(0, MainScreen.gpu, val);
- break;
- case REG_DISPA_BG0VOFS:
- GPU_setBGxVOFS(0, MainScreen.gpu, val);
- break;
- case REG_DISPA_BG1HOFS:
- GPU_setBGxHOFS(1, MainScreen.gpu, val);
- break;
- case REG_DISPA_BG1VOFS:
- GPU_setBGxVOFS(1, MainScreen.gpu, val);
- break;
- case REG_DISPA_BG2HOFS:
- GPU_setBGxHOFS(2, MainScreen.gpu, val);
- break;
- case REG_DISPA_BG2VOFS:
- GPU_setBGxVOFS(2, MainScreen.gpu, val);
- break;
- case REG_DISPA_BG3HOFS:
- GPU_setBGxHOFS(3, MainScreen.gpu, val);
- break;
- case REG_DISPA_BG3VOFS:
- GPU_setBGxVOFS(3, MainScreen.gpu, val);
- break;
-
- case REG_DISPA_WIN0H:
- GPU_setWIN0_H (MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN1H:
- GPU_setWIN1_H(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN0H:
- GPU_setWIN0_H(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN1H:
- GPU_setWIN1_H(SubScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN0V:
- GPU_setWIN0_V(MainScreen.gpu,val) ;
- break ;
- case REG_DISPA_WIN1V:
- GPU_setWIN1_V(MainScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN0V:
- GPU_setWIN0_V(SubScreen.gpu,val) ;
- break ;
- case REG_DISPB_WIN1V:
- GPU_setWIN1_V(SubScreen.gpu,val) ;
- break ;
- case REG_DISPA_WININ:
- GPU_setWININ(MainScreen.gpu, val) ;
- break ;
- case REG_DISPA_WINOUT:
- GPU_setWINOUT16(MainScreen.gpu, val) ;
- break ;
-
- case REG_DISPB_BG0HOFS:
- GPU_setBGxHOFS(0, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG0VOFS:
- GPU_setBGxVOFS(0, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG1HOFS:
- GPU_setBGxHOFS(1, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG1VOFS:
- GPU_setBGxVOFS(1, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG2HOFS:
- GPU_setBGxHOFS(2, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG2VOFS:
- GPU_setBGxVOFS(2, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG3HOFS:
- GPU_setBGxHOFS(3, SubScreen.gpu, val);
- break;
- case REG_DISPB_BG3VOFS:
- GPU_setBGxVOFS(3, SubScreen.gpu, val);
- break;
- case REG_DISPB_WININ:
- GPU_setWININ(SubScreen.gpu, val) ;
- break ;
- case REG_DISPB_WINOUT:
- GPU_setWINOUT16(SubScreen.gpu, val) ;
- break ;
-
- case REG_DISPB_MASTERBRIGHT:
- GPU_setMasterBrightness (SubScreen.gpu, val);
- break;
-
- case REG_POWCNT1 :
- {
-// TODO: make this later
-#if 0
- u8 _LCD = (val) & 0x01;
- u8 _2DEngineA = (val>>1) & 0x01;
- u8 _2DEngineB = (val>>9) & 0x01;
- u8 _3DRender = (val>>2) & 0x01;
- u8 _3DGeometry = (val>>3) & 0x01;
-#endif
- if(val & (1<<15))
- {
- LOG("Main core on top\n");
- MainScreen.offset = 0;
- SubScreen.offset = 192;
- }
- else
- {
- LOG("Main core on bottom (%04X)\n", val);
- MainScreen.offset = 192;
- SubScreen.offset = 0;
- }
- osdA->setOffset(MainScreen.offset);
- osdB->setOffset(SubScreen.offset);
-
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x304, val);
- }
-
- return;
-
- case REG_EXMEMCNT:
- {
- u16 oldval = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x204, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x204, (val & 0xFF80) | (oldval & 0x7F));
- }
- return;
-
- case REG_AUXSPICNT:
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][(REG_AUXSPICNT >> 20) & 0xff], REG_AUXSPICNT & 0xfff, val);
- AUX_SPI_CNT = val;
-
- if (val == 0)
- mc_reset_com(&MMU.bupmem); /* reset backup memory device communication */
- return;
-
- case REG_AUXSPIDATA:
- if(val!=0)
- AUX_SPI_CMD = val & 0xFF;
-
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, bm_transfer(&MMU.bupmem, val));
- return;
- case REG_DISPA_BG0CNT :
- //GPULOG("MAIN BG0 SETPROP 16B %08X\r\n", val);
- GPU_setBGProp(MainScreen.gpu, 0, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x8, val);
- return;
- case REG_DISPA_BG1CNT :
- //GPULOG("MAIN BG1 SETPROP 16B %08X\r\n", val);
- GPU_setBGProp(MainScreen.gpu, 1, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xA, val);
- return;
- case REG_DISPA_BG2CNT :
- //GPULOG("MAIN BG2 SETPROP 16B %08X\r\n", val);
- GPU_setBGProp(MainScreen.gpu, 2, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC, val);
- return;
- case REG_DISPA_BG3CNT :
- //GPULOG("MAIN BG3 SETPROP 16B %08X\r\n", val);
- GPU_setBGProp(MainScreen.gpu, 3, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xE, val);
- return;
- case REG_DISPB_BG0CNT :
- //GPULOG("SUB BG0 SETPROP 16B %08X\r\n", val);
- GPU_setBGProp(SubScreen.gpu, 0, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1008, val);
- return;
- case REG_DISPB_BG1CNT :
- //GPULOG("SUB BG1 SETPROP 16B %08X\r\n", val);
- GPU_setBGProp(SubScreen.gpu, 1, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x100A, val);
- return;
- case REG_DISPB_BG2CNT :
- //GPULOG("SUB BG2 SETPROP 16B %08X\r\n", val);
- GPU_setBGProp(SubScreen.gpu, 2, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x100C, val);
- return;
- case REG_DISPB_BG3CNT :
- //GPULOG("SUB BG3 SETPROP 16B %08X\r\n", val);
- GPU_setBGProp(SubScreen.gpu, 3, val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x100E, val);
- return;
-
- case REG_VRAMCNTA:
- case REG_VRAMCNTC:
- case REG_VRAMCNTE:
- MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
- MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, val >> 8);
- return;
- case REG_VRAMCNTG:
- MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
- /* Update WRAMSTAT at the ARM7 side */
- T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x241, val >> 8);
- return;
- case REG_VRAMCNTH:
- MMU_VRAMmapControl(adr-REG_VRAMCNTA, val & 0xFF);
- MMU_VRAMmapControl(adr-REG_VRAMCNTA+1, val >> 8);
- return;
-
- case REG_IME:
- {
- u32 old_val = MMU.reg_IME[ARMCPU_ARM9];
- u32 new_val = val & 0x01;
- MMU.reg_IME[ARMCPU_ARM9] = new_val;
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x208, val);
-#ifndef NEW_IRQ
- if ( new_val && old_val != new_val)
- {
- // raise an interrupt request to the CPU if needed
- if ( MMU.reg_IE[ARMCPU_ARM9] & MMU.reg_IF[ARMCPU_ARM9])
- {
- NDS_ARM9.wIRQ = TRUE;
- NDS_ARM9.waitIRQ = FALSE;
- }
- }
-#endif
- return;
- }
- case REG_IE :
- MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9]&0xFFFF0000) | val;
-#ifndef NEW_IRQ
- if ( MMU.reg_IME[ARMCPU_ARM9])
- {
- // raise an interrupt request to the CPU if needed
- if ( MMU.reg_IE[ARMCPU_ARM9] & MMU.reg_IF[ARMCPU_ARM9])
- {
- NDS_ARM9.wIRQ = TRUE;
- NDS_ARM9.waitIRQ = FALSE;
- }
- }
-#endif
- return;
- case REG_IE + 2 :
- MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9]&0xFFFF) | (((u32)val)<<16);
-#ifndef NEW_IRQ
- if ( MMU.reg_IME[ARMCPU_ARM9])
- {
- // raise an interrupt request to the CPU if needed
- if ( MMU.reg_IE[ARMCPU_ARM9] & MMU.reg_IF[ARMCPU_ARM9])
- {
- NDS_ARM9.wIRQ = TRUE;
- NDS_ARM9.waitIRQ = FALSE;
- }
- }
-#endif
- return;
-
- case REG_IF :
- MMU.reg_IF[ARMCPU_ARM9] &= (~((u32)val));
- return;
- case REG_IF + 2 :
- MMU.reg_IF[ARMCPU_ARM9] &= (~(((u32)val)<<16));
- return;
-
- case REG_IPCSYNC :
- MMU_IPCSync(ARMCPU_ARM9, val);
- return;
-
- case REG_IPCFIFOCNT :
- IPC_FIFOcnt(ARMCPU_ARM9, val);
- return;
- case REG_TM0CNTL :
- case REG_TM1CNTL :
- case REG_TM2CNTL :
- case REG_TM3CNTL :
- MMU.timerReload[ARMCPU_ARM9][(adr>>2)&3] = val;
- return;
- case REG_TM0CNTH :
- case REG_TM1CNTH :
- case REG_TM2CNTH :
- case REG_TM3CNTH :
- {
- int timerIndex = ((adr-2)>>2)&0x3;
- int mask = ((val&0x80)>>7) << timerIndex;
- MMU.CheckTimers = (MMU.CheckTimers & (~mask)) | mask;
-
- if(val&0x80)
- MMU.timer[ARMCPU_ARM9][timerIndex] = MMU.timerReload[ARMCPU_ARM9][((adr-2)>>2)&0x3];
-
- MMU.timerON[ARMCPU_ARM9][((adr-2)>>2)&0x3] = val & 0x80;
-
- switch(val&7)
- {
- case 0 :
- MMU.timerMODE[ARMCPU_ARM9][timerIndex] = 0+1;//ARMCPU_ARM9;
- break;
- case 1 :
- MMU.timerMODE[ARMCPU_ARM9][timerIndex] = 6+1;//ARMCPU_ARM9;
- break;
- case 2 :
- MMU.timerMODE[ARMCPU_ARM9][timerIndex] = 8+1;//ARMCPU_ARM9;
- break;
- case 3 :
- MMU.timerMODE[ARMCPU_ARM9][timerIndex] = 10+1;//ARMCPU_ARM9;
- break;
- default :
- MMU.timerMODE[ARMCPU_ARM9][timerIndex] = 0xFFFF;
- break;
- }
-
- if(!(val & 0x80))
- MMU.timerRUN[ARMCPU_ARM9][timerIndex] = FALSE;
-
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & 0xFFF, val);
- return;
- }
-
- case REG_DISPA_DISPCNT :
- {
- u32 v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0) & 0xFFFF0000) | val;
- GPU_setVideoProp(MainScreen.gpu, v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0, v);
- return;
- }
- case REG_DISPA_DISPCNT+2 :
- {
- u32 v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0) & 0xFFFF) | ((u32) val << 16);
- GPU_setVideoProp(MainScreen.gpu, v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0, v);
- }
- return;
- case REG_DISPA_DISPCAPCNT :
- {
- u32 v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x64) & 0xFFFF0000) | val;
- GPU_set_DISPCAPCNT(val);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x64, v);
- return;
- }
- case REG_DISPA_DISPCAPCNT + 2:
- {
- u32 v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x64) & 0xFFFF) | val;
- GPU_set_DISPCAPCNT(val);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x64, v);
- return;
- }
-
- case REG_DISPB_DISPCNT :
- {
- u32 v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000) & 0xFFFF0000) | val;
- GPU_setVideoProp(SubScreen.gpu, v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000, v);
- return;
- }
- case REG_DISPB_DISPCNT+2 :
- {
- //emu_halt();
- u32 v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000) & 0xFFFF) | ((u32) val << 16);
- GPU_setVideoProp(SubScreen.gpu, v);
- T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000, v);
- return;
- }
- case REG_DMA0CNTH :
- {
- u32 v;
- //if(val&0x8000) emu_halt();
- //LOG("16 bit dma0 %04X\r\n", val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xBA, val);
- DMASrc[ARMCPU_ARM9][0] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xB0);
- DMADst[ARMCPU_ARM9][0] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xB4);
- v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xB8);
- MMU.DMAStartTime[ARMCPU_ARM9][0] = (v>>27) & 0x7;
- MMU.DMACrt[ARMCPU_ARM9][0] = v;
- if(MMU.DMAStartTime[ARMCPU_ARM9][0] == 0)
- MMU_doDMA(ARMCPU_ARM9, 0);
- #ifdef LOG_DMA2
- //else
- {
- LOG("ARMCPU_ARM9 %d, dma %d src %08X dst %08X %s\r\n", ARMCPU_ARM9, 0, DMASrc[ARMCPU_ARM9][0], DMADst[ARMCPU_ARM9][0], (val&(1<<25))?"ON":"OFF");
- }
- #endif
- }
- return;
- case REG_DMA1CNTH :
- {
- u32 v;
- //if(val&0x8000) emu_halt();
- //LOG("16 bit dma1 %04X\r\n", val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC6, val);
- DMASrc[ARMCPU_ARM9][1] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xBC);
- DMASrc[ARMCPU_ARM9][1] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC0);
- v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC4);
- MMU.DMAStartTime[ARMCPU_ARM9][1] = (v>>27) & 0x7;
- MMU.DMACrt[ARMCPU_ARM9][1] = v;
- if(MMU.DMAStartTime[ARMCPU_ARM9][1] == 0)
- MMU_doDMA(ARMCPU_ARM9, 1);
- #ifdef LOG_DMA2
- //else
- {
- LOG("ARMCPU_ARM9 %d, dma %d src %08X dst %08X %s\r\n", ARMCPU_ARM9, 1, DMASrc[ARMCPU_ARM9][1], DMADst[ARMCPU_ARM9][1], (val&(1<<25))?"ON":"OFF");
- }
- #endif
- }
- return;
- case REG_DMA2CNTH :
- {
- u32 v;
- //if(val&0x8000) emu_halt();
- //LOG("16 bit dma2 %04X\r\n", val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xD2, val);
- DMASrc[ARMCPU_ARM9][2] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC8);
- DMASrc[ARMCPU_ARM9][2] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xCC);
- v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xD0);
- MMU.DMAStartTime[ARMCPU_ARM9][2] = (v>>27) & 0x7;
- MMU.DMACrt[ARMCPU_ARM9][2] = v;
- if(MMU.DMAStartTime[ARMCPU_ARM9][2] == 0)
- MMU_doDMA(ARMCPU_ARM9, 2);
- #ifdef LOG_DMA2
- //else
- {
- LOG("ARMCPU_ARM9 %d, dma %d src %08X dst %08X %s\r\n", ARMCPU_ARM9, 2, DMASrc[ARMCPU_ARM9][2], DMADst[ARMCPU_ARM9][2], (val&(1<<25))?"ON":"OFF");
- }
- #endif
- }
- return;
- case REG_DMA3CNTH :
- {
- u32 v;
- //if(val&0x8000) emu_halt();
- //LOG("16 bit dma3 %04X\r\n", val);
- T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xDE, val);
- DMASrc[ARMCPU_ARM9][3] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xD4);
- DMASrc[ARMCPU_ARM9][3] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xD8);
- v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xDC);
- MMU.DMAStartTime[ARMCPU_ARM9][3] = (v>>27) & 0x7;
- MMU.DMACrt[ARMCPU_ARM9][3] = v;
-
- if(MMU.DMAStartTime[ARMCPU_ARM9][3] == 0)
- MMU_doDMA(ARMCPU_ARM9, 3);
- #ifdef LOG_DMA2
- //else
- {
- LOG("ARMCPU_ARM9 %d, dma %d src %08X dst %08X %s\r\n", ARMCPU_ARM9, 3, DMASrc[A...
[truncated message content] |
|
From: <ric...@us...> - 2008-12-28 15:01:25
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Revision: 1271
http://desmume.svn.sourceforge.net/desmume/?rev=1271&view=rev
Author: riccardom
Date: 2008-12-28 15:01:16 +0000 (Sun, 28 Dec 2008)
Log Message:
-----------
Made two functions static a put parentheses around | operand as suggested by gcc.
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-28 14:53:57 UTC (rev 1270)
+++ trunk/desmume/src/MMU.cpp 2008-12-28 15:01:16 UTC (rev 1271)
@@ -708,7 +708,7 @@
}
char txt[80];
-void execsqrt() {
+static void execsqrt() {
u32 ret;
u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0);
switch(cnt&1)
@@ -733,7 +733,7 @@
MMU.sqrtRunning = TRUE;
}
-void execdiv() {
+static void execdiv() {
u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280);
s64 num,den;
s64 res,mod;
@@ -1587,7 +1587,7 @@
u32 IPCSYNC_remote = T1ReadLong(MMU.MMU_MEM[proc^1][0x40], 0x180);
IPCSYNC_local = (IPCSYNC_local&0x6000)|(val&0xf00)|(IPCSYNC_local&0xf);
- IPCSYNC_remote =(IPCSYNC_remote&0x6f00)|(val>>8)&0xf;
+ IPCSYNC_remote =(IPCSYNC_remote&0x6f00)|((val>>8)&0xf);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x180, IPCSYNC_local);
T1WriteLong(MMU.MMU_MEM[proc^1][0x40], 0x180, IPCSYNC_remote);
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From: <ric...@us...> - 2008-12-30 16:32:29
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Revision: 1320
http://desmume.svn.sourceforge.net/desmume/?rev=1320&view=rev
Author: riccardom
Date: 2008-12-30 16:32:26 +0000 (Tue, 30 Dec 2008)
Log Message:
-----------
Rework conditionals in execsqrt() and execdiv() so that gcc stop saying that ret, den and num can be used uninitialized. I assume that all the possibile value of the test are already there otherwise these changes are wrong! :)
Modified Paths:
--------------
trunk/desmume/src/MMU.cpp
Modified: trunk/desmume/src/MMU.cpp
===================================================================
--- trunk/desmume/src/MMU.cpp 2008-12-30 16:16:31 UTC (rev 1319)
+++ trunk/desmume/src/MMU.cpp 2008-12-30 16:32:26 UTC (rev 1320)
@@ -756,18 +756,13 @@
static void execsqrt() {
u32 ret;
u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0);
- switch(cnt&1)
- {
- case 0: {
- u32 v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
- ret = isqrt(v);
- break;
- }
- case 1: {
+
+ if (cnt&1) {
u64 v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
ret = isqrt(v);
- break;
- }
+ } else {
+ u32 v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
+ ret = isqrt(v);
}
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B4, 0);
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0, cnt | 0x8000);
@@ -782,20 +777,22 @@
u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280);
s64 num,den;
s64 res,mod;
+
switch(cnt&3)
{
case 0:
num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
MMU.divCycles = (nds.cycles + 36);
- break;
- case 3: //gbatek says this is same as mode 1
+ break;
case 1:
+ case 3: //gbatek says this is same as mode 1
num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
MMU.divCycles = (nds.cycles + 68);
- break;
+ break;
case 2:
+ default:
num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
den = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
MMU.divCycles = (nds.cycles + 68);
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