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<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Recent changes to Rewriter</title><link>https://sourceforge.net/p/decompiler/wiki/Rewriter/</link><description>Recent changes to Rewriter</description><atom:link href="https://sourceforge.net/p/decompiler/wiki/Rewriter/feed" rel="self"/><language>en</language><lastBuildDate>Sun, 03 May 2015 18:02:34 -0000</lastBuildDate><atom:link href="https://sourceforge.net/p/decompiler/wiki/Rewriter/feed" rel="self" type="application/rss+xml"/><item><title>Rewriter modified by John Källén</title><link>https://sourceforge.net/p/decompiler/wiki/Rewriter/</link><description>&lt;div class="markdown_content"&gt;&lt;pre&gt;--- v1
+++ v2
@@ -1,4 +1,4 @@
-A **rewriter** is a class that transforms machine language instructions for a particular processor architecture into extremely simple Register Transfer Level (RTL) instructions. Many processor instructions have multiple side effects, and these need to be modeled accurately for the Decompiler to be able to reconstruct a reasonably faithful source version.
+A **rewriter** is a class that transforms machine language instructions for a particular processor architecture into extremely simple [Register Transfer Language] (RTL) instructions. Many processor instructions have multiple side effects, and these need to be modeled accurately for the Decompiler to be able to reconstruct a reasonably faithful source version.

 The rewriter for a particular architecture is an implementation of `IEnumerable&amp;lt;RtlInstructionCluster&amp;gt;`. That is, it can be viewed as the source of a stream of `RtlInstructionCluster`s. Each `RtlInstructionCluster` corresponds to a single machine code instruction, and consists of the address of the instruction, its size (remember that many processor architectures have variable-sized instructions -- see VAX, 8080, 68000, x86 and ARM Thumb for examples), and **one or more** `RtlInstruction`s which,  when executed, model the behavior of the machine instruction.

&lt;/pre&gt;
&lt;/div&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">John Källén</dc:creator><pubDate>Sun, 03 May 2015 18:02:34 -0000</pubDate><guid>https://sourceforge.net8248a9160af6e4338dea0d7b0b5af60dbe6a5e91</guid></item><item><title>Rewriter modified by John Källén</title><link>https://sourceforge.net/p/decompiler/wiki/Rewriter/</link><description>&lt;div class="markdown_content"&gt;&lt;p&gt;A &lt;strong&gt;rewriter&lt;/strong&gt; is a class that transforms machine language instructions for a particular processor architecture into extremely simple Register Transfer Level (RTL) instructions. Many processor instructions have multiple side effects, and these need to be modeled accurately for the Decompiler to be able to reconstruct a reasonably faithful source version.&lt;/p&gt;
&lt;p&gt;The rewriter for a particular architecture is an implementation of &lt;code&gt;IEnumerable&amp;lt;RtlInstructionCluster&amp;gt;&lt;/code&gt;. That is, it can be viewed as the source of a stream of &lt;code&gt;RtlInstructionCluster&lt;/code&gt;s. Each &lt;code&gt;RtlInstructionCluster&lt;/code&gt; corresponds to a single machine code instruction, and consists of the address of the instruction, its size (remember that many processor architectures have variable-sized instructions -- see VAX, 8080, 68000, x86 and ARM Thumb for examples), and &lt;strong&gt;one or more&lt;/strong&gt; &lt;code&gt;RtlInstruction&lt;/code&gt;s which,  when executed, model the behavior of the machine instruction.&lt;/p&gt;
&lt;p&gt;As an example, the x86 Rewriter will take the following x86 machine instruction&lt;/p&gt;
&lt;div class="codehilite"&gt;&lt;pre&gt;add eax,[ebx+esi*4+0x204]
&lt;/pre&gt;&lt;/div&gt;
&lt;p&gt;and rewrite it into:&lt;/p&gt;
&lt;div class="codehilite"&gt;&lt;pre&gt;eax = eax + Mem0[ebx + esi * 4 + 0x0204:word32]
SZCO = cond(eax)
&lt;/pre&gt;&lt;/div&gt;
&lt;p&gt;As you can see, it has translated the machine code instruction into its RTL equivalent. First, the main effect of the instruction is to add a memory value to the current value of the &lt;code&gt;eax&lt;/code&gt; register. The effective address of the memory instruction has been transformed into an RTL expression. Then the effective address is used inside of a &lt;code&gt;MemoryAccess&lt;/code&gt; expression, which also has been given a &lt;code&gt;word32&lt;/code&gt; as the size of the memory access. &lt;/p&gt;
&lt;p&gt;However, the x86 &lt;code&gt;add&lt;/code&gt; instruction also affects the condition codes. Therefore, the rewriter must also emit a statement to model this. The second RTL instruction in the cluster assigns the &lt;code&gt;S&lt;/code&gt;, &lt;code&gt;Z&lt;/code&gt;, &lt;code&gt;C&lt;/code&gt;, and &lt;code&gt;O&lt;/code&gt; flags (sign, zero, carry, and overflow, respectively) with the result of applying the pseudo-function &lt;code&gt;cond&lt;/code&gt; to the result of the addition operation. The &lt;span&gt;[condition code elimination]&lt;/span&gt; stage of the decompiler will replace processor flag references and &lt;code&gt;cond&lt;/code&gt; applications with higher-level constructs.&lt;/p&gt;&lt;/div&gt;</description><dc:creator xmlns:dc="http://purl.org/dc/elements/1.1/">John Källén</dc:creator><pubDate>Sun, 03 May 2015 17:48:08 -0000</pubDate><guid>https://sourceforge.net9f3d8c7de35ff868e351b5a2fa81e75157fb622e</guid></item></channel></rss>