#17 systemverilog support for ctags

open
nobody
None
5
2015-01-21
2010-05-13
No

Hi all,

I worked on a personal project last fall to develop a Systemverilog parser for ctags-5.8.

It supports most language features (based on the BNF from the IEEE 1800 spec draft). I\'ve been using it for actual development for the last few months and I can safely venture to call it beta quality.

I\'m not quite sure about the submission procedure and whether I need some sort of developer access to be able to checkin my changes? Could one of the existing developers perhaps point me the way?

As far as I can tell, no one else has been working on SV support -- I\'m willing to become a maintainer of this language support if warranted.
.
Thanks,
Vikram Khosa

Related

Support Requests: #17

Discussion

<< < 1 2 (Page 2 of 2)
  • Vikram Khosa

    Vikram Khosa - 2014-02-28

    Hi guys,

    Unfortunately, my professional and other commitments have left me little time to contribute to this effort all this while.

    I would like to resume helping out with enhancements and bug-fixes. However I don't expect to have enough solo bandwidth to get this to production quality -- Steve, Adam or anyone else interested, any help with development and/or validation would be appreciated.

    The parser was originally meant to be comprehensive (i.e. cover all of the language). However, I do agree with Steve -- there's a lot left to do (especially with the SV standard having evolved since I started).

    Regards,
    Vikram

     
    Last edit: Vikram Khosa 2014-05-05
  • Suresh Mathew

    Suresh Mathew - 2014-05-02

    I am more than happy to validate!

    On Thu, May 1, 2014 at 9:44 PM, Suresh Mathew sureshamathew@gmail.com wrote:

    Guys - any update on this?

    On Fri, Feb 28, 2014 at 4:42 PM, Steve snarum-micron@users.sf.net wrote:

    Sorry guys, I got sucked off on other priorities for a bit. I've got it back
    to compiling, but seem to have broken support for modules of all things! I
    was working on better support for classes and some of the more fancy things
    they can do, and ran into a problem telling the difference between a
    function prototype and an actual function declaration within the body of the
    class declaration. I probably broke modules in the process of messing with
    that part of the parser.


    [support-requests:#17] systemverilog support for ctags

    Status: open
    Group:

    Created: Thu May 13, 2010 03:53 AM UTC by Vikram Khosa
    Last Updated: Fri Feb 28, 2014 12:00 AM UTC
    Owner: nobody

    Hi all,

    I worked on a personal project last fall to develop a Systemverilog parser
    for ctags-5.8.

    It supports most language features (based on the BNF from the IEEE 1800 spec
    draft). I\'ve been using it for actual development for the last few months
    and I can safely venture to call it beta quality.

    I\'m not quite sure about the submission procedure and whether I need some
    sort of developer access to be able to checkin my changes? Could one of the
    existing developers perhaps point me the way?

    As far as I can tell, no one else has been working on SV support -- I\'m
    willing to become a maintainer of this language support if warranted.
    .
    Thanks,
    Vikram Khosa


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    Related

    Support Requests: #17

  • Vitor Antunes

    Vitor Antunes - 2014-06-03

    Hi everyone,

    I have started extending the Verilog parser a bit, but I've been working in a github fork [1] of fishman's repository.
    Masatake has kindly pointed out this thread, to which I feel I can contribute.
    Since I don't want to wait for a github/sourceforge flow to be defined, I decided to reply directly to be able to receive comments from the verilog parser maintainers.

    At the moment I've only done the following:

    1. Implemented support for the new Verilog 2001 port declaration format.
      In these cases I've simply ommited the ports from the net declaration groups and only kept the port declaration itself.
    2. Added scope extraction, such that taglist like plugins can extract hierarchical information.
    3. Started extending the Verilog parser to be able to support SystemVerilog keywords.
      This one is still in a proof of concept state and would probably benefit from Vikram's work if we could somehow coordinate the merge of our work.

    I am not very experienced in C, so any suggestions originating from a code review are welcome.

    Until now I have only made a very brief check of Vikram's work and only have the following comments to make:

    1. I don't know if it makes sense to have a "undefined/global" in the scope. Why not use module/class/etc?
    2. Function/task ports/arguments are not extracted.

    I'll try to analyse Vikram's code in more detail as soon as I have some free time.

    As a final topic of discussion, I'd like to know if anyone has any ideas on how we can support dynamic types, like classes.

    [1] https://github.com/vhda/ctags

     
  • Steve

    Steve - 2014-06-04

    Vitor,

    I have a partial start in my working copy of class support. Unfortunately, it has stalled behind paying work. I'd be happy to have more people working on it, and am certainly interested in getting a single version merged rather than three partial ones.

    I think the first thing we need to figure out is, what is the official head, and how do we go about getting it updated? Official release 5.8 from 2009 is in serious need of update, and nobody seems to be interested / know / care about who owns this thing now, as Mr. Hiebert seems to have disappeared.

    ================================

    From: Vitor Antunes [mailto:vantunes@users.sf.net]
    Sent: Tuesday, June 03, 2014 11:46 AM
    To: [ctags:support-requests]
    Subject: [ctags:support-requests] #17 systemverilog support for ctags

    Hi everyone,
    I have started extending the Verilog parser a bit, but I've been working in a github fork [1] of fishman's repository.
    Masatake has kindly pointed out this thread, to which I feel I can contribute.
    Since I don't want to wait for a github/sourceforge flow to be defined, I decided to reply directly to be able to receive comments from the verilog parser maintainers.
    At the moment I've only done the following:
    1. Implemented support for the new Verilog 2001 port declaration format.
    In these cases I've simply ommited the ports from the net declaration groups and only kept the port declaration itself.
    2. Added scope extraction, such that taglist like plugins can extract hierarchical information.
    3. Started extending the Verilog parser to be able to support SystemVerilog keywords.
    This one is still in a proof of concept state and would probably benefit from Vikram's work if we could somehow coordinate the merge of our work.
    I am not very experienced in C, so any suggestions originating from a code review are welcome.
    Until now I have only made a very brief check of Vikram's work and only have the following comments to make:
    1. I don't know if it makes sense to have a "undefined/global" in the scope. Why not use module/class/etc?
    2. Function/task ports/arguments are not extracted.
    I'll try to analyse Vikram's code in more detail as soon as I have some free time.
    As a final topic of discussion, I'd like to know if anyone has any ideas on how we can support dynamic types, like classes.
    [1] https://github.com/vhda/ctags

     
  • Vitor Antunes

    Vitor Antunes - 2014-06-04

    Steve,

    I think we can do both things in parallel: we can start working towards a merge of our work and when we figure out the head of the code we rebase over it.
    My suggestion would be to work in github because there are other people already working in it. Do you think you would be able to apply your work on a github fork of fishman's repository? Please apply it over commit 1d395ed, which is before my work got merged.

    Vitor

     
  • Vitor Antunes

    Vitor Antunes - 2014-06-24

    Hi Steve,

    The github fork now includes the complete subversion tree merged into it (search for the git-svn tags in the commit descriptions). This should help tracking the differences between SF and github.

    I'm still looking forward to your review of my patches :)

    Vitor

     
  • MJ1

    MJ1 - 2015-01-21

    Hi,

    Just curious as to where this was left. Are there any implementations that are available for testing?

     
  • Vitor Antunes

    Vitor Antunes - 2015-01-21

    SystemVerilog support is implemented in exuberant-ctags github development area [1]. Note: this is different from the version provided by Vikram.

    [1] https://github.com/fishman/ctags

     
<< < 1 2 (Page 2 of 2)

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