#79 Add support for Verilog 2001

[Elias Wang]

In the following case, ctags generates wrong tags
// Signed arithmetic extension
reg signed [63:0] data;
// Combined port and data type declarations
output reg [7:0] y;
// ANSI-style input and output declarations
module mux8 (
output reg [7:0] y,
input wire [7:0] a,
input wire [7:0] b,
input wire en );

Reference: http://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf

[Elias Wang]

changes for supporting verilog 2001

[Elias Wang]

test case for this patch