This is a tested simple 32-bit MIPS CPU as described in the Patterson-Hennessy book "Computer Organization and Design". The CPU is tailored to run only a small subset of instructions (ADD,SUB,ADDI,SLT,BEQ,LW,SW) for initial training of students to formally described architectural blocks that make a simple CPU.

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CPUMIPS DATAPATH Timing Diagram for a small example of 15 MIPS instructions

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2018-10-20
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