Controlix virtual machine

The document describing the hierarchy of the Controlix virtual machine layers/sectors has been completely reworked and debugged. I think I've finally gotten it straight now, at least to a rough-grained degree. The first two layers are defined, which I think is enough to start working with in terms of actual VHDL code generation.

One major area left to define is the design of the assembly language parsed by the VM. It will need to reflect the core nature of the VHDL language, so I'll need to spend some time boning up on the IEEE STD documents that define the VHDL abstraction....

Edit: Don't know where my head went, but that document really describes the basic abstract classes. Also, Controlix uses GHDL which simulates a circuit, so therefore Controlix should really be described as a virtual circuit using OS, not a virtual machine OS.