Signaling and abstract types

After a few weeks of downtime for me, it is time to start working on Controlix again. This time I need to discuss an attempt to properly virtualize an aspect of the VHDL language - the type system, variables and signals.

First of all, we need to discuss what NOT to do, and that IMHO is to use much if any of the ADA-holdover standard types provided by VHDL. What is needed is to use the fundamental standard types 'bit' and 'bit_vector' as the basis upon which to construct another type system.