Controlix and SysML

So far, the design of the controls which make up the body of Controlix have been somewhat ad-hoc and limited to emulating networking hardware and a simple ASCII-based packeting motif. A more all-encompassing approach for the long term would be to specify and encourage the use of a more abstract set of forms which can encapsulate any software and hardware motif in systems as a whole. The logical choice here is the SysML systems modeling language, which is designed to model generic systems in an abstract sense. SysML defines a set of prototype form elements which are used to model systems in general.

Several SysML design tools already exist, but even the good ones like IBM's Rational or Eclipse's Papyrus are limited to combination of forms, and while these tools can generate C/C++ or VHDL source code from a SysML design, they don't allow the user to "punch down" through the system abstraction and directly encapsulate native code inside a given SysML element (i.e. they are not real integrated development environments). Given this restriction, it make sense to continue to work on the native-code level and write VHDL for systems code, as Controlix does. However, the library of standard SysML form elements can easily be viewed as a sort of "class library", which can be implemented directly as VHDL code (more specifically, as architecture blocks).