export to VHDL
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#23 export to VHDL
hello,
would it be feasible to add an option of converting a circuit to VHDL?
I understand it would be needed to add the support to all/most built-in and JAR libraries (if any subcomponent of x cannot be converted neiter can x). Moreover, circuits using tri-state logic may behave differently after the export (NAND gates emiting true instead of floating).
Another nice feature would be to import VHDL as components in logisim (load library / vhdl file...) but might be already possible via java components.
Thanks for listening,
Honnza
As you say, there would inevitably be some semantic differences between the Logisim simulation and the simulation of the exported VHDL file. I've thought about doing this with Verilog quite a bit, since that's what I'm most familiar with. One difficulty is translating Logisim's splitters, which don't have any directionality: Signals can travel both ways through them. The best Verilog equivalence I know requires them to be one-way (either splitting or combining), so any attempt at doing the translation would have to go through hoops to try to guess splitters' directionality. This could be done in a way that guesses correctly 99% of the time, but it can't be done perfectly. Another difference - where Verilog and VHDL are much stronger than Logisim - is in their multi-valued logic.
Anyway, I've been doing a lot of work with Logisim just recently, and I have a very long list of major features I'm hoping to implement this summer. While I agree that VHDL/Verilog support would also be a wonderful feature, it would be very work-intensive, and I'd have to scrub the other plans - which include a number of other highly requested features like editing how subcircuits are drawn (rather than just as a rectangle) and stretching wires when the selection is moved. If I get all that done, then VHDL/Verilog support would be next on my list. Maybe it will be something for my sabbatical, which will likely be at the end of 2010.
In the vein of HDL support, I have a related feature that is earlier on my list: I want to add some scripting feature, so a user could write code that includes Logisim-designed components and then test them. This would be useful in the classroom setting for testing circuits built for student assignments; but it would also be useful to others who want a way to script tests of their circuits. The scripting code would be a subset of Verilog (or maybe VHDL).
If this gets working, then the second feature you mention is the logical next step: Creating components by writing HDL code rather than by using the graphical interface. Then you could incorporate the HDL-specified component as a subcircuit in the graphical interface.