Hello. FOr educational puposes, I'm trying to create flip flops out of logic gates only. It worked fine for D type, but T and JK won't work. Am I doing something wrong, is it a limitation of the simulator, is there any known workaroud ?
Thnaks for helping :)
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You mean Project > Options > Simulation > Add noise to component delay ?
I tried with this option both enable or disable, it doesn't work...
I must be doing something wrong... Do you have an example of a working JK Flip Flop ?
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I think this is a good site and have some .circ projects
if you download the 5.4.3 JK Master-Slave Flip-Flop Schematic Diagram
Read the note:
"
although this is a viable circuit using real IC's Logisim can have problems initializing this circuit (see Help>User's Guide> Value Propagation> Shortcomings)
If conductors are initially RED (indicating error values when simulation is initialized this can be remedied by making sure all inputs are at logic 0, temporarily disconnecting (deleting) and reconnecting the bottom input to G3 (marked X)
"
The Latch part needs to be initialized seems like to make it work set all inputs to 0 and delete the little wire from G3 to X, all the wires will urn green and the circuit will work.
Last edit: random 2017-02-09
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I don't understand what you want to do, the leftmost transistor will output undefined because the input pin is 0, the other will output error because it's connected to an undefined value
Last edit: Logisim IT 2017-07-18
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Hello. FOr educational puposes, I'm trying to create flip flops out of logic gates only. It worked fine for D type, but T and JK won't work. Am I doing something wrong, is it a limitation of the simulator, is there any known workaroud ?
Thnaks for helping :)
You have to give it an initial state, i suggest you a clear or preset
did you check the 'noice' option ?
You mean Project > Options > Simulation > Add noise to component delay ?
I tried with this option both enable or disable, it doesn't work...
I must be doing something wrong... Do you have an example of a working JK Flip Flop ?
maybe there is an oscilation error.. uncheck simulation enable, then reset it, after the cables are blue, enable sim again...
http://www.learnabout-electronics.org/Digital/dig54.php
I think this is a good site and have some .circ projects
if you download the 5.4.3 JK Master-Slave Flip-Flop Schematic Diagram
Read the note:
"
"
The Latch part needs to be initialized seems like to make it work set all inputs to 0 and delete the little wire from G3 to X, all the wires will urn green and the circuit will work.
Last edit: random 2017-02-09
Hi everyone,
I designed two or latch, one with or gate, and other one with transistors, but the one i designed with transistors wont work as expected.
I've tried and thought so much time to find bug but I couldn't !!!
Can anyone please tell me if it has a logical problem or "logisim" cause that problem ?
here is the image :
http://imgur.com/a/B4p36
I used "logisim" app to create these circuits.
Last edit: strong 2017-07-07
I don't understand what you want to do, the leftmost transistor will output undefined because the input pin is 0, the other will output error because it's connected to an undefined value
Last edit: Logisim IT 2017-07-18