Help please, I'm a student in a technical university and it is very important to get the task done.
10111 - Code
Design a synchronous sequential circuit with input x and output y with the following behavior: the output y is always 1 if (the initial state) of the input sequence sequence occurs ...... .
In memory of Use minimum number of bistable circuits D - PO,
in the combination of a minimum number of logic gates NAND.
Custom Solution Verify program means ESPRESSO (minimizing functions) and
LOG, LogiSim, FitBoard (designed to draw the logical schema using TTL library and check motion simulation).
Im sorry for my bad english)!I'm from Slovakia
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Help please, I'm a student in a technical university and it is very important to get the task done.
10111 - Code
Design a synchronous sequential circuit with input x and output y with the following behavior: the output y is always 1 if (the initial state) of the input sequence sequence occurs ...... .
In memory of Use minimum number of bistable circuits D - PO,
in the combination of a minimum number of logic gates NAND.
Custom Solution Verify program means ESPRESSO (minimizing functions) and
LOG, LogiSim, FitBoard (designed to draw the logical schema using TTL library and check motion simulation).
Im sorry for my bad english)!I'm from Slovakia