A .circ file with steps to produce four logisim bugs
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4 logisim bugs
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ad bug1: I could not reproduce it but I could imagine an oscillation easily.
ad bug2: actually both outputs are equally likely and equally (il)legitimate. Floating state is neither 0 nor 1.
ad bug3: This is not a bug, it's a design flaw (the circuit is an active low SR latch. 0-0 means off, 1-1 means hold output). Sometimes the latch is designed to break the ties.
This is not a software bug since a physical device would misbehave too.
I agree the software sould intruduce random delays to destabilise such oscillations.
ad bug4:this happens in real devices, too. The most usual solution is to ignore random peaks (an RC quasiintegrator will smooth out such peaks), to design a gate such that one bit input changes will not produce such peaks or to use a clocked logic.