#654 nvicEnableVector broken for Cortex-M0

[Stephen Caudle]

nvicEnableVector and nvicDisableVector are broken for Cortex-M0 chips. The NVIC->IP register is byte addressable for Cortex-M3, but only word addressable for Cortex-M0. See section 4.2.6 in the Cortex-M0 Devices Generic User Guide versus section 4.2.7 of the Cortex-M3 Devices Generic User Guide.

nvicSetSystemHandlerPriority is also broken for Cortex-M0. The attached patch only addresses the bug with nvicEnableVector/nvicDisableVector. Feel free to implement this however you'd like.

[Stephen Caudle]

Sorry, I should have been more specific ... the thing that is broken for Cortex-M0 is the setting of the interrupt priority only. The interrupts are enabled properly, but their corresponding priority bits are not set properly.

[Giovanni Di Sirio]

Hi,

Thanks for fining, the code was fine in 2.6.x. I fixed it by using the same CMSIS macros in nvic.c but without using CMSIS functions because handler indexes are unsigned in ChibiOS.

Please let me know if you see problems in the fix.

Giovanni