I tried to help write SystemVerilog parser for semantic athttp://sourceforge.net/projects/wisentsverilog/
As I recall this project stalled due to Andrea, the project leader, and me not
being able to get our emacs to behave the same. I use emacs 24.3, as well as
my own build of emacs from source code at git://git.savannah.gnu.org/emacs.git
I use GNU/Linux only; no windows.
I'm still interested in getting this thing done, because many of my colleagues
would love to use this. If you would like to take the lead, then I can help
you with writing parser and documenting not only the parser, but also
SystemVerilog itself in texinfo so that it can be hooked up to emacs via
My software experience is with C++, python, and emacs-lisp among others.
However I don't know SystemVerilog or other hardware description languages. My
contribution would be in helping write the parser as well as in documentation.
I have experience in writing parsers using bison as well as semantic, e.g., I
wrote the original python parser for semantic about 12 years ago.
Let me know if you are interested in bringing up SystemVerilog parser.