I'm definitely interested. Thanks! I'll take a look.

My experience is varied. Since I'm starting to hack emacs more and more (and since I have been looking to get SV support in CEDET) I've been getting more and more familiar with emacs lisp. I've a lot of experience with C++ and other C-style languages, scripting with Perl and Bash, and so forth. Python is on my radar these days though. 😊

My day job is as a design verification engineer, so I'm working within SystemVerilog (and UVM, lately) quite often. I am on Linux most of the time for work, though I am on Windows at home most of the time. Anything I do as a hobby at home is using emacs-w32 or emacs on Cygwin/X11.

I'm on the latest packages as a habit at home, and have a built-from-source version of emacs 24.3 at work. I would be testing it on both, as time allows.

I'm glad to see there are things in place already! I hope we can get things moving on this!


Benjamin Richards

Sent from Surface Pro

From: Richard Kim
Sent: ‎Monday‎, ‎June‎ ‎9‎, ‎2014 ‎11‎:‎15‎ ‎PM
To: Ben Richards
Cc: cedet-devel@lists.sourceforge.net

I tried to help write SystemVerilog parser for semantic at

As I recall this project stalled due to Andrea, the project leader, and me not
being able to get our emacs to behave the same.  I use emacs 24.3, as well as
my own build of emacs from source code at git://git.savannah.gnu.org/emacs.git.
I use GNU/Linux only; no windows.

I'm still interested in getting this thing done, because many of my colleagues
would love to use this.  If you would like to take the lead, then I can help
you with writing parser and documenting not only the parser, but also
SystemVerilog itself in texinfo so that it can be hooked up to emacs via

My software experience is with C++, python, and emacs-lisp among others.
However I don't know SystemVerilog or other hardware description languages.  My
contribution would be in helping write the parser as well as in documentation.
I have experience in writing parsers using bison as well as semantic, e.g., I
wrote the original python parser for semantic about 12 years ago.

Let me know if you are interested in bringing up SystemVerilog parser.

On 7 June 2014 17:55, <benjamin.richards86@gmail.com> wrote:
Hi, I have been looking around but haven’t seen decent support for SystemVerilog anywhere. I know there is Verilog support already but it doesn’t get me very far with being able to use CEDET’s feature set. So, I’m starting to think about doing it, myself. I already have some hacked in support using a regex language definition for CTAGS but that obviously has its limitations. Before I actually start with this project, I was wondering if anyone else already was working on something to this effect, and if so, if it is already available somewhere.

Also, I was wondering if my work for adding support should exist in any particular repository or if I can do this in my own repo (probably to be published to github) and that it can be merged back to CEDET’s repo later on, when it reaches a stable point?


Benjamin Richards

Sent from Surface Pro

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