I just wanted to say Thanks for this software; it has been hugely useful to me in my beginning logic design / computer architecture course. It honestly has really brought this topic to life for me, being able to visualize circuits like this! It's easy to use, too.
I hope you will keep up development on it.
Thanks! And thanks for reporting that bug with the adder, too. Just a quick survey-question: Did you find the program easy to figure out and get started with? Did you use the help tutorials to find out how the interface worked?
Yes, I found it really easy & intuitive. (I have a background in CAD, so that helps, but still it was quite easy.) I found the software in the late morning, and had prepared a sequential logic design exercise for my class by the same afternoon.
I just started playing around with the interface; I never even touched the tutorial. The only things I needed to go into the documentation to figure out were:
- Disconnecting wires
- How to use the To & From components
- How the paging system works
- Finding the O-Scope
The "palletes at the left" thing is pretty standard and straightforward to figure out. The first thing I tried was dragging gates from the pallete to the work area, which is just how it was desinged. And having the small red box light up at the connection points when you mouse over them was a good hint that I could make conenctions by clicking there.
I guess some indication of which components can be adjusted by double-clicking would help, though I figured that out by experimenting too. It's maybe slightly counterintuitive to adjust the properties by double-clicking and rotate by right-clicking (which seems to make a mess of the wiring, by the way). I would have done it as: adjust properties by right-clicking and maybe have a toolbar button for Rotate.
But that's a nitpicky issue. Really it's very easy to use. The documentation is pretty thorough, too, for a project at this stage.
I've been promoting CEDAR to my classmates & instructor, so hopefully you'll get some more testers soon. I just wish I had found it earlier than the last week of class; it really, really helped my understanding of this topic.
Oh yeah, one other thing:
I didn't find any documentation of what the time slider does.
I mean, obviously it controls the speed of the simulation, but what exactly do the "ms" numbers to the right of it mean? Is it some kind of scale, like 1 real sec.=50 simulation milliseconds, or what?
The time slider is how many milliseconds of real time pass between each "gate delay" (Which should be around 5ns in real NPN logic). Each gate all has the same gate delay currently. It is there so that you can slow the simulation down to see how the signal propagates through your circuit (as most people starting out learning digital logic don't realize that there is in fact gate delay), and so you can debug timing errors when signals arrive at different times.
Just to say I am running CEDAR on linux ubuntu using wine. Only problem is the help does not work (but I converted the .chm file to pdf).
An excellent bit of software. I intend to use it to teach. I am currently building a very simple virtual 4bit microprocessor.
For your feedback I only referred to the help to find some of the pin assignments. It seems to do exactly what I want in an intuitive :-)
Only thing I have not figured out is why I need 5 clicks to step one cycle (I could see why 2 or 4) !!!!
Hey Lovely software.
Has anyone thought of how a generic monostable multivibrator could be added. Or am I missing something? I need to sim a couple of circuits with LS123 and LS221 in them.
Also a three way link would be nice :) Here is the one I created by hacking the 4 way one :)
Wanted to say that this is a job well done
I'm currently using this to simulate some 35yr old designs
I like how it's clean-cut and low overhead.
And very intuitive.
I saw somewhere that it's possible to simulate the Gate Delays ?
I might be mistaken.
I wondered about the Write Clock input on the RAM modules.
This is somewhat awkward - as most Ram devices don't have a Write Clock input.
The data is typically latched on a Write operation, eg. TTL 74373
I see the symbol for this model is updated in the Help file.
But not the description - but it also doesn't mention about the Write Clock input
I can see in the *.lib file that the DATA IN pins were commented out.
But if I edit the cl_gatedefs.lib
and comment out the Write Clock input
then it should show up component panel [left side] with any Write Clock input
I imagine this is all transparent to the simulation engine
So if there were no Write Clock input in that RAM model
Then it won't simulate this signal
I was going to give this a try
I supposed you have already finished college
So there might not be any further updates ?
keep up the great work !
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