From: Derrick M. <der...@gm...> - 2019-07-31 12:37:53
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The idea is to make the generation of the needed inc file less of a black box, and ensure that it is properly ordered. On Wed, Jul 31, 2019, 06:42 Nguyen Anh Quynh <aq...@gm...> wrote: > > > On Tue, Jul 30, 2019, 23:07 Derrick McKee <der...@gm...> wrote: > >> So, looking closer at the existing MappingInsnOp.inc files, it looks like >> my proposed YAML format is not suitable. So instead I propose the following: >> >> output: "MipMappingInsnOp.inc" >> Insns: >> - enum: MIPS_INS_ABSQ_S >> subtypes: >> - examples: { >> Mips_ABSQ_S_PH: "ABSQ_S.PH rd, rt", >> Mips_ABSQ_S_QB: "ABSQ_S.QB rd, rt", >> Mips_ABSQ_S_W: "ABSQ_S.W rd, rt" >> } >> operands: >> - read: No >> write: Yes >> - read: Yes >> write: No >> > > Yes sounds good. > > But how does this make it better than current .inc format? A bit more > readability, but not too much to me. > > > >> >> On Tue, Jul 30, 2019 at 8:45 AM Derrick McKee <der...@gm...> >> wrote: >> >>> I think I am mostly done with the C implementation, and have updated the >>> bindings. I just need to generate the {Mips,PPC}MappingInsnOp.inc files. >>> The existing files for ARM and x86 seem to contain the read/write >>> information for every instruction, sorted by enum name. They also say that >>> they were autogenerated, but I guess that isn't quite correct. I am >>> thinking that I can write a Python script that reads in a YAML file, and >>> outputs the properly sorted inc file containing all the information >>> (including comments) currently in existing InsnOp.inc files. The YAML file >>> will have a structure like the following: >>> >>> output: "MipsMappingInsnOp.inc" >>> Insns: >>> - enum: MIPS_INS_ADD >>> example: "add $d, $t, $s" >>> operands: >>> - read: No >>> write: Yes >>> - read: Yes >>> write: No >>> - read: Yes >>> write: No >>> >>> Thoughts? >>> >>> On Tue, Jul 30, 2019 at 1:24 AM Nguyen Anh Quynh <aq...@gm...> >>> wrote: >>> >>>> Those .inc files involved a lot of manual work, that is why it takes >>>> time. >>>> >>>> What is your progress? >>>> >>>> Cheers. >>>> >>>> On Mon, Jul 29, 2019, 23:47 Derrick McKee <der...@gm...> >>>> wrote: >>>> >>>>> Hi, >>>>> >>>>> I am beginning to add support for regs_access for MIPS and PPC. >>>>> Currently, I am following what has been done for ARM and x86, which as far >>>>> as I can tell for PPC involves adding a new access member to the >>>>> cs_ppc_op struct, writing a new PPC_regs_access function, and setting >>>>> the regs_access function pointer in cs_struct in PPC_global_init. My >>>>> question is how is the access member set? For both ARM and x86, there is a >>>>> MappingInsnOp.inc file that appears to be autogenerated, which contains the >>>>> access information. How was this file generated? >>>>> >>>>> -- >>>>> Derrick McKee >>>>> Phone: (703) 957-9362 >>>>> Email: der...@gm... >>>>> _______________________________________________ >>>>> Capstone-users mailing list >>>>> Cap...@li... >>>>> https://lists.sourceforge.net/lists/listinfo/capstone-users >>>>> >>>> _______________________________________________ >>>> Capstone-users mailing list >>>> Cap...@li... >>>> https://lists.sourceforge.net/lists/listinfo/capstone-users >>>> >>> >>> >>> -- >>> Derrick McKee >>> Phone: (703) 957-9362 >>> Email: der...@gm... >>> >> >> >> -- >> Derrick McKee >> Phone: (703) 957-9362 >> Email: der...@gm... >> _______________________________________________ >> Capstone-users mailing list >> Cap...@li... >> https://lists.sourceforge.net/lists/listinfo/capstone-users >> > _______________________________________________ > Capstone-users mailing list > Cap...@li... > https://lists.sourceforge.net/lists/listinfo/capstone-users > |