Re: [Capstone-users] Capstone support for AMD instructions, Power 8 & 9 vector instructions, and ARM SVE instructions

[Xiaozhu M. <mx...@gm...>]

Hi Quynh,

Thanks for your reply!

I have 8 AVX instructions that are currently missing in Dyninst. I tried Capstone’s master branch and it correctly decodes 7 of the 8. For the remaining one, I would like double check with you whether the test itself is correct.

The bytes are "0x62, 0xd2, 0xf5, 0x78, 0xb8, 0xd1”. I am using the test1 example from the capstone c tutorial and it prints ""ERROR: Failed to disassemble given code!” for this one. Objdump says these bytes is "vfmadd231pd {rz-sae},%zmm9,%zmm1,%zmm2”.

I have to admit that this is something we collected about two years ago, and I cannot confirm from which binary I got them. So, I am not sure that whether my recorded test is actually correct or not. In general, it looks very promising for integrating capstone with Dyninst. I will send followup emails if I need further help.

Thanks,

—Xiaozhu




> On Jun 3, 2019, at 9:57 PM, Nguyen Anh Quynh <aq...@gm...> wrote:
> 
> hi,
> 
> On Mon, Jun 3, 2019 at 11:15 PM Xiaozhu Meng <mx...@gm... <mailto:mx...@gm...>> wrote:
> Hi,
> 
> I am a developer from the Dyninst project (https://github.com/dyninst/dyninst <https://github.com/dyninst/dyninst>). For a long time, Dyninst has its own instruction decoder. However, we have been falling behind on instruction decoding in recent years, due to our focuses on binary analysis and instrumentation. We are considering integrating with external instruction decoder to better support our binary analysis and instrumentation functionality. Dyninst's main target architectures are x86, Power, and ARM. 
> 
> yes, i understand the pain of maintaining/developing a subproject which is as complicated as disassembler. 
> using a third party instead is a smart approach, IMO.
>  
> 
> Capstone is a good candidate we are considering because it covers the three main architectures we are supporting and provides thread-safe instruction decoding (Dyninst's parallel binary analysis needs thread-safe instruction decoder). 
> 
> I have a couple of specific questions on this topic:
> 
> (1) Dyninst's own instruction decoder mainly failed on vector instructions, especially on AMD extensions such as XOP and FMA4 and ARM's SVE. We recently improved our decoder for Power vector instructions, but there are still many missing ones. How is capstone's current status for those different vector instructions?
> 
> check it out our "next" branch at https://github.com/aquynh/capstone/tree/next <https://github.com/aquynh/capstone/tree/next>
> in this branch, we support the latest instructions sets for X86, Arm & AArch64.
> as far as i know, we do not miss anything.
> 
> 
> 
> (2) Dyninst will need to translate Capstone's instruction decoding results from Capstone instruction representation to Dyninst instruction representation. We will need instruction length (how many bytes), instruction opcode, operands (both explicit and implicit operands), and operands types (such as IMM, mem, or register), and the addressing mode for constructing our AST representation for effective address. I believe Capstone provides all the information we need, but would like to confirm whether it is indeed the case.
> 
> yes, we can confirm that we provide these information for X86, Arm & Arm64.
> 
> 
> (3) I am aware that Capstone is thread-safe, which is great and necessary for us. I would like to ask whether there are going to any scalability concerns as we run Dyninst's parallel binary analysis on dozens to hundreds cores. 
> 
> 
> yes, Capstone is thread-safe by design. 
> 
> let me know if you need any helps integrating with Dyninst.
> 
> 
> Thanks,
> Quynh
> 
> http://www.keystone-engine.org <http://www.keystone-engine.org/>
> http://www.capstone-engine.org <http://www.capstone-engine.org/>
> http://www.unicorn-engine.org <http://www.unicorn-engine.org/>
> 
> 
> 
>  
> I am looking forward to hearing from you folks.
> 
> Thanks,
> 
> --Xiaozhu
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